CN118114317A

CN118114317A - Electronic system and method and device for managing memory

Info

Publication number: CN118114317A
Application number: CN202311628889.3A
Authority: CN
Inventors: 奥斯卡·P·平托; 威廉·马丁
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-11-30
Filing date: 2023-11-30
Publication date: 2024-05-31

Abstract

An electronic system and a method and apparatus for managing memory are provided. The method may comprise: receiving, by a controller, a command specifying an amount of computing resources and an amount of memory resources associated with a program; and processing, by the controller, the command, wherein the processing includes dynamically allocating a portion of the one or more computing resources and allocating a portion of the one or more memory resources for use by the program based on the command.

Description

Electronic system and method and device for managing memory

The present application claims the benefits of U.S. provisional patent application No. 63/429,125, entitled "mechanism for dynamic memory protection for program execution in a multi-tenant environment of computing storage device (A MECHANISM OF DYNAMIC MEMORY PROTECTIONS FOR PROGRAM EXECUTION IN A MULTI-TENANT ENVIRONMENT FOR COMPUTATIONAL STORAGE DEVICES)", filed 11/30 2022, and U.S. patent application No. 18/521,875, filed 11/28 2023, which are incorporated herein by reference for all purposes.

Technical Field

The disclosure relates generally to storage systems, and more particularly to systems and methods for memory protection of computing storage, and in particular to systems and methods for dynamic memory protection using program execution in a multi-tenant environment of computing storage.

Background

This background section is intended to provide background only and the disclosure of any concepts in this section is not an admission that such concepts are prior art.

As technology advances, the size and amount of data increases rapidly as data is collected by devices such as mobile devices, internet of things devices, aerial (remote sensing) devices, software logs, cameras, microphones, radio Frequency Identification (RFID) readers, wireless sensor networks, and the like. In order to process and use information represented by collected data, storage devices, processing elements, and servers are typically used in data centers to filter, calculate, store, and perform related operations on the data. There remains a need for systems and methods that improve computing functionality in storage devices.

The above information disclosed in this background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art.

Disclosure of Invention

In various embodiments, what is described herein includes systems, methods, and apparatus for computing memory protection for a storage device. In various aspects, the disclosed system describes a system for managing memory, the system comprising: a controller; one or more computing resources; and one or more memory resources. Furthermore, the system may be configured to: a command specifying an amount of computing resources and an amount of memory resources associated with a program is received. The system may process the command by a controller, wherein the processing may include dynamically allocating a portion of the one or more computing resources and allocating a portion of the one or more memory resources for use by the program based on the command. In other aspects, the command may specify that the portion of the one or more memory resources is restricted from access. In one aspect, the system determines that the program attempts to access a different region of the one or more memory resources than the allocated portion of the one or more memory resources and the system halts execution of the program. In some aspects, the one or more memory resources may include one or more local memory namespaces. In some aspects, the system may include one or more storage resources including one or more storage namespaces. In one aspect, the program is a first program in a multi-tenant environment that includes at least a second program. In other aspects, the commands may be based on a protocol including non-volatile memory express (NVMe). In one aspect, the one or more computing resources may include computing resources including at least one of a Central Processing Unit (CPU), a Graphics Processor (GPU), a Field Programmable Gate Array (FPGA), a Tensor Processor (TPU), or an Application Specific Integrated Circuit (ASIC). In some aspects, the computing storage may include storage that supports non-volatile memory express (NVMe).

Corresponding methods, apparatus and computer readable media are described.

As shown, the disclosed mechanisms may be applied to computing storage (e.g., storage with processing functionality) and related systems. In other aspects, the disclosed systems can be used in conjunction with any suitable storage device, such as non-volatile memory express (NVMe), structural NVMe (NVMe-orf), and/or non-NVMe (non-NVMe) Solid State Drives (SSDs). Furthermore, the disclosed systems and methods may be standardized and applied to a range of storage devices and related systems, without being known to the vendor.

Drawings

The above-mentioned and other aspects of the present technology will be better understood when the present application is read in light of the following drawings in which like reference numerals refer to similar or identical elements. Furthermore, the drawings are provided herein for the purpose of illustrating particular embodiments only; other embodiments that may not be explicitly described are not excluded from the scope of the present disclosure.

These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims, and appended drawings, wherein:

FIG. 1 illustrates a system including a computing storage unit that supports maintenance of storage devices according to a disclosed embodiment.

FIG. 2 shows details of the machine of FIG. 1, according to a disclosed embodiment.

Fig. 3A illustrates a first example arrangement of computing storage units that may be associated with the storage device of fig. 1, according to a disclosed embodiment.

Fig. 3B illustrates a second example arrangement of computing storage units that may be associated with the storage device of fig. 1, according to a disclosed embodiment.

Fig. 3C illustrates a third example arrangement of computing storage units that may be associated with the storage device of fig. 1, according to a disclosed embodiment.

Fig. 3D illustrates a fourth example arrangement of computing storage units that may be associated with the storage device of fig. 1, according to a disclosed embodiment.

FIG. 4 illustrates a computing storage device according to a disclosed example embodiment.

Fig. 5A illustrates fields specifying parameters that may be used to calculate memory protection of a storage device according to a disclosed example embodiment.

Fig. 5B illustrates another field specifying parameters that may be used to calculate memory protection of a storage device according to a disclosed example embodiment.

FIG. 6 illustrates a representation of a data pointer that may be used to compute memory protection of a storage device according to a disclosed example embodiment.

Fig. 7 is a diagram illustrating an exemplary operational flow of an exemplary operation associated with the disclosed system in accordance with the disclosed exemplary embodiment.

FIG. 8 illustrates an example schematic diagram of a system that may be used to practice embodiments of the present disclosure.

FIG. 9 illustrates an example schematic diagram of managing computing entities in accordance with a disclosed example embodiment.

Fig. 10 shows an example schematic diagram of a user device according to an example embodiment of the disclosure.

While the technology is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described. The drawings may not be to scale. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the technology to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present technology as defined by the appended claims.

Detailed Description

The details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

Various embodiments of the present disclosure now will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments are shown. Indeed, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term "or" is used herein in both the alternative and the connected sense, unless indicated otherwise. The terms "illustrative" and "example" are used for illustration and do not indicate a quality level. Like numbers refer to like elements throughout. The arrows in each figure depict bi-directional data flow and/or bi-directional data flow capabilities. The terms "path," "pathway," and "route" are used interchangeably herein.

Embodiments of the present disclosure may be implemented in various ways, including as a computer program product comprising an article of manufacture. The computer program product may include a non-transitory computer-readable storage medium storing an application, a program component, a script, a source code, a program code, an object code, a byte code, a compiled code, an interpreted code, a machine code, an executable instruction, etc. (also referred to herein as executable instructions, instructions for execution, a computer program product, a program code, and/or similar terms are used interchangeably herein). Such non-transitory computer-readable storage media include all computer-readable media (including volatile and nonvolatile media).

In one embodiment, the non-volatile computer-readable storage medium may include a floppy disk, a flexible disk, a hard disk, a solid state storage device (SSS) (e.g., a Solid State Drive (SSD), a Solid State Card (SSC), a Solid State Module (SSM)), an enterprise flash drive, a tape, or any other non-transitory magnetic medium, etc. The non-volatile computer-readable storage medium may also include punch cards, paper tape, optical marking sheets (or any other physical medium having a hole pattern or other optically identifiable marking), compact disc read-only memory (CD-ROM), compact disc rewriteable (CD-RW), digital Versatile Discs (DVD), blu-ray discs (BD), any other non-transitory optical medium, etc. Such non-volatile computer-readable storage media may also include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, etc.), multimedia Memory Cards (MMC), secure Digital (SD) memory cards, smart media cards, compact Flash (CF) cards, memory sticks, and the like. In addition, the non-volatile computer-readable storage medium may also include Conductive Bridge Random Access Memory (CBRAM), phase change random access memory (PRAM), ferroelectric random access memory (FeRAM), non-volatile random access memory (NVRAM), magnetoresistive Random Access Memory (MRAM), resistive Random Access Memory (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), floating junction gate random access memory (FJG RAM), millipede (Millipede) memory, racetrack memory, and the like.

In one embodiment, the volatile computer-readable storage medium may include Random Access Memory (RAM), dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), second generation double data rate synchronous dynamic random access memory (DDR 2 SDRAM), third generation double data rate synchronous dynamic random access memory (DDR 3 SDRAM), lanbas (Rambus) dynamic random access memory (RDRAM), double transistor RAM (TTRAM), thyristor RAM (T-RAM), zero capacitor (Z-RAM), lanbas direct memory component (RIMM), dual inline memory component (DIMM), single inline memory component (SIMM), video Random Access Memory (VRAM), cache memory (including various levels), flash memory, register memory, and the like. It will be appreciated that where embodiments are described as using a computer-readable storage medium, other types of computer-readable storage media may be substituted or used in addition to the computer-readable storage media described above.

It should be appreciated that the various embodiments of the present disclosure may also be implemented as a method, apparatus, system, computing device, computing entity, or the like. As such, embodiments of the present disclosure may take the form of an apparatus, system, computing device, computing entity, or the like that executes instructions stored on a computer-readable storage medium to perform particular steps or operations. Accordingly, embodiments of the present disclosure may also take the form of an entirely hardware embodiment, an entirely computer program product embodiment and/or an embodiment containing a combination of computer program products and hardware performing certain steps or operations.

Embodiments of the present disclosure are described below with reference to block diagrams and flowchart illustrations. Accordingly, it should be understood that each block of the block diagrams and flowchart illustrations can be implemented in the form of computer program products, entirely hardware embodiments, combinations of hardware and computer program products, and/or devices, systems, computing devices, computing entities, etc. that execute instructions, operations, steps and similar words (e.g., executable instructions, instructions for execution, program code, etc.) on a computer readable storage medium for execution. For example, the fetching, loading, and executing of code may be performed sequentially such that one instruction is fetched, loaded, and executed once. In some example embodiments, fetching, loading, and/or executing may be performed in parallel such that multiple instructions are fetched, loaded, and/or executed together. Thus, such embodiments may result in a specially configured machine performing the steps or operations specified in the block diagrams and flowchart illustrations. Accordingly, the block diagrams and flowchart illustrations support various combinations of embodiments for performing the specified instructions, operations or steps.

In various aspects, a computing storage device may significantly affect the manner in which a storage device, such as a storage device supporting non-volatile memory express (NVMe), functions and operates. By adding the computations available to the Computing Storage (CS) device, various computing operations can be offloaded from the host to the storage where the data resides. As calculations are performed on given data, some models extract the data from a storage medium or network resource into the memory of the host, and then cause a Central Processing Unit (CPU) to run a calculation operation on the data (e.g., find a count of all zip codes with a trend virus infection). This approach becomes limited because the data must traverse structures such as a direct attached peripheral component interconnect express (PCIe) bus or a network fabric that adds latency.

Additionally, since the bus may not take advantage of the overall performance provided by NVMe devices, if multiple such devices are occupied, the overall throughput of each device will be lower than when a single device is occupied. The computing storage device enables near memory computing to be run, saving transfer delay. Furthermore, only the results of the copy operation are needed, and not the source data, which may be very large in a particular use case. There are a number of benefits of Computational Storage (CS) available based on use cases. The CS device obtains its computation by an embedded CPU, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Graphics Processor (GPU), or the like. Some computations may be done more efficiently using the CS device, while other computations may be better canceled using the host CPU.

The CS enabled device runs a program that contains specific algorithms within the device. These programs may be pre-built at the time of manufacture or may be downloaded later by the host user. These programs will be executed by the host user for the data and can be serviced based on the results of the programs.

In some aspects, a storage device with processing capabilities may provide near data processing via Computing Storage (CS) operations within the device that include CS command processing. In some aspects, CS command processing may be accomplished at least in part by the host CPU, CS storage, or another computing device, as configuration and applicability may vary. In some aspects, a computer program may run a computing operation on data provided as an input, and the computer program may provide a result of the computing operation as an output. In some aspects, such a program may be included in the host CPU as a software program, or may be included in the CS device (e.g., included in a processing element) as a software program or a hardware program.

In some aspects, programs/functions may be constructed differently for execution within a device for the type of computation (e.g., FPGA bit file for FPGA-based computation, extended berkeley packet filter (eBPF) program for embedded CPU, program-based C/c++ language, etc.). Further, program execution and data processing may depend on the algorithm running the CS device and the amount of data that the CS device may consume. In some aspects, the host application may be configured to use these device programs to offload computing and memory resources normally occupied by the host into the CS device.

Furthermore, the amount of CS device memory required and consumed to execute a program for a given task may not always be known in advance and may be due to dynamic properties of the data being processed (e.g., different sizes of incoming object data). In some aspects, pre-allocation of device memory prior to data processing may not be feasible because device memory may be a depletable, limited resource. The CS device may provide device memory protection for the executing program to access those particular memory regions. Furthermore, when executing programs in a multi-tenant environment, memory protection may be required so that data is secure between programs.

Some mechanisms defined for memory protection may handle pre-allocated memory rather than dynamic memory usage. This may limit the ability to provide data protection across the executives of CS devices in a multi-tenant environment. The disclosed embodiments support dynamic device memory usage-based protection for executing computationally stored programs. The mechanism may include dynamic memory protection based on memory usage used in conjunction with executing programs in the CS-capable device.

In some aspects, the disclosed embodiments can include systems and methods that specify a memory region to use in a command (e.g., in NVMe execution program commands). In another aspect, the disclosed system can include one or more memory regions associated with executing commands. Further, the disclosed system can designate a memory region for protection in a multi-tenant environment. In some aspects, the disclosed systems may include a mechanism whereby the provided memory region may be applied by a device to limit executive access to only a specified device memory region. In some aspects, such memory protection may limit the use of designated memory regions by unauthorized entities, including peer-to-peer (P2P) devices, load/store devices, another host, and/or programs running on separate devices or different containers/virtual machines.

In some aspects, the disclosed system can include a method of including a memory region and program parameter data in a host data pointer buffer. In other aspects, the disclosed system may include mechanisms that do not require administrative privileges (privileged users) to designate memory regions. In other aspects, the disclosed system includes a computing namespace that supports execution of programs with dynamic memory protection enabled. Furthermore, the disclosed system may allow a device to pause and stop further execution of a program if the device accesses a memory region outside of the protection specified in the command (e.g., in executing the command).

In various aspects, the disclosed system can include a program running on a host that facilitates building dynamic memory ranges for program access using one or more Application Program Interfaces (APIs). The API may be used to interface with the execution of the program, which facilitates dynamic memory range based protection of the program. The systems and methods are compatible with and may coexist with existing storage protocols (e.g., NVMe, CS standards). Further, the disclosed system may be executed on storage devices (e.g., solid state drives SSDs) and those with computing capabilities.

In general, the disclosed system provides the ability to specify dynamic memory protection for executing programs in a CS-capable storage that includes an NVMe compliant device that can enable dynamic memory usage protection for the device. Furthermore, the disclosed system enables memory protection in a multi-tenant environment, extending the supported computing and algorithm types.

FIG. 1 illustrates a system (e.g., an electronic system) that includes a computing storage unit that supports various functions on a storage device (e.g., providing dynamic memory protection for programs) according to disclosed embodiments. In fig. 1, a machine 105 (which may also be referred to as a host or system) may include a processor 110, a memory 115, and a storage 120. The processor 110 may be any kind of processor. For ease of description, the processor 110 is shown external to the machine along with other components discussed below; the disclosed embodiments include these components within the machine. Although FIG. 1 shows a single processor 110, machine 105 may include any number of processors, and may be mixed in any desired combination, each processor may be a single-core or multi-core processor, each processor may implement a Reduced Instruction Set Computer (RISC) architecture or a Complex Instruction Set Computer (CISC) architecture, among other possibilities.

The processor 110 may be coupled to a memory 115. The memory 115 may be any kind of memory such as flash memory, dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), persistent random access memory, ferroelectric Random Access Memory (FRAM), or non-volatile random access memory (NVRAM) (such as Magnetoresistive Random Access Memory (MRAM), etc.). The memory 115 may also be any desired combination of different memory types and may be managed by the memory controller 125. The memory 115 may be used to store data that may be referred to as "short-term": that is, data that is not expected to be stored for an extended period of time. Examples of short-term data may include temporary files, data being used locally by an application (which may have been copied from other storage locations), and so forth.

The processor 110 and memory 115 may also support an operating system under which various applications may run. These applications may issue requests (also referred to as commands) to read data from memory 115 or storage 120 or to write data to memory 115 or storage 120. The storage device 120 may be accessed using a device driver 130.

The storage 120 may be associated with a computing storage unit 135. As discussed below with reference to fig. 3A-3D, the calculation storage unit 135 may be part of the storage device 120, or the calculation storage unit 135 may be separate from the storage device 120. The phrase "associated with … …" is intended to cover both storage that includes a computing storage unit as well as storage that is paired with a computing storage unit that is not part of the storage unit itself. In other words, when the storage device and the calculation storage unit are physically separate devices but connected in such a manner that they can communicate with each other, the storage device and the calculation storage unit may be referred to as being "paired".

In addition, the connection between the storage device 120 and the paired computing storage unit 135 may enable the two devices to communicate, but may not enable one (or both) devices to work with different partners (i.e., the storage device 120 may not be able to communicate with another computing storage unit, and/or the computing storage unit 135 may not be able to communicate with another storage device). For example, the storage 120 and paired computing storage 135 may be connected in series (in either order) to a fabric (fabric) such as a bus, enabling the computing storage 135 to access information from the storage 120 in a manner that another computing storage may not be capable of.

The processor 110 and the storage 120 may be coupled to a structure. The structure may be any structure along which information may be transferred. The fabric may include a fabric that may be internal to machine 105, and the fabric that may be internal to machine 105 may use interfaces such as peripheral component interconnect express (PCIe), serial Advanced Technology (AT) attachment (SATA), small Computer System Interface (SCSI), and the like. The fabric may also include a fabric that may be external to machine 105, and the fabric external to machine 105 may use interfaces such as ethernet, infiniband, or fibre channel. In addition, the fabric may support one or more protocols (such as non-volatile memory (NVM) flash (NVMe), NVMe-oh on the fabric (NVMe-oh), or Simple Service Discovery Protocol (SSDP), etc.). Thus, the structure may be considered to include both an internal networking connection and an external networking connection through which commands may be sent directly or indirectly to the storage 120 (and more specifically to a computing storage unit associated with the storage 120).

Although FIG. 1 shows one storage device 120 and one computing storage unit 135, any number of storage device(s) and/or any number of computing storage unit(s) may be present in machine 105.

Although fig. 1 uses the generic term "storage," the disclosed embodiments may include any storage format that may benefit from the use of computing storage units, examples of which may include hard disk drives and Solid State Drives (SSDs). Any reference below to an "SSD" should be understood to include such other embodiments of the disclosure. In addition, while the discussion above (and below) focuses on storage 120 associated with a computing storage unit, the disclosed embodiments extend to devices other than storage that may include or be associated with a computing storage unit. Any reference above (and below) to "storage means" may be understood to also include other means that may be associated with the computing storage unit.

The host may be implemented using any type of device that may be configured as a host including, for example, a server (such as a computing server, a storage node, a web server, etc.), a computer (such as a workstation, a personal computer, a tablet computer, a smart phone, etc.), or any combination thereof. The apparatus may be implemented using any type of device that may be configured as an apparatus including, for example, accelerator apparatus, storage apparatus, network apparatus, memory expansion and/or buffer apparatus, graphics Processor (GPU), neural Processor (NPU), tensor Processor (TPU), etc., or any combination thereof.

Any communication between devices (e.g., host, CS device, and/or any intermediate device) may occur through an interface, which may be implemented using any type of wired and/or wireless communication medium, interface, protocol, etc., including: PCIe, NVMe, ethernet, NVMe-orf, computing fast link (CXL) and/or coherence protocols (such as cxl.mem, cxl.cache, cxl.io, etc.), gen-Z, open coherence accelerator processor interface (OpenCAPI), cache coherence interconnect for accelerator (CCIX), advanced extensible interface (AXI), etc., or any combination thereof, transmission control protocol/internet protocol (TCP/IP), fibre channel, infiniband, serial AT attachment (SATA), small Computer System Interface (SCSI), serial Attached SCSI (SAS), iWARP, any generation wireless network including 2G, 3G, 4G, 5G, etc., any generation wireless fidelity (Wi-Fi), bluetooth, near field communication, etc., or any combination thereof. In some embodiments, the communication interface may include a communication structure including one or more links, buses, switches, hubs, nodes, routers, switches, repeaters, and the like. In some embodiments, the systems illustrated herein may include one or more additional devices having one or more additional communication interfaces.

In embodiments where the apparatus is implemented as a storage device, the storage device may include any type of non-volatile storage medium based on, for example, a solid state medium (e.g., a Solid State Drive (SSD)), a magnetic medium (e.g., a Hard Disk Drive (HDD)), an optical medium, or the like, or any combination thereof. For example, in some embodiments, the storage device may be implemented as a NAND (NAND) flash based SSD, a persistent memory (such as a cross-grid non-volatile memory), a memory with a change in bulk resistance, a Phase Change Memory (PCM), or the like, or any combination thereof. Any such storage device may be implemented in any form factor (such as 3.5 inches, 2.5 inches, 1.8 inches, m.2, enterprise and data center SSD form factors (EDSFF), NF1, etc.) using any connector configuration (such as SATA, SCSI, SAS, U.2, m.2, etc.). Any such storage device may be implemented in whole or in part using and/or in combination with a server chassis, a server rack, a data room, a data center, an edge data center, a mobile edge data center, and/or any combination thereof.

Any of the functions described herein, including any host functions, device functions, etc., may be implemented using hardware, software, firmware, or any combination thereof, including, for example, executing instructions stored in any type of memory: hardware and/or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM)), non-volatile memory (including flash memory, persistent memory (such as cross-grid non-volatile memory), memory with body resistance change, phase Change Memory (PCM), etc. and/or any combination thereof), complex Programmable Logic Devices (CPLDs), field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), CPUs including Complex Instruction Set Computer (CISC) processors (such as x86 processors) and/or Reduced Instruction Set Computer (RISC) processors (such as RISC-V and/or ARM processors), graphics Processors (GPUs), neural Processors (NPUs), tensor Processors (TPU), etc. In some embodiments, one or more components may be implemented as a system on a chip (SOC).

FIG. 2 shows details of machine 105 of FIG. 1 in accordance with the disclosed embodiments. In FIG. 2, in general, machine 105 includes one or more processors 110, and processor 110 may include a memory controller 125 and a clock 205 that may be used to coordinate the operation of the components of the machine. The processor 110 may also be coupled to a memory 115, and the memory 115 may include, by way of example, random Access Memory (RAM), read Only Memory (ROM), or other state preserving medium. The processor 110 may also be coupled to the storage 120 and the network connector 210, the network connector 210 may be, for example, an ethernet connector or a wireless connector. The processor 110 may also be connected to a bus 215, and a user interface 220 and input/output (I/O) interface ports, which may be managed using an I/O engine 225, may be attached to the bus 215, among other components.

Fig. 3A-3D illustrate various arrangements of the computing storage unit 135 of fig. 1 (which may also be referred to as a "computing device" or "device") that may be associated with the storage device 120 of fig. 1, according to disclosed embodiments. In FIG. 3A, storage device 305 and computing device 310-1 are shown. Storage 305 may include controller 315 and storage 320-1 and may be reachable through a Queue Pair (QP) 325: queue pair 325 may be used for both management of storage device 305 and controlling I/O of storage device 305.

Computing device 310-1 may be paired with storage device 305. Computing device 310-1 may include any number of processor(s) 330, and processor 330 may provide any number of service(s) 335-1 and 335-2. For greater clarity, each processor 330 may provide any number of service(s) 335-1 and 335-2 (although the disclosed embodiments may include computing device 310-1 that includes exactly two services 335-1 and 335-2). Each processor 330 may be a single-core processor or a multi-core processor. Computing device 310-1 may be reachable through queue pair 340, and queue pair 340 may be used for both management of computing device 310-1 and/or controlling I/O of computing device 310-1.

Processor 330 may be considered a near storage process (i.e., a process that is closer to storage device 305 than processor 110 of fig. 1). Because processor 330 is closer to storage device 305, processor 330 may be able to execute commands to data stored in storage device 305 faster than processor 110 of fig. 1. Although not shown in fig. 3A, the processor 330 may have associated memory (see, e.g., fig. 4 and related description) that may be used for local execution of commands on data stored in the storage device 305. The associated memory may include local memory similar to memory 115 of fig. 1, on-chip memory (which may be faster than memory such as memory 115, but may be more expensive to produce), or both.

Although FIG. 3A shows storage device 305 and computing device 310-1 as being individually reachable through fabric 345, the disclosed embodiments may also include storage device 305 and computing device 310-1 connected in series (as shown in FIG. 1). That is, commands directed to storage device 305 and computing device 310-1 may be received at the same physical connection to fabric 345 and may reach one device through another device. For example, if computing device 310-1 is located between storage device 305 and fabric 345, computing device 310-1 may receive commands directed to both computing device 310-1 and storage device 305: computing device 310-1 may process commands directed to computing device 310-1 and may pass commands directed to storage device 305. Similarly, if storage device 305 is located between computing device 310-1 and fabric 345, storage device 305 may receive commands directed to both storage device 305 and computing device 310-1: storage device 305 may process commands directed to storage device 305 and may communicate commands directed to computing device 310-1.

Services 335-1 and 335-2 may provide a number of different functions (e.g., customer Service Functions (CSFs)) that may be performed on data stored in storage device 305. For example, services 335-1 and 335-2 may provide predefined functions (such as encryption, decryption, compression and/or decompression of data, erasure coding, and/or application of regular expressions). Or services 335-1 and 335-2 may provide more general functionality such as data search functionality and/or Structured Query Language (SQL) functionality. Services 335-1 and 335-2 may also support running special codes. That is, applications using services 335-1 and 335-2 may provide custom code to be executed using data on storage device 305. Services 335-1 and 335-2 may also be any combination of such functions. Table 1 lists some examples of services that may be provided by processor 330.

Table 1: service type

The processor 330 (and indeed the computing device 310-1) may be implemented in any desired manner. Example embodiments may include a local processor (such as a Central Processing Unit (CPU) or some other processor), a Graphics Processor (GPU), a General Purpose GPU (GPGPU), a Data Processor (DPU), a Tensor Processor (TPU), or a Neural Processor (NPU), etc. The processor 330 may also be implemented using a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC), or the like. If computing device 310-1 includes more than one processor 330, each processor may be implemented as described above. For example, computing device 310-1 may have each of a CPU, TPU, and FPGA, or computing device 310-1 may have two FPGAs, or computing device 310-1 may have two CPUs, one ASIC, and so on.

The computing device 310-1 or the processor 330 may be considered a computing storage unit, depending on the interpretation desired.

Although fig. 3A shows storage device 305 and computing device 310-1 as separate devices, in fig. 3B storage device 305 and computing device 310-1 may be combined. Accordingly, computing device 310-2 may include a controller 315, a storage 320-1, and a processor 330 providing services 335-1 and 335-2. As with storage device 305 and computing device 310-1 of FIG. 3A, management and I/O commands may be received via queue pair 340. Even though computing device 310-2 is shown as including both storage 320-1 and processor 330, fig. 3B may be considered to include storage associated with a computing storage unit.

In another variation shown in FIG. 3C, computing device 310-3 is shown. Computing device 310-3 may include a controller 315 and a storage 320-1 and a processor 330 providing services 335-1 and 335-2. But even though computing device 310-3 may be considered a single component including controller 315, storage 320-1, and processor 330 (and also considered storage associated with a computing storage unit), unlike the embodiment shown in fig. 3B, controller 315 and processor 330 may each include their own queue pairs 325 and 340 (again, queue pairs 325 and 340 may be used for management and/or I/O). By including queue pair 325, controller 315 can provide transparent access to storage device 320-1 (rather than requiring all communication to occur through processor 330).

In addition, the processor 330 may have a proxy storage access (proxied storage access) 350 to the storage device 320-1. Thus, instead of routing the access request through the controller 315, the processor 330 may be able to directly access the data from the storage device 320-1.

In fig. 3C, both the controller 315 and the proxy storage access 350 are shown using dashed lines to indicate that they are optional elements and may be omitted depending on the implementation.

Finally, fig. 3D shows another embodiment. In FIG. 3D, computing device 310-4 is shown, computing device 310-4 may include a controller 315 and proxy storage access 350 similar to FIG. 3C. Additionally, computing device 310-4 may include an array of one or more storage devices (or storage elements) 320-1 through 320-4. Although fig. 3D shows four storage elements, the disclosed embodiments may include any number (one or more) of storage elements. In addition, the individual storage elements may be other storage devices (such as those shown in fig. 3A-3D).

Because computing device 310-4 may include more than one storage element 320-1 through 320-4, computing device 310-4 may include an array controller 355. Array controller 355 may manage how data is stored on storage elements 320-1 through 320-4 and how data is retrieved from storage elements 320-1 through 320-4. For example, if the storage elements 320-1 through 320-4 are implemented as a level of Redundant Array of Independent Disks (RAID), then the array controller 355 may be a RAID controller. If some form of erase code is used to implement storage elements 320-1 through 320-4, array controller 355 may be an erase code controller.

FIG. 4 illustrates a conceptual diagram of a computing storage device providing dynamic memory protection for programs according to a disclosed example embodiment. In particular, diagram 400 shows a CS device 402, which CS device 402 can include a controller 404 (e.g., an NVMe controller) to be discussed, one or more compute namespaces 406, one or more memory namespaces 408 (memory namespaces 408 can include a subsystem local memory namespace (device memory)), and one or more storage namespaces 410 and a communication port 411 (for sending and receiving information with any suitable device (such as a host) using any suitable protocol (such as NVMe). In some aspects, the one or more memory namespaces 408 can include volatile memory. In other aspects, the one or more storage namespaces 410 can include non-volatile memory (such as flash memory). In some aspects, the memory namespaces may be byte-addressable and the memory namespaces may be standard block-addressable. The computing namespace may include abstract resources that are addressable by NVMe commands to run a computing program.

The computing namespace 406 may include an abstract representation of one or more computing engines CE (such as CE0, CE1, and CE2 shown in the graph 400) running a program (e.g., program 0 in the graph 400). The computing namespaces may include additional resources, such as actual computing modules and programs designated as Computing Engines (CEs). The compute engine resources may be comprised of one or more processing elements (such as CPU, ASIC, FPGA, GPU, TPU, etc.). For example, the compute namespace 406 may include a CPU core that may be additionally paired with an FPGA. The utilization of each of these resources need not be exclusive. The CPU core may also be reused/mapped to another compute namespace and similarly used for ASICs and the like. The namespace abstraction may allow hardware characteristics of computing resources to be selectively exposed (i.e., the host is not directly exposed to the CPU or FPGA, but interfaces with the virtualized computing namespace).

The computing program may run on the CE and may process data that is available through the device local memory or directly into the CE. In some aspects, these programs may allow for computational storage of NVMe devices. Different usage models may be used to manage and use CS features available in the device. The computing resource may be represented as a namespace, which may be mapped directly into the virtual environment of the virtual machine, if desired.

In some aspects, as noted, the disclosed embodiments may include systems and methods for protecting device memory in a multi-tenant environment. The memory namespace 408 can include device memory that can be referred to as Subsystem Local Memory (SLM) of NVMe. Furthermore, such SLMs may represent scarce resources (i.e., only a certain amount of memory may be installed and available to the host). Such scarcity of memory may be due to various factors including device form factor, power consumption, cost, and market suitability. For example, device 402 may be filled with only 8GB of DRAM, while the host system may be able to fill 1TB of DRAM. The device memory (e.g., SLM) may be used by programs running on the device as part of the computing storage and provide performance, power and cost savings compared to the case where the program runs entirely on the host. In some aspects, more than one program may run on the device 402, and there may be more than one host user running the device program.

In some aspects, the host user may run the program in a stand-alone manner, or may run in a virtual machine or container. Each of these tenants may use their own memory space allocated from a larger memory namespace 408 (e.g., SLM). Data security and data privacy are maintained only if memory allocated to one user is not accessible to another user through a program running on the device. To achieve this, some NVMe-based devices may use the following mechanism: the area of memory is pre-registered with the device for use of the application. Registration may include a memory region to be accessed during program execution. Multiple registrations may be done in advance before execution. When the device program is running, a registration Identifier (ID) is provided along with other parameters of the program that contain the actual SLM area to be accessed.

Such a pre-registration mechanism may be useful for some applications but not all applications, since not all applications may determine the amount of memory they will consume for a particular program to run. While the amount of SLM may be predetermined by the application for some specific use cases, for other use cases the application may only learn about memory usage when an IO request is received. Object storage and processing applications may consume different sized data streams that may come in different sizes (e.g., in writing, ranging from about 1MB to 1000 MB). Pre-allocation may not be a viable option since SLMs may represent scarce resources. Device memory requirements must be completed on the fly and protection (e.g., the dynamic memory protection scheme disclosed herein) needs to be applied.

Thus, in such cases, the pre-registration mechanism may lack availability for the following reasons: the memory usage requirements for program execution are well known. The memory area needs to be registered with the device in advance. The registration command is a privileged command issued to the NVMe management queue. Even if there were ways to send management commands prior to execution, the delay caused by the commands would be a burden for each program execution.

For these reasons, some definitions are limiting and may not be suitable for applications that dynamically use device memory. The present disclosure describes embodiments in which a field in a command is received by a CS device, the field in the command specifying whether there is a dynamic memory range in the command.

Fig. 5A illustrates a field 500 specifying parameters that may be used to calculate memory protection of a storage device according to a disclosed example embodiment. The number of bits (502) of the field 500 may be, for example, 32 bits, and the meaning (504) of the field 500 may be the number of memory regions (NUMR). As shown in fig. 5A, the number of memory regions (NUMR) may be used to specify the number of subsystem local memory regions specified in the command. Further, if NUMR is a non-zero value, then the dynamic memory region is applied to execute the program command. If NUMR is set to zero, no memory region is specified and the system can apply a (static) pre-registered memory range.

In some embodiments, a memory range identifier, such as a memory Range Set ID (RSID), may include a field for a preregistered memory region, and may be set to zero, which indicates that a range set without preregistration is in use.

Fig. 5B illustrates another field 510 specifying parameters that may be used to calculate memory protection of a storage device according to a disclosed example embodiment. The number of bits (512) of the field 510 may be, for example, 128 bits, and the meaning (514) of the field 510 may be a Data Pointer (DPTR). The actual memory region is then filled in memory addressed by the Data Pointer (DPTR) field (e.g., similar to the definition provided by the NVMe specification, where reference is made to the NVMe base specification for details of PRP entries (pointers) and SGL entries (pointers)). This field specifies the host buffer containing the program parameters. The length of the buffer is defined by a Data Length (DLEN) field.

FIG. 6 illustrates a representation 600 of a data pointer that may be used to compute memory protection of a storage device according to a disclosed example embodiment. As shown in fig. 6, if NUMR field is non-zero and RSID is set to zero, the host buffer may contain NUMR memory region at offset zero, followed by program parameters. In this case, the DLEN field will be equal to the sum of the specified total memory area and the length of the program parameter data. In some aspects, when NUMR is a non-zero field, memory range 602 represents the memory range that begins at offset 0 in the Data Pointer (DPTR). Each memory range may be specified according to a protocol (e.g., NVMe protocol). The program parameter data 604 may include one or more program parameters and may begin at an offset in the DPTR, which may be determined by multiplying the length of each memory range by the total number of memory ranges specified by NUMR. Since the number of ranges may be dynamic, the beginning of the program parameter data is also dynamic. Additionally, while RSID and DLEN are not shown in fig. 6, DLEN may include valid data (i.e., memory range and program parameter data) that is filled in DPTR.

Each memory region has a definition that includes the following details: a memory namespace ID, a starting offset for an area within the memory namespace, and a total length of the memory area in use. There may be multiple memory regions available to the program that can be dynamically captured in the commands specified above.

Thus, the mechanism enables dynamic memory protection (e.g., updateable program state specific memory protection) of a computing program while accessing device memory in a multi-tenant environment. Current protocols and mechanisms may be prohibitive, at least because they may require privileged users and knowledge prior to memory use. Most program uses (such as data analysis, big data, and object-based computing) dynamically use memory when needed. Using such dynamic memory usage protection schemes, host applications can securely run programs with the protection in devices in a multi-tenant environment. Providing such protection enables devices with computing power to perform more tasks and support different uses.

Fig. 7 illustrates a representative flow diagram 700 of some example operations associated with the disclosed system in accordance with the disclosed embodiments. At block 702, the disclosed system receives a command specifying an amount of computing resources and an amount of memory resources associated with a program. In other aspects, the command may specify that portions of one or more memory resources are restricted from access. At block 704, the disclosed system processes the command through the controller, wherein the processing includes allocating a portion of the one or more computing resources and allocating a portion of the one or more memory resources for use by the program based on the command. In one aspect, the system determines that the program is attempting to access a different region of the one or more memory resources than the allocated portion of the one or more memory resources, and the system halts execution of the program. In some aspects, the one or more memory resources may include one or more local memory namespaces. In other aspects, the system may also include one or more storage resources that include one or more storage namespaces. In one aspect, the program is a first program in a multi-tenant environment that includes at least a second program. In other aspects, the commands may be based on a protocol, including non-volatile memory express (NVMe). In one aspect, the one or more computing resources may include computing resources including at least one of a Central Processing Unit (CPU), a Graphics Processor (GPU), a Field Programmable Gate Array (FPGA), a Tensor Processor (TPU), and an Application Specific Integrated Circuit (ASIC). In some aspects, the computing storage may include storage that supports non-volatile memory express (NVMe).

FIG. 8 illustrates an example schematic diagram of a system that may be used to practice embodiments of the present disclosure. As shown in fig. 8, this particular embodiment may include one or more management computing entities 800, one or more networks 805, and one or more user devices 810 (e.g., host devices, storage devices, add-ons, etc.). In various embodiments, management computing entity 800 may be configured to perform operations associated with the disclosed systems and associated embodiments described throughout the disclosure, including but not limited to those described in connection with the example operations in fig. 7. Further, the management computing entity 800 may reside in any suitable portion of the disclosed system (such as a computing storage controller, a computing storage device manager, a host application, a remote host, another device, combinations thereof, and the like). Each of these components, entities, devices, systems, and the like, as used interchangeably herein, may communicate directly or indirectly with one another, such as through the same or different wired or wireless networks. Additionally, while fig. 8 shows the various system entities as separate, stand-alone entities, the various embodiments are not limited to this particular architecture. As illustrated, the communication may be performed using any suitable protocol as further described herein.

Fig. 9 illustrates an example schematic diagram 900 of managing computing entities in accordance with a disclosed example embodiment. As shown, the management computing entity may be configured to perform operations associated with the disclosed system and associated embodiments described throughout the disclosure. Furthermore, management computing entity 900 can reside in any suitable portion of the disclosed system. In particular, the content component can be employed to determine a signal indicative of data (e.g., video, audio, text, data, combinations thereof, etc.) to be transmitted through the systems described herein. In another embodiment, the determination of the signal for transmission may be based, for example, on user input to the device, a predetermined schedule of data transmissions on a network associated with the system, a change in network conditions, and so on. In one embodiment, the signal may include data that may be encapsulated in data frames and/or packets (packets) configured to be transmitted from a device to one or more devices on a network.

In another embodiment, the processing element 905 may be used to determine various parameters associated with data transmitted over a network associated with the disclosed system. As another example, the processing element 905 may be used to perform various acceleration operations (such as offloading at least a portion of functions, data pre-or post-processing, combinations thereof, and the like).

In one embodiment, a transmitting component (not shown) may be used to transmit signals from one device to another device on a network. For example, the transmitting component may be used to prepare a transmitter (e.g., transmitter 1004 of fig. 10 below) to transmit a signal over a network. For example, the transmitting component may queue the data in one or more buffers, may determine that the transmitting device and associated transmitter are functional and have sufficient power to transmit signals over the network, may adjust one or more parameters associated with the transmission of the data (e.g., modulation type, signal amplification, signal power level, noise suppression, combinations thereof, etc.).

In general, the terms computing entity, computer, entity, device, system, and/or the like, as used interchangeably herein, may represent, for example, one or more computers, computing entities, desktop computers, mobile phones, tablet computers, slates, notebook computers, laptop computers, distributed systems, gaming machines (e.g., xbox, playstation, wii), watches, glasses, ibeacons, proximity beacons, key fobs, radio Frequency Identification (RFID) tags, headsets, scanners, televisions, dongles, cameras, bracelets, wearable items/devices, self-service terminals (kiosks), input terminals, servers or server networks, blades (blades), gateways, switches, processing devices, processing entities, set-top boxes, repeaters, routers, network access points, base stations, and the like, and/or any combination of devices or entities suitable for performing the functions, operations, and/or processes described herein. Such functions, operations, and/or processes may include, for example, transmitting, receiving, operating, processing, displaying, storing, determining, creating/generating, monitoring, evaluating, comparing, and/or like terms as used interchangeably herein. In one embodiment, these functions, operations, and/or processes may be performed on data, content, information, and/or similar terms as used interchangeably herein.

As indicated, in one embodiment, the managing computing entity 900 may also include one or more communication interfaces 920 for communicating with various computing entities (such as by communicating data, content, information, and/or similar terms as may be transmitted, received, operated upon, processed, displayed, stored, etc., and/or used interchangeably herein). For example, the managing computing entity 900 may communicate with the user device 810 and/or various other computing entities.

As shown in fig. 9, in one embodiment, the management computing entity 900 may include or be in communication with one or more processing elements 905 (also referred to as processors, processing circuitry, and/or similar terms used interchangeably herein), or with one or more processing elements 905 (also referred to as processors, processing circuitry, and/or similar terms used interchangeably herein), the processing elements 905 communicating with other elements within the management computing entity 900, for example, via a bus. As will be appreciated, the processing element 905 may be implemented in a number of different ways. For example, the processing element 905 may be implemented as one or more Complex Programmable Logic Devices (CPLDs), microprocessors, multi-core processors, co-processing entities, special-purpose instruction set processors (ASIPs), microcontrollers, and/or controllers. Furthermore, the processing element 905 may be implemented as one or more other processing devices or circuitry. The term "circuitry" may represent an entirely hardware embodiment or a combination of hardware and a computer program product. Thus, the processing element 905 may be implemented as an integrated circuit, application Specific Integrated Circuit (ASIC), field Programmable Gate Array (FPGA), programmable Logic Array (PLA), hardware accelerator, other circuitry, or the like. Thus, as will be appreciated, the processing element 905 may be configured for a particular use or to execute instructions stored in a volatile or non-volatile medium or otherwise accessible to the processing element 905. As such, whether configured by hardware or a computer program product, or by a combination thereof, the processing element 905, when configured accordingly, is capable of performing steps or operations in accordance with embodiments of the present disclosure.

In one embodiment, management computing entity 900 may also include or be in communication with non-volatile media (also referred to as non-volatile storage, memory storage, memory circuitry, and/or similar terms used interchangeably herein). In one embodiment, the non-volatile storage device or memory may include one or more non-volatile storage devices or memory media (or memories) 910 including, but not limited to, hard disks, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory cards, memory sticks, CBRAM, PRAM, feRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, huperzia memory, racetrack memory, and the like. As will be appreciated, the non-volatile storage device or memory medium may store a database, database instance, database management system, data, application, program component, script, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and the like. The term database, database instance, database management system, and/or similar terms as used interchangeably herein may refer to a collection of records or data stored in a computer-readable storage medium using one or more database models (such as hierarchical database models, network models, relational models, entity-relationship models, object models, document models, semantic models, graph models, etc.). In one embodiment, management computing entity 900 may also include or be in communication with volatile media (also referred to as volatile memory device, memory storage device, memory circuitry, and/or like terms used interchangeably herein). In one embodiment, the volatile storage device or memory may also include one or more volatile storage devices or storage media (or volatile memory) 915, including but not limited to RAM、DRAM、SRAM、FPM DRAM、EDO DRAM、SDRAM、DDR SDRAM、DDR2 SDRAM、DDR3 SDRAM、RDRAM、TTRAM、T-RAM、Z-RAM、RIMM、DIMM、SIMM、VRAM、 cache memory, register memory, and the like. As will be appreciated, a volatile storage device or memory medium may be used to store at least a portion of a database, database instance, database management system, data, applications, programs, program components, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and the like that are executed by, for example, the processing element 905. Thus, databases, database instances, database management systems, data, applications, programs, program components, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and the like may be used to control particular aspects of the operation of the management computing entity 900 with the aid of the processing elements 905 and the operating system.

As indicated, in one embodiment, the managing computing entity 900 may also include one or more communication interfaces 920 for communicating with various computing entities (such as by communicating data, content, information, and/or similar terms as may be transmitted, received, operated upon, processed, displayed, stored, etc., and/or used interchangeably herein). Such communication may be performed using a wired data transfer protocol such as peripheral component interconnect express (PCIe), fiber Distributed Data Interface (FDDI), digital Subscriber Line (DSL), ethernet, asynchronous Transfer Mode (ATM), frame relay, data Over Cable Service Interface Specification (DOCSIS), or any other wired transfer protocol. Similarly, the management computing entity 900 may be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), universal Mobile Telecommunications System (UMTS), code division multiple access 2000 (CDMA 2000), CDMA 2000X (1 xRTT), wideband Code Division Multiple Access (WCDMA), time division synchronous code division multiple access (TD-SCDMA), long Term Evolution (LTE), evolved universal terrestrial radio access network (E-UTRAN), evolved data optimized (EVDO), high Speed Packet Access (HSPA), high Speed Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), wi-Fi direct, 802.16 (WiMAX), ultra Wideband (UWB), infrared (IR) protocols, near Field Communication (NFC) protocols, zigBee, bluetooth protocols, 5G protocols, wireless Universal Serial Bus (USB), and/or any other wireless protocols.

Although not shown, the management computing entity 900 can include or be in communication with one or more input elements (such as keyboard input, mouse input, touch screen/display input, motion input, movement input, audio input, pointing device input, joystick input, keypad input, etc.). The management computing entity 900 may also include or be in communication with one or more output elements (not shown), such as audio output, video output, screen/display output, motion output, movement output, etc.

As will be appreciated, one or more of the components of the management computing entity 900 may be located remotely from other management computing entity 900 components (such as in a distributed system). Further, one or more components may be combined and additional components performing the functions described herein may be included in the management computing entity 900. Thus, the management computing entity 900 may be adapted to accommodate various needs and situations. As will be appreciated, these architectures and descriptions are provided for exemplary purposes only and are not limited to the various embodiments.

The user may be an individual, a household, a company, an organization, an entity, a department within an organization, a representative of an organization and/or individual, etc. In one example, the user may be an employee, resident, customer, or the like. For example, a user may operate user device 810 including one or more components functionally similar to the components of management computing entity 900.

As shown and described herein in connection with fig. 8 and 9, in various aspects, the processing component, transmitting component, and/or receiving component (not shown) may be configured to operate one or more times, which may include aspects of managing the functionality of computing entity 900. In particular, the processing component, the transmitting component, and/or the receiving component may be configured to communicate with one or more processing elements 905, memory 910, volatile memory 915, and may include a communication interface 920 (e.g., to facilitate communication between devices).

Fig. 10 shows an example schematic diagram of a user device according to an example embodiment of the disclosure. Fig. 10 provides an illustrative illustration showing a user device 1010 (e.g., host device, storage device, peripheral device, etc.) that may be used in connection with embodiments of the present disclosure. In general, the terms device, system, computing entity, and/or the like, as used interchangeably herein, may represent, for example, one or more computers, computing entities, desktop computers, mobile phones, tablet computers, cell phones, notebook computers, laptop computers, distributed systems, gaming machines (e.g., xbox, play Station, wii), watches, glasses, key fobs, radio Frequency Identification (RFID) tags, headsets, scanners, cameras, wrist bands, self-service terminals, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, set-top boxes, repeaters, routers, network access points, base stations, and the like, and/or any combination of devices or entities suitable for performing the functions, operations, and/or processes described herein. The user device 1010 may be operated by various parties. As shown in fig. 10, the user device 1010 may include an antenna 1012, a transmitter 1004 (e.g., radio), a receiver 1006 (e.g., radio), and a processing element 1008 (e.g., CPLD, FPGA, microprocessor, multi-core processor, co-processing entity, ASIP, microcontroller, and/or controller), the processing element 1008 providing signals to the transmitter 1004 and receiving signals from the receiver 1006, respectively.

The signals provided to the transmitter 1004 and received from the receiver 1006, respectively, may comprise signaling information in accordance with the air interface standard of the applicable wireless system. In this regard, the user device 1010 may be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. More specifically, the user device 1010 may operate in accordance with any of a number of wireless communication standards and protocols, such as those described above with respect to the management computing entity 900 of fig. 9. In a particular embodiment, the user device 1010 may operate in accordance with a plurality of wireless communication standards and protocols, such as the disclosed internet of things (IoT) DOCSIS protocol, UMTS, CDMA2000, 1xRTT, WCDMA, TD-SCDMA, LTE, E-UTRAN, EVDO, HSPA, HSDPA, 5G, wi-Fi, wi-Fi direct, wiMAX, UWB, IR, NFC, bluetooth, USB, etc. Similarly, the user device 1010 may operate in accordance with a plurality of wired communication standards and protocols (such as those described above with respect to the managing computing entity 900) via the network interface 1020.

Via these communication standards and protocols, the user device 1010 may communicate with various other entities using concepts such as Unstructured Supplementary Service Data (USSD), short Message Service (SMS), multimedia Message Service (MMS), dual tone multi-frequency (DTMF) signaling, and/or subscriber identity component dialer (SIM dialer). The user device 1010 may also download changes, additions and updates to, for example, its firmware, software (e.g., including executable instructions, applications, program components), and operating system.

According to one embodiment, the user device 1010 may include location determining aspects, devices, components, functions, and/or the like, as used interchangeably herein. The location determination aspects may be used to inform a model used by a managing computing entity and one or more of the models and/or machine learning techniques described herein. For example, the user device 1010 may include an outdoor positioning aspect (such as a location component adapted to obtain, for example, latitude, longitude, altitude, geocode, route, direction, heading, speed, universal Time (UTC), date, and/or various other information/data). In one embodiment, the location component may obtain data, sometimes referred to as ephemeris data, by identifying the number of satellites in view and the relative positions of the satellites. The satellites may be a variety of different satellites including Low Earth Orbit (LEO) satellite systems, department of defense (DOD) satellite systems, european union galileo positioning systems, chinese compass navigation systems, indian regional navigation satellite systems, etc. Alternatively, the location information may be determined by triangulating the location of the user device 1010 in conjunction with various other systems, including cellular towers, wi-Fi access points, and the like. Similarly, the user device 1010 can include indoor positioning aspects (such as a location component adapted to obtain, for example, latitude, longitude, altitude, geocode, route, direction, heading, speed, time, date, and/or various other information/data). Some of the indoor systems may use various location or positioning technologies including RFID tags, indoor beacons or transmitters, wi-Fi access points, cellular towers, nearby computing devices (e.g., smartphones, laptops), etc. For example, such technologies may include iBeacon, universal proximity beacons, bluetooth Low Energy (BLE) transmitters, NFC transmitters, and the like. These indoor positioning aspects may be used in various settings to determine the position of someone or something within an inch or centimeter.

The user device 1010 may also include a user interface (which may include a display 1016 coupled to the processing element 1008) and/or a user input interface (coupled to the processing element 1008). For example, as described herein, the user interface may be a user application executing on the user device 1010 and/or accessible via the user device 1010, a browser, a user interface, and/or the like, as used interchangeably herein, to interact with and/or cause display of information from the managing computing entity. The user input interface may include any of a number of devices or interfaces that allow the user device 1010 to receive data, such as a keypad 1018 (hard or soft), a touch display, a voice/speech or motion interface, or other input device. In embodiments that include keypad 1018, keypad 1018 may include (or cause to be displayed) conventional numbers (0-9) and associated keys (#) as well as other keys for operating user device 1010, and may include a complete set of alphabetic keys or a set of keys that may be activated to provide a complete set of alphanumeric keys. In addition to providing input, the user input interface may be used, for example, to activate or deactivate certain functions (such as a screen saver and/or sleep mode).

The user apparatus 1010 may also include volatile storage or memory 1022 and/or non-volatile storage or memory 1024, which volatile storage or memory 1022 and/or non-volatile storage or memory 1024 may be embedded and/or may be removable. For example, the nonvolatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, feRAM, NVRAM, MRAM, RRAM, SONOS, FJG RAM, huperzia memory, racetrack memory, and the like. The volatile memory may be RAM、DRAM、SRAM、FPM DRAM、EDO DRAM、SDRAM、DDR SDRAM、DDR2 SDRAM、DDR3 SDRAM、RDRAM、TTRAM、T-RAM、Z-RAM、RIMM、DIMM、SIMM、VRAM、 cache memory, register memory, or the like. Volatile and nonvolatile storage devices or memories may store databases, database instances, database management systems, data, applications, programs, program components, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and the like to implement the functionality of user device 1010. As indicated, this may include a user application residing on the entity or accessible through a browser or other user interface for communicating with the managing computing entity and/or various other computing entities.

In another embodiment, as described in more detail above, the user device 1010 may include one or more components or functions that are the same as or similar to the components or functions of the managing computing entity. As will be appreciated, these architectures and descriptions are provided for exemplary purposes only and are not limited to the various embodiments.

Particular embodiments may be implemented in one or a combination of hardware, firmware, and software. Other embodiments may also be implemented as instructions stored on a computer-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. Computer-readable storage devices may include any non-transitory memory mechanism for storing information in a form readable by a machine (e.g., a computer). For example, computer-readable storage devices may include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and other storage devices and media.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The terms "computing device," "user device," "communication station," "handheld device," "mobile device," "wireless device," and "user equipment" (UE) as used herein refer to a wireless communication device, such as a cellular telephone, smart phone, tablet computer, netbook, wireless terminal, laptop computer, femtocell, or femtocell, high Data Rate (HDR) subscriber station, access point, printer, point-of-sale device, access terminal, or other Personal Communication System (PCS) device. The device may be mobile or stationary.

As used in this document, the term "communication" is intended to include transmission, or reception, or both transmission and reception. This may be particularly useful in the claims when describing the organization of data sent by one device and received by another device, but only requiring the function of one of these devices to infringe the claim. Similarly, when only the function of one of these devices is claimed, the bidirectional data exchange between two devices (both devices transmitting and receiving during the exchange) may be described as "communication". The term "communication" as used herein with respect to a wireless communication signal includes transmitting a wireless communication signal and/or receiving a wireless communication signal. For example, a wireless communication unit capable of communicating wireless communication signals may include a wireless transmitter that transmits wireless communication signals to at least one other wireless communication unit, and/or a wireless communication receiver that receives wireless communication signals from at least one other wireless communication unit.

Some embodiments may be used in conjunction with various devices and systems (e.g., personal Computers (PCs), desktop computers, mobile computers, laptop computers, notebook computers, tablet computers, server computers, handheld devices, personal Digital Assistant (PDA) devices, handheld PDA devices, in-vehicle devices, off-vehicle devices, hybrid devices, vehicle devices, off-vehicle devices, mobile or portable devices, consumer devices, non-mobile or non-portable devices, wireless communication stations, wireless communication devices, wireless Access Points (APs), wired or wireless routers, wired or wireless modems, video devices, audio-video (a/V) devices, wired or wireless networks, wireless area networks, wireless Video Area Networks (WVAN), local Area Networks (LANs), wireless LANs (WLANs), personal Area Networks (PANs), wireless PANs (WPANs), etc.).

Some embodiments may be used in conjunction with unidirectional and/or bidirectional radio communication systems, cellular radiotelephone communication systems, mobile telephones, cellular telephones, wireless telephones, personal Communication Systems (PCS) devices, PDA devices which include wireless communication devices, mobile or portable Global Positioning System (GPS) devices, devices which include GPS receivers or transceivers or chips, devices which include RFID elements or chips, multiple Input Multiple Output (MIMO) transceivers or devices, single Input Multiple Output (SIMO) transceivers or devices, multiple Input Single Output (MISO) transceivers or devices, devices with one or more internal and/or external antennas, digital Video Broadcasting (DVB) devices or systems, multi-standard radios or systems, wired or wireless handheld devices (e.g., smart phones), wireless Application Protocol (WAP) devices, and so forth.

Some embodiments may be used in conjunction with one or more types of wireless communication signals and/or systems that conform to one or more wireless communication protocols (e.g., radio Frequency (RF), infrared (IR), frequency Division Multiplexing (FDM), orthogonal FDM (OFDM), time Division Multiplexing (TDM), time Division Multiple Access (TDMA), extended TDMA (E-TDMA), general Packet Radio Service (GPRS), extended GPRS, code Division Multiple Access (CDMA), wideband CDMA (WCDMA), CDMA2000, single carrier CDMA, multi-carrier modulation (MDM), discrete Multitone (DMT), bluetooth ^TM, global Positioning System (GPS), wi-Fi, wi-Max, zigBee ^TM, ultra Wideband (UWB), global system for mobile communications (GSM), 2G, 2.5G, 3G, 3.5G, 4G, fifth generation (5G) mobile networks, 3GPP, long Term Evolution (LTE), LTE-advanced, enhanced data rates for GSM evolution (EDGE), etc.). Other embodiments may be used in various other devices, systems, and/or networks.

Although an example processing system has been described above, embodiments of the subject matter and functional operations described herein may be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

Embodiments of the subject matter and operations described herein may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more components of computer program instructions encoded on a computer storage medium for execution by, or to control the operation of, information/data processing apparatus. Alternatively or additionally, the program instructions may be encoded on a manually-generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode information/data for transmission to suitable receiver apparatus for execution by an information/data processing apparatus. The computer storage medium may be or be included in a computer readable storage device, a computer readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Furthermore, while the computer storage medium is not a propagated signal, the computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagated signal. Computer storage media may also be or be included in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

The operations described herein may be implemented as operations performed by an information/data processing apparatus on information/data stored on one or more computer-readable storage devices or received from other sources.

The term "data processing apparatus" includes all types of apparatus, devices, and machines for processing data, including for example, a programmable processor, a computer, a system-on-a-chip, or a plurality of programmable processors, computers, systems-on-a-chip, or a combination as described above. The device may comprise a dedicated logic circuit, for example an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). In addition to hardware, the apparatus may include code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them. The devices and execution environments may implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a component, subroutine, object or other unit suitable for use in a computing environment. The computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or information/data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store multiple portions of one or more components, sub-programs, or code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input information/data and generating output. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and information/data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive information/data from or transfer information/data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, the computer need not have such devices. Devices suitable for storing computer program instructions and information/data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disk; CD-ROM and DVD-ROM discs. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

To provide for interaction with a user, embodiments of the subject matter described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information/data to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other types of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may receive input from a user in any form including acoustic, speech, or tactile input. Further, the computer may interact with the user by sending and receiving documents to and from the device used by the user; for example, by sending web pages to a web browser on a user's client device in response to requests received from the web browser.

Embodiments of the subject matter described herein can be implemented in a computing system that includes a back-end component, e.g., as an information/data server, or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with an embodiment of the subject matter described herein), or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital information/data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), internetworks (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, the server sends information/data (e.g., HTML pages) to the client device (e.g., for the purpose of displaying information/data to and receiving user input from a user interacting with the client device). Information/data generated at the client device (e.g., results of user interactions) may be received at the server from the client device.

While this specification contains many specifics of specific embodiments, these should not be construed as limitations on the scope of any embodiments or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying drawings do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In particular embodiments, multitasking and parallel processing may be advantageous.

Many modifications and other embodiments of the disclosure set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the embodiments are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. An electronic system, the electronic system comprising:

A controller;

one or more computing resources; and

One or more memory resources;

Wherein the controller is configured to:

receiving a command specifying an amount of computing resources and an amount of memory resources associated with a program; and

Processing the command, wherein the processing includes dynamically allocating a portion of the one or more computing resources and allocating a portion of the one or more memory resources for use by the program based on the command.

2. The electronic system of claim 1, wherein the command specifies that the portion of the one or more memory resources is restricted from access.

3. The electronic system of claim 1, wherein the controller determines that the program attempts to access an area of the one or more memory resources that is different from the portion of the allocation of the one or more memory resources and the controller stops execution of the program.

4. The electronic system of claim 1, wherein the one or more memory resources comprise one or more local memory namespaces.

5. The electronic system of claim 1, wherein the electronic system comprises one or more storage resources comprising one or more storage namespaces.

6. The electronic system of claim 1, wherein the program is a first program in a multi-tenant environment comprising at least a second program.

7. The electronic system of claim 1, wherein the command is based on a protocol that includes a nonvolatile memory flash.

8. The electronic system of any of claims 1-7, wherein the one or more computing resources comprise computing resources including at least one of a central processor, a graphics processor, a field programmable gate array, a tensor processor, and an application specific integrated circuit.

9. The electronic system of any of claims 1-7, wherein the electronic system comprises a computing storage device comprising the one or more computing resources and the one or more memory resources, the computing storage device being a storage device that supports non-volatile memory flash.

10. A method for managing memory, the method comprising:

receiving, by a controller, a command specifying an amount of computing resources and an amount of memory resources associated with a program; and

Processing, by the controller, the command, wherein the processing includes dynamically allocating a portion of one or more computing resources and allocating a portion of one or more memory resources for use by the program based on the command.

11. The method of claim 10, wherein the command specifies that the portion of the one or more memory resources is restricted from access.

12. The method of claim 10, wherein the method further comprises: determining that the program attempts to access an area of the one or more memory resources that is different from the portion of the allocation of the one or more memory resources, and stopping execution of the program.

13. The method of claim 10, wherein the program is a first program in a multi-tenant environment comprising at least a second program.

14. The method of any of claims 10 to 13, wherein the command is based on a protocol that includes non-volatile memory express.

15. An apparatus for managing memory, the apparatus comprising:

A controller;

Wherein the controller is configured to:

Processing the command, wherein the processing includes dynamically allocating a portion of one or more computing resources and allocating a portion of one or more memory resources for use by the program based on the command.

16. The apparatus of claim 15, wherein the command specifies that the portion of the one or more memory resources is restricted from access.

17. The apparatus of claim 15, wherein the controller is further configured to determine that the program is attempting to access the one or more memory resources in a different area than the portion of the allocation of the one or more memory resources and to stop execution of the program.

18. The apparatus of claim 15, wherein the program is a first program in a multi-tenant environment comprising at least a second program.

19. The apparatus of claim 15, wherein the command is based on a protocol comprising a nonvolatile memory flash.

20. A non-transitory computer-readable storage medium storing instructions that, when executed by a controller, cause the controller to perform the method of any of claims 10 to 14.