CN118102730A - Novel charge trapping split gate flash memory and manufacturing process thereof - Google Patents

Abstract

The invention provides a novel charge trapping split gate flash memory and a manufacturing process thereof. The memory cell of the memory includes: a substrate, a source region and a drain region, a select transistor and a memory transistor on each side. The left side memory transistor and the right side memory transistor are symmetrical structures and belong to the SONOS type memory principle. The left and right ONO dielectric layers and their corresponding control gates are all fabricated by an intermediate select gate sidewall process. The flash memory cell structure has the advantages of high density and high efficiency operation.

Description

Novel charge trapping split gate flash memory and manufacturing process thereof

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a novel charge trapping split gate flash memory and a manufacturing process thereof.

Background

The charge trapping split gate unit can be applied to not only universal MCU, but also industrial and automobile application MCU and other fields needing to have high-speed random reading characteristics, extremely low defect rate and severe high-temperature durability.

The storage medium layer of the traditional flash memory is a polysilicon floating gate, and the charge trapping type is made of silicon nitride material for charge storage. In the case of polysilicon floating gate type cells, the storage region is a conductor. When there is a conductive defect in the oxide film around the polysilicon floating gate, all stored charge is eventually lost through the defect. In contrast, for charge trapping memories, the storage region is a charge trap in a thin silicon nitride film of an insulating layer. The traps are distributed individually and only charge in the vicinity of the defect is lost. That is, more reliable in nature. The structure realizes the storage operation and the erasing operation of charges, so that the memory has different threshold voltages in a storage state and an erasing state, and further the logical 0 and 1 states are distinguished by reading leakage currents (of different orders of magnitude) in the two states. Nitride thin film memory has high compatibility with logic CMOS. Low power programming can be achieved using source side injection channel hot electrons (SSI-CHE). In addition, there is no High Voltage (HV) in the low voltage word line drive and read path, enabling high speed random read of >100MHz, lower power consumption read operations and smaller flash cell sizes.

The technical indexes of the memory mainly comprise: memory cell size, program erase operation efficiency and reliability. Firstly, with the development of the miniaturization of semiconductor integrated circuits, the floating gate memories of the conventional stacked gate structures are gradually unable to meet the requirements, and the reduction of the cell size is often realized by a novel structure and a new memory layer material. In addition, the conventional charge trapping memory can cause irreversible electrical damage to the tunneling dielectric layer through repeated programming and erasing operations under high operating voltage, so that the electrical performance of the memory is gradually affected, and the reliability can not reach the standard. Therefore, it is of great significance to propose a charge trapping memory of a novel structure with high density, high operation efficiency and high reliability, which satisfies the increasing market demand.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a novel charge trapping split gate flash memory and a manufacturing method thereof, which can realize high-density, high-reliability and high-operation efficiency information storage.

In a first aspect, the present invention provides a charge trapping split gate flash memory comprising a plurality of memory cells, wherein each memory cell comprises a substrate, and a transistor, a drain region, and a source region over the substrate; wherein the drain region and the source region are respectively configured at two sides of the transistor; a bottom dielectric layer is arranged between the transistor and the substrate;

The transistors comprise a selection transistor, a first ONO type storage transistor and a second ONO type storage transistor which are respectively arranged at two sides of the selection transistor;

The select transistor includes a polysilicon select gate;

The first ONO type storage transistor and the second ONO type storage transistor have the same structure and comprise an ONO type dielectric layer and a control grid.

In one embodiment, the first ONO memory transistor, the selection transistor and the second ONO memory transistor are sequentially connected in series.

In one embodiment, the cross section of the ONO type dielectric layer is in an L-shaped structure, the outer side is in contact with the selection transistor, and the inner side wraps the control gate.

In one embodiment, the cross section of the ONO type dielectric layer comprises a vertical arm and a horizontal arm which are vertically arranged; the longitudinal arm is adjacent to the select transistor and the horizontal arm is below the control gate.

In one embodiment, the top of the longitudinal arm of the ONO type dielectric layer is closer to the side of the selection transistor than the top of the longitudinal arm is farther from the side of the selection transistor.

In one embodiment, the height of the longitudinal arms of the ONO type dielectric layer is flush with the height of the select transistor.

In one embodiment, the bottom dielectric layer has a thickness of 50-150 angstroms.

In one embodiment, the ONO type dielectric layer has a thickness of 100-200 angstroms, and the silicon nitride has a thickness of 50-90 angstroms.

In one embodiment, the bottom dielectric layer is made of silicon oxide, and the select gate is made of polysilicon.

In a second aspect, the present invention provides a process for manufacturing the above memory, comprising the steps of:

forming a bottom dielectric layer on a silicon substrate;

forming a select gate on the bottom dielectric layer to form a select transistor;

Forming an ONO type dielectric layer and a control grid on two side walls of the selection grid structure in sequence, removing redundant parts of the ONO type dielectric layer and the control grid to form a first ONO type storage transistor and a second ONO type storage transistor,

Source and drain regions located on both sides of the first and second ONO type memory transistors by ion implantation;

contact holes, metal layers and vias are formed to realize external connection of the memory.

Compared with the prior art, the invention has the beneficial effects that:

The invention provides a novel charge trapping split gate flash memory structure unit and a manufacturing method thereof. The steps play a role in collaborative optimization on main technical indexes of the memory, and the novel charge trapping split gate memory has high density, high efficiency, low power consumption and high reliability.

Drawings

FIG. 1 is a schematic cross-sectional view of a charge trapping split gate flash memory according to the present invention;

FIG. 2 is a schematic diagram of a process flow of fabricating a charge trapping split gate flash memory according to the present invention;

FIG. 3 is a schematic cross-sectional view illustrating a main process flow of a charge trapping split gate flash memory according to the present invention; wherein the a-f diagrams correspond to the step flows a-f respectively;

the marks in the figure: 1. a Si substrate; 2. a source region S; 3. a drain region D; 4. a bottom silicon oxide dielectric layer; 5. an intermediate polysilicon select gate SG; 6. a left side ONO dielectric layer; 7. a left control gate; 8. a right side ONO dielectric layer; 9. and a right control gate.

Detailed Description

The invention will be described in further detail with reference to the drawings and the detailed description.

FIG. 1 is a schematic cross-sectional view of a charge trapping flash memory according to the present invention;

the memory cell is located on a Si substrate 1, comprising: a source region S2, a drain region D3, a bottom silicon oxide dielectric layer 4, an intermediate polysilicon select gate SG 5, a left ONO (silicon oxide-silicon nitride-silicon oxide) dielectric layer 6, a left control gate CG 7, a right ONO dielectric layer 8, a right control gate CG 9. Compared with the traditional stacked gate structure, the novel unit structure provided by the invention can reduce the unit size and improve the operation efficiency of the memory.

A left ONO (silicon oxide-silicon nitride-silicon oxide) dielectric layer 6 is located between the middle polysilicon select gate SG5 and the left control gate CG 7. A right ONO type dielectric layer 8 is located between the middle polysilicon select gate SG5 and the right control gate CG 9.

The thickness of the inter-gate silicon oxide-silicon nitride-silicon oxide dielectric layer is between 100 and 150 angstroms, wherein the thickness of the silicon nitride is between 50 and 90 angstroms, respectively.

The control gate CG is half-clad with an inter-gate silicon oxide-silicon nitride-silicon oxide dielectric layer.

The left side ONO type dielectric layer 6 and the right side ONO type dielectric layer 8 are of back-to-back and axisymmetric L-shaped structures.

FIG. 2 is a schematic diagram of a process flow of fabricating a charge trapping flash memory according to the present invention;

The inter-polysilicon select gate SG5 is patterned on the silicon substrate by, for example, a deposition process and a subsequent etching process.

Subsequently, an L-shaped inter-gate silicon oxide-silicon nitride-silicon oxide dielectric layer is formed on the basis of the inter-polysilicon select gate SG5 by, for example, a deposition process for preparing a sidewall and an etching process.

Left and right control gates CG are then patterned by deposition and etching processes.

Ion implantation doping is carried out on the source electrode region and the drain electrode region, and the specific N type or P type doping is determined by the design of the element.

Finally, the contact hole, the metal layer and the through hole are formed through patterning process to realize external connection of the memory unit.

FIG. 3 is a schematic cross-sectional view illustrating a main process flow of fabricating a charge trapping flash memory according to the present invention;

a) A bottom silicon oxide dielectric layer 4, a polysilicon gate and a hard mask layer are formed on a silicon substrate by, for example, a deposition process, and then the hard mask layer, the polysilicon gate and the bottom silicon oxide dielectric layer 4 are sequentially etched by an etching process to form an intermediate polysilicon select gate SG5.

B) An inter-gate silicon oxide-silicon nitride-silicon oxide dielectric layer may then be formed on the basis of the select transistor by, for example, a deposition process.

C) Etching to remove the redundant inter-gate silicon oxide-silicon nitride-silicon oxide dielectric layer by an etching process;

d) Left and right control gates CG are formed by patterning by a deposition process and an etching process. And finally forming the side walls of the selection transistor, namely the inter-gate silicon oxide-silicon nitride-silicon oxide layer and the control gates on the left side and the right side.

E) The source region and the drain region on two sides of the main body part formed by the right transistor, the middle transistor and the left transistor are doped with N type or P type through ion implantation, and the specific N type or P type doping depends on the design of the element.

F) And finally, forming a contact hole, a metal layer and a through hole through a deposition process and a patterning process of a photoetching process to realize external connection of the memory unit.

The novel flash memory cell structure according to the present invention has the advantages of high density, high reliability and efficient operation.

Claims (10)

1. A charge trapping split gate flash memory comprising a plurality of memory cells, wherein each memory cell comprises a substrate, and a transistor, a drain region, and a source region over the substrate; wherein the drain region and the source region are respectively configured at two sides of the transistor; a bottom dielectric layer is arranged between the transistor and the substrate;

The transistors comprise a selection transistor, a first ONO type storage transistor and a second ONO type storage transistor which are respectively arranged at two sides of the selection transistor;

The select transistor includes a polysilicon select gate;

The first ONO type storage transistor and the second ONO type storage transistor have the same structure and comprise an ONO type dielectric layer and a control grid.

2. The memory of claim 1 wherein the first ONO type memory transistor, the select transistor, and the second ONO type memory transistor are sequentially connected in series.

3. The memory of claim 1 wherein said ONO type dielectric layer has an L-shaped cross-section, with an outer side in contact with said select transistor and an inner side surrounding said control gate.

4. The memory of claim 1, wherein a cross-section of said ONO type dielectric layer comprises a vertical arm and a horizontal arm disposed vertically; the longitudinal arm is adjacent to the select transistor and the horizontal arm is below the control gate.

5. The memory of claim 4 wherein a top of a longitudinal arm of said ONO type dielectric layer is higher near said select transistor side than a top of a longitudinal arm is farther from said select transistor side.

6. The memory of claim 4 wherein the vertical arm height of said ONO type dielectric layer is level with the height of said select transistor.

7. The memory of claim 1 wherein said bottom dielectric layer has a thickness of 50-150 angstroms.

8. The memory of claim 1 wherein said ONO type dielectric layer is 100-200 angstroms thick and wherein silicon nitride is 50-90 angstroms thick.

9. The memory of claim 1 wherein the bottom dielectric layer is silicon oxide and the select gate is polysilicon.

10. A process for manufacturing a memory according to any of claims 1-9, characterized by the steps of:

forming a bottom dielectric layer on a silicon substrate;

forming a select gate on the bottom dielectric layer to form a select transistor;

Forming an ONO type dielectric layer and a control grid on two side walls of the selection grid structure in sequence, removing redundant parts of the ONO type dielectric layer and the control grid to form a first ONO type storage transistor and a second ONO type storage transistor,

Source and drain regions located on both sides of the first and second ONO type memory transistors by ion implantation;

contact holes, metal layers and vias are formed to realize external connection of the memory.