CN118100872B - Double J-K positive edge trigger and semiconductor device - Google Patents
Double J-K positive edge trigger and semiconductor device Download PDFInfo
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- CN118100872B CN118100872B CN202410509620.1A CN202410509620A CN118100872B CN 118100872 B CN118100872 B CN 118100872B CN 202410509620 A CN202410509620 A CN 202410509620A CN 118100872 B CN118100872 B CN 118100872B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
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- 230000002708 enhancing effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 15
- 230000009977 dual effect Effects 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 230000001976 improved effect Effects 0.000 abstract description 4
- 230000001965 increasing effect Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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Abstract
The application provides a double J-K positive edge trigger and a semiconductor device, wherein the double J-K positive edge trigger comprises: a trigger body, an anti-latch-up structure, and an ESD protection circuit; in the layout of the double J-K positive edge trigger, the distance between the PMOS and the NMOS is larger than a specified distance threshold value, and an anti-latch structure is arranged between the PMOS and the NMOS; one end of the ESD protection circuit is connected with the internal circuit of the trigger body; the other end of the ESD protection circuit is connected with a PAD in the layout; the ESD protection circuit is used for enhancing the antistatic capability of the trigger. The anti-latch-up structure and the enhanced ESD protection structure are added in the trigger, so that the anti-latch-up capability of the trigger can be improved, and parasitic effects can be avoided.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a double J-K positive edge trigger and a semiconductor device.
Background
In the existing double J-K positive edge trigger, the protection capability of ESD is weak, the ESD is a serious problem in a CMOS circuit, and the P-tube and N-tube grid are interconnected in the product, so that the latch-up resistance is weak.
Disclosure of Invention
The application aims to provide a double J-K positive edge trigger and a semiconductor device, wherein an anti-latch-up structure and an enhanced ESD protection structure are added in the trigger, so that the anti-latch-up capability of the trigger can be improved, and parasitic effects can be avoided.
In a first aspect, the present application provides a dual J-K positive edge flip-flop comprising: a trigger body, an anti-latch-up structure, and an ESD protection circuit; in the layout of the double J-K positive edge trigger, the distance between the PMOS and the NMOS is larger than a specified distance threshold value, and an anti-latch structure is arranged between the PMOS and the NMOS; one end of the ESD protection circuit is connected with the internal circuit of the trigger body; the other end of the ESD protection circuit is connected with a PAD in the layout; the ESD protection circuit is used for enhancing the antistatic capability of the trigger.
Further, the latch-up preventing structure includes: n+ rings are arranged around the P well and the PMOS tube, and P+ rings are arranged in the P well to avoid latch-up effect.
Further, VCC is looped around the PMOS transistor, and GND is looped around the NMOS transistor in the P-well.
Furthermore, a plurality of contact holes are distributed around the P-well and the PMOS tube and in the P-well, so that well contact and substrate contact are carried out through the contact holes, and parasitic resistance of the substrate and the P-well is reduced.
Further, the ESD protection circuit includes: two sets of diodes and a polycrystalline structure.
Further, each set of diodes includes two diodes.
Further, each diode is embedded in the substrate as described above to protect the circuit and not increase the chip area.
Further, the polycrystalline structure comprises a polycrystalline resistor; one end of the polycrystalline resistor is respectively connected with the anode of the first diode, the cathode of the second diode and the PAD; the other end of the polycrystalline resistor is respectively connected with the anode of the third diode, the cathode of the fourth diode and the internal circuit of the trigger; the cathode of the first diode and the cathode of the third diode are both connected with a high level; the cathode of the third diode and the anode of the fourth diode are grounded.
Further, the specified distance threshold is a distance value determined according to a process.
In a second aspect, the present application also provides a semiconductor device, which includes the dual J-K positive edge flip-flop according to the first aspect.
In the dual J-K positive edge trigger and the semiconductor device provided by the application, the dual J-K positive edge trigger comprises: a trigger body, an anti-latch-up structure, and an ESD protection circuit; in the layout of the double J-K positive edge trigger, the distance between the PMOS and the NMOS is larger than a specified distance threshold value, and an anti-latch structure is arranged between the PMOS and the NMOS; one end of the ESD protection circuit is connected with the internal circuit of the trigger body; the other end of the ESD protection circuit is connected with a PAD in the layout; the ESD protection circuit is used for enhancing the antistatic capability of the trigger. The anti-latch-up structure and the enhanced ESD protection structure are added in the trigger, so that the anti-latch-up capability of the trigger can be improved, and parasitic effects can be avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a layout of a prior art double J-K positive edge trigger;
FIG. 2 is a layout corresponding to a double J-K positive edge trigger according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a contact hole in a layout corresponding to a double J-K positive edge trigger according to an embodiment of the present application;
FIG. 4 is a layout of an ESD protection circuit according to an embodiment of the present application;
Fig. 5 is a schematic structural diagram of an ESD protection circuit according to an embodiment of the present application.
Detailed Description
The technical solutions of the present application will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the design of dual J-K positive edge flip-flops, latch-up may occur, which is common in CMOS and may lead to failure of the CMOS circuit if not resolved and to burning out of the chip if severe. Under normal operating conditions, latch-up results from an N-P-N-P structure consisting of the active region of the NMOS, the N substrate, the P well, the active region of the PMOS.
Based on the above, the embodiment of the application provides a double J-K positive edge trigger and a semiconductor device, wherein an anti-latch-up structure and an enhanced ESD protection structure are added in the trigger, so that the anti-latch-up capability of the trigger can be improved, and parasitic effects can be avoided.
For the convenience of understanding the present embodiment, a dual J-K positive edge trigger disclosed in the present embodiment will be described in detail.
The embodiment of the application provides a double J-K positive edge trigger, which comprises: a trigger body, an anti-latch-up structure, and an ESD protection circuit; the flip-flop body includes two NAND gates and an inverter. Wherein the inputs of the first NAND gate are the J signal and the inverse of the clock signal CLK, and the inputs of the second NAND gate are the K signal and the clock signal CLK. The J signal and the K signal are respectively connected with the NAND gates, and the working states of the flip-flops are controlled through a clock signal CLK. When the clock signal arrives, the state of the flip-flop changes according to the input states of J and K. Inverters are commonly used in logic circuits to invert a signal. In a J-K flip-flop, an inverter is used to connect the output of the first NAND gate to the input of the second NAND gate to achieve feedback to ensure the stability of the flip-flop. The outputs Q and Q' are connected to respective NAND gates for outputting the two states of the flip-flop. When j=k=1, the outputs Q and Q' will remain unchanged.
In the layout of the double J-K positive edge trigger, the distance between the PMOS and the NMOS is larger than a specified distance threshold, and the specified distance threshold is a distance value determined according to a process. An anti-latch-up structure is arranged between the PMOS and the NMOS; one end of the ESD protection circuit is connected with the internal circuit of the trigger body; the other end of the ESD protection circuit is connected with a PAD in the layout; the ESD protection circuit is used for enhancing the antistatic capability of the trigger.
In the design of the dual J-K positive edge flip-flop provided in the embodiment of the present application, the gates of the PMOS and NMOS transistors need to be separated first, as shown in fig. 1 and 2. In which, fig. 1 shows the layout of the existing double J-K positive edge trigger, it can be seen that the PMOS and NMOS gates are connected together, and the two pipes are relatively close in distance, so that a coupling effect is easy to form, and there is a risk of latch-up; fig. 2 shows a corresponding layout in the dual J-K positive edge trigger provided by the embodiment of the present application, it can be seen that, in the optimized layout, the gate is disconnected, the distance between the two tubes is increased, and an anti-latch structure is added in the middle to block the coupling and control the flow of current, so as to avoid latch.
Secondly, parasitic resistance of the substrate and the P well is reduced, well contact and substrate contact are required to be performed through punching, as shown in fig. 3, a plurality of contact holes are distributed around the P well and the PMOS tube and in the P well, substrate contact is performed through the contact holes of the T-shaped area, parasitic resistance is reduced, well contact is performed through the contact holes of the two areas on the right side, and parasitic resistance of the P well is reduced.
Finally, collecting injected carriers by using a protection ring, arranging N+ rings around the P well and the PMOS tube, arranging P+ rings in the P well, connecting VCC around the PMOS tube, and connecting GND around the NMOS tube in the P well to avoid latch-up effect.
In summary, the method for avoiding latch-up provided by the embodiment of the application is as follows: reducing parasitic resistance of the substrate and the P-well, strictly following the distance rule between the N+ active region in the P-well and the P+ active region of the substrate and the P-well and substrate contact rule, increasing the spacing and using guard rings at the I/O pressure points to improve the latch-up capability.
Further, in addition to the anti-latch-up structure described above, the embodiment of the present application further provides an ESD protection circuit to improve the anti-static capability. The ESD protection circuit includes: two sets of diodes and a polycrystalline structure. Each set of diodes comprises two diodes. As shown in fig. 4, embedding each diode in the substrate can protect the circuit without increasing the chip area.
Referring to fig. 5, the polycrystalline structure includes a polycrystalline resistor; one end of the polycrystalline resistor is respectively connected with the anode of the first diode, the cathode of the second diode and the PAD; the other end of the polycrystalline resistor is respectively connected with the anode of the third diode, the cathode of the fourth diode and the internal circuit of the trigger; the cathode of the first diode and the cathode of the third diode are both connected with a high level; the cathode of the third diode and the anode of the fourth diode are grounded.
The ESD protection circuit prevents the working circuit from being damaged due to being an ESD discharge path, ensures that the ESD generated between any two chip pins has a proper low-resistance bypass to lead the ESD current into the power line. Most of the ESD current comes from outside the circuit, so the ESD protection circuit is typically designed beside the PAD, inside the I/O circuit, which typically consists of both the output driver and the input receiver. ESD is led into the chip through the PAD, so that all devices directly connected with the PAD in the I/O are required to be provided with an ESD electrostatic structure, ESD current is led into voltage lines, and then the voltage lines are distributed to all pins of the chip, thereby reducing the influence of the ESD. In particular, to an I/O circuit, i.e., an output driver and input receiver connected to a PAD, it is necessary to ensure that a low resistance channel is formed in parallel with the protection circuit when ESD occurs, bypassing the ESD current, and immediately and effectively clamping the protection circuit voltage. And when the two parts work normally, the normal work of the circuit is not influenced.
In the double J-K positive edge trigger provided by the embodiment of the application, the PMOS and NMOS transistors are separated, the distance between the MOS transistors at the upper end and the lower end is increased, and the latch-up effect is avoided; substrate contact is increased, parasitic effect is avoided, and bypass resistance is limited; the double protection rings are added to absorb current carriers, so that latch-up is avoided; and an ESD protection circuit is added, so that the antistatic capability is enhanced.
The key points of the embodiment of the application are as follows:
1. The PMOS tube and the NMOS tube are separated, an anti-latch structure is added in the middle, and then the wires are re-wired.
2. And adding a P+ ring in the P well, and surrounding the P+ ring by using a GND line and arranging contact holes as much as possible. And (3) arranging an N+ ring outside the P well and the PMOS tube, surrounding the N+ ring by using a VCC wire, and arranging contact holes as much as possible. The contact areas are enlarged as much as possible at the connection place of the PMOS tube and the NMOS tube, and the contact holes are distributed as much as possible, so that the direct connection is avoided, and the diode is formed.
3. And a diode is added at the input of the circuit to form an ESD protection circuit, so that stronger electrostatic protection is realized.
Based on the above trigger embodiment, the embodiment of the present application further provides a semiconductor device, where the semiconductor device includes the dual J-K positive edge trigger as described in the above embodiment.
The implementation principle and the technical effects of the semiconductor device provided by the embodiment of the present application are the same as those of the trigger embodiment, and for the sake of brevity, reference may be made to the corresponding content in the trigger embodiment.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (2)
1. A dual J-K positive edge trigger, the dual J-K positive edge trigger comprising: a trigger body, an anti-latch-up structure, and an ESD protection circuit;
In the layout of the double J-K positive edge trigger, the distance between the PMOS and the NMOS is larger than a specified distance threshold value, and the latch-up resisting structure is arranged between the PMOS and the NMOS; the specified distance threshold is a distance value determined according to a process;
One end of the ESD protection circuit is connected with an internal circuit of the trigger body; the other end of the ESD protection circuit is connected with a PAD in the layout; the ESD protection circuit is used for enhancing the antistatic capability of the trigger; the ESD protection circuit includes: two sets of diodes and a polycrystalline structure; each group of diodes comprises two diodes; embedding each diode in the substrate to protect the circuit and not increase the chip area; the polycrystalline structure comprises a polycrystalline resistor; one end of the polycrystalline resistor is respectively connected with the anode of the first diode, the cathode of the second diode and the PAD; the other end of the polycrystalline resistor is respectively connected with the anode of the third diode, the cathode of the fourth diode and the internal circuit of the trigger; the cathode of the first diode and the cathode of the third diode are both connected with high level; the cathode of the third diode and the anode of the fourth diode are grounded;
The anti-latch-up structure includes: n+ rings are arranged around the P well and the PMOS tube, and P+ rings are arranged in the P well to avoid latch-up effect; the periphery of the PMOS tube is connected with VCC in a looping way, and the periphery of the NMOS tube in the P well is connected with GND in a looping way; and a plurality of contact holes are distributed around the P well and the PMOS tube and in the P well so as to carry out well contact and substrate contact through the contact holes, thereby reducing parasitic resistance of the substrate and the P well.
2. A semiconductor device comprising the dual J-K positive edge trigger of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410509620.1A CN118100872B (en) | 2024-04-26 | 2024-04-26 | Double J-K positive edge trigger and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410509620.1A CN118100872B (en) | 2024-04-26 | 2024-04-26 | Double J-K positive edge trigger and semiconductor device |
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| CN118100872B true CN118100872B (en) | 2024-07-02 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399264A (en) * | 2007-05-17 | 2009-04-01 | 沙诺夫公司 | Cdm ESD protection for integrated circuits |
| CN103633086A (en) * | 2013-12-19 | 2014-03-12 | 电子科技大学 | Anti-latch-up SCR (Semiconductor Control Rectifier) with low trigger voltage for ESD (Electro-Static Discharge) protection |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6803633B2 (en) * | 2001-03-16 | 2004-10-12 | Sarnoff Corporation | Electrostatic discharge protection structures having high holding current for latch-up immunity |
| CN103681660B (en) * | 2013-12-13 | 2015-12-30 | 江南大学 | A kind of high-voltage ESD protective device of annular LDMOS-SCR structure of dual latch-up |
| CN103886158B (en) * | 2014-03-31 | 2017-01-25 | 西安空间无线电技术研究所 | Standard cell design method resistant to single-particle latch-up effect |
| US10741548B2 (en) * | 2015-04-13 | 2020-08-11 | Infineon Technologies Ag | Protection devices with trigger devices and methods of formation thereof |
| CN117766534A (en) * | 2023-12-22 | 2024-03-26 | 天水天光半导体有限责任公司 | Three 3-input AND gate and semiconductor structure thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399264A (en) * | 2007-05-17 | 2009-04-01 | 沙诺夫公司 | Cdm ESD protection for integrated circuits |
| CN103633086A (en) * | 2013-12-19 | 2014-03-12 | 电子科技大学 | Anti-latch-up SCR (Semiconductor Control Rectifier) with low trigger voltage for ESD (Electro-Static Discharge) protection |
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