CN112786586A - Integrated circuit with high ESD grade - Google Patents

Integrated circuit with high ESD grade Download PDF

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Publication number
CN112786586A
CN112786586A CN202110194975.2A CN202110194975A CN112786586A CN 112786586 A CN112786586 A CN 112786586A CN 202110194975 A CN202110194975 A CN 202110194975A CN 112786586 A CN112786586 A CN 112786586A
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CN
China
Prior art keywords
circuit
pad port
diode
pad
port
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Pending
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CN202110194975.2A
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Chinese (zh)
Inventor
熊伟
张军
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Beijing Core Vision Software Technology Co ltd
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Beijing Core Vision Software Technology Co ltd
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Priority to CN202110194975.2A priority Critical patent/CN112786586A/en
Publication of CN112786586A publication Critical patent/CN112786586A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to an integrated circuit with high ESD level, which comprises a first PAD port, a second PAD port, a third PAD port, an ESD1 circuit, an ESD2 circuit, a PMOS transistor P1 and a diode D1, wherein the ESD1 circuit comprises an NMOS transistor N1, an ESD2 circuit comprises an NMOS transistor N2, the ESD1 circuit is connected to the first PAD port and the third PAD port, the ESD2 circuit is connected to the second PAD port and the third PAD port, the PMOS transistor P1 is connected to the first PAD port and the second PAD port, a cathode of the diode D1 is connected with the first PAD port, an anode of the diode D1 is connected with the second PAD port, and the PMOS transistor and the NMOS transistor are separated through the diode D1, so that the latch-up resistance of a chip can be effectively improved, and the area of the chip can be reduced.

Description

Integrated circuit with high ESD grade
Technical Field
The invention relates to the field of integrated circuit design, in particular to an integrated circuit design with high ESD level.
Background
In most integrated circuits, VDD generated by an internal regulator is used as a power supply voltage in addition to VCC voltage inputted from the outside, and VDD is generated by VCC, and in order to provide a large current path from VCC to VDD, a PMOS transistor needs to be amplified between VCC and VDD.
Conventionally, a large PMOS tube and a regulator or other circuits are placed together in an internal area of a chip, and only an IO circuit, including a corresponding ESD circuit, is placed in an IO area of the chip. There are some disadvantages to this approach: firstly, wiring resources are wasted, a relatively thick power line needs to be drawn from a VCC pin and connected to an internal PMOS transistor, and if the power line is far away from the PMOS transistor, more wiring space is consumed; and the PMOS tube is not utilized as an auxiliary element for ESD discharge.
To address the above disadvantages, large PMOS transistors are typically placed relatively close to PAD for VDD and VCC, typically in the IO region. However, this also has the disadvantage that when VCC, VDD, GND and 3 PADs are closer, it will result in ESD circuits for VCC and ESD circuits for VDD and large PMOS being also closer, which easily causes latch-up.
Disclosure of Invention
In view of this, the present invention provides an integrated circuit with a high ESD level, which can effectively improve the wiring efficiency by reasonably laying out the PAD ports (VCC, VDD, GND), the PMOS, the diodes, and the layout positions of the ESD circuit; furthermore, through the special layout of the diode and the PMOS layout, the ESD grade is improved, the latch-up resistance is improved, and the chip area is reduced.
The technical scheme of the invention is as follows: an integrated circuit with high ESD level, comprising a first PAD port, a second PAD port, a third PAD port, an ESD1 circuit, an ESD2 circuit, a PMOS transistor P1, and a diode D1, wherein the ESD1 circuit comprises an NMOS transistor N1, the ESD2 circuit comprises an NMOS transistor N2, the ESD1 circuit is connected to the first PAD port and the third PAD port, the ESD2 circuit is connected to the second PAD port and the third PAD port, the PMOS transistor P1 is connected to the first PAD port and the second PAD port, a cathode of the diode D1 is connected to the first PAD port, and an anode of the diode D1 is connected to the second PAD port, the integrated circuit is characterized in that: the diode separates the PMOS transistor from the NMOS transistor.
Furthermore, the layout of the diode is in a U shape and surrounds the PMOS transistor.
Further, two ESD circuits are placed on both sides of the diode.
Further, the layout of the diode is T-shaped, and the PMOS transistor is separated from the ESD circuit.
Further, an ESD1 circuit is adjacent to PAD port VCC.
Furthermore, the layout sequentially comprises a PMOS transistor, a diode and an ESD circuit from top to bottom.
Further, an ESD1 circuit is adjacent to PAD port VCC.
The PMOS transistor is separated from the ESD circuit through the diode, the chip area can be saved, and the NMOS is used as a discharge tube and is separated from the PMOS, so that the PMOS transistor is effectively protected.
The PMOS and the NMOS are separated by the diode, so that the latch-up resistance of the chip can be effectively improved, and the area of the chip can be reduced.
Furthermore, after the ESD time of the PMOS transistor occurs, the PMOS transistor is in a complete opening state, and the equivalent resistance value of the PMOS transistor is smaller at the moment, so that a larger current path can be provided. This is equivalent to discharging the ESD bleeder circuit using both VDD and VCC with the PMOS transistor, increasing the ESD rating.
Drawings
FIG. 1 is a schematic diagram of a high ESD rating integrated circuit of the present invention.
Fig. 2 is a layout of the first embodiment of the present invention.
Fig. 3 is a variation of the layout of the first embodiment of the present invention.
Fig. 4 is a layout of the second embodiment of the present invention.
Fig. 5 is a layout of the third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An ESD integrated circuit, as shown in fig. 1, includes 3 PAD ports, i.e. a first PAD port VCC, a second PAD port VDD, and a third PAD port GND, two ESD circuits, a diode D1, and a PMOS transistor P1. One end (source end/drain end) of the PMOS transistor P1 is connected with a first PAD port VCC, and the other end (drain end/source end) is connected with a second PAD port VDD; the diode D1 is connected in parallel with the PMOS transistor P1, the cathode of the diode D1 is connected with the first PAD port VCC, and the anode is connected with the second PAD port VDD; the ESD1 circuit is arranged between the first PAD port VCC and the third PAD port GND, one end of the ESD1 circuit is connected with the first PAD port VCC, the other end of the ESD1 circuit is connected with the third PAD port GND, the further ESD1 circuit comprises an NMOS transistor N1, wherein the grid electrode of the NMOS transistor N1 is connected with an RC Detect circuit; the ESD2 circuit is arranged between the second PAD port VDD and the third PAD port GND, one end of the ESD2 circuit is connected with the second PAD port VDD, the other end of the ESD2 circuit is connected with the third PAD port GND, and the further ESD2 circuit comprises an NMOS transistor N2, wherein the grid electrode of the NMOS transistor N2 is connected with the RC Detect circuit.
In layout design, in order to prevent latch-up of a chip, the following three methods are generally adopted:
the first approach is to maintain a sufficiently large spacing between the NMOS and PMOS transistors to reduce the chance of triggering the SCR. And simultaneously, power lines and ground lines in the layout are thickened as much as possible. Although the method can achieve good effect, the method has the defect that the area of the layout is increased.
The second method, adding Guard Ring, not only prevents latch-up, but also isolates noise. This approach also increases the area of the layout.
The third method, independent double-well protection, improves the anti-latch-up effect of the layout by respectively placing the PMOS and the NMOS in the N well and the P well, and the anti-latch-up effect of the layout is the best. But this method still increases the area of the layout by increasing the well region.
In order to solve the problems, the invention provides a layout mode of an ESD circuit layout.
Example one
As shown in fig. 2, the ESD1 circuit and the ESD2 circuit are respectively disposed on two sides of the circuit layout, the diode D1 is disposed in a U-shape, the PMOS transistor is disposed in the U-shape of the diode D1, and the first port VCC, the second port VDD, and the third port GND are disposed on one side of the circuit layout.
The diode D1 can be used for ESD protection between the PAD ports VCC and VDD, and effectively isolates NMOS tubes in PMOS and ESD through the diode D1, so that the latch-up resistance effect of the chip can be improved, and the area of a layout is greatly reduced under the condition that a Guard Ring protection Ring and a double-well process are not increased.
Furthermore, the PMOS transistor is arranged at a position far away from the PAD, and the NMOS transistor is arranged at a position close to the PAD. Because the NMOS transistor is used as a drain tube and is close to the PAD port, the on-resistance can be reduced, and a drain path can be provided more quickly and effectively when overvoltage or overcurrent exists.
Further, the PAD port VDD is disposed between GND and VCC.
Further, another modification of the first embodiment may be that the diode D1 may be not only a single diode, but also a parallel/series connection of a plurality of diodes; as shown in particular in figure 3. The diode D1 is a series/parallel connection of a plurality of diodes, wherein the diode D1 is disposed on both sides of the PMOS transistor P1 to separate the PMOS transistor P1 from the NMOS transistors N1 and N2.
Example two
The difference from the first embodiment is that the diode D1 has a T-shaped layout, as shown in fig. 4. The PMOS transistor and the ESD2 circuit are respectively arranged on the upper side and the lower side of the T-shaped diode D1, the ESD1 circuit is arranged on the right side of the circuit layout, and the three PAD ports VCC, VDD and GND are arranged on one side of the circuit layout.
The diode D1 can be used for ESD protection between a PAD port VCC and a VDD, and effectively isolates NMOS tubes in PMOS and ESD through the diode D1, so that the latch-up resistance of a chip can be improved, and the area of a layout is greatly reduced under the condition that a Guard Ring protection Ring and a double-well process are not increased.
Furthermore, the PMOS transistor is arranged at a position far away from the PAD, and the NMOS transistor is arranged at a position close to the PAD. Because the NMOS transistor is used as a drain tube and is close to the PAD port, the on-resistance can be reduced, and a drain path can be provided more quickly and effectively when overvoltage or overcurrent exists.
Further, the PAD port VDD is disposed between GND and VCC.
EXAMPLE III
The difference from the first embodiment is that the PMOS transistor, the diode D1, the ESD circuit, and the input/output port are sequentially arranged as shown in fig. 5.
The invention separates PMOS and NMOS by diode D1, which can effectively improve the anti-latch-up effect of the chip and reduce the area of the chip.
Furthermore, the diode is not only used as a protection tube of the ESD and the PMOS transistor, but also used as a spacer between the PMOS transistor and the NMOS, so that the latch-up resistance is improved, and the area is saved.
Furthermore, the PMOS transistor is arranged at a position far away from the PAD, and the NMOS transistor is arranged at a position close to the PAD. Because the NMOS transistor is used as a drain tube and is close to the PAD port, the on-resistance can be reduced, and a drain path can be provided more quickly and effectively when overvoltage or overcurrent exists.
Furthermore, after the ESD event occurs, the PMOS transistor is in a complete opening state, and the equivalent resistance value of the PMOS transistor is smaller, so that a larger current path can be provided. This is equivalent to discharging the ESD bleeder circuit using both VDD and VCC with the PMOS transistor, increasing the ESD rating.
Furthermore, because the devices related to the ESD circuit are all conventional devices and do not need special process treatment, the latch-up resistance of the ESD circuit can be improved under the condition of not increasing the process difficulty.
The above embodiments are only used for illustrating the present invention, and not for limiting the present invention, and various combinations, modifications, or equivalent substitutions may be made on the technical solution of the present invention, or directly or indirectly applied to other related technical fields, and all of them are included in the scope of the present invention.

Claims (5)

1. An integrated circuit with high ESD level, comprising a first PAD port, a second PAD port, a third PAD port, an ESD1 circuit, an ESD2 circuit, a PMOS transistor P1, and a diode D1, wherein the ESD1 circuit comprises an NMOS transistor N1, the ESD2 circuit comprises an NMOS transistor N2, the ESD1 circuit is connected to the first PAD port and the third PAD port, the ESD2 circuit is connected to the second PAD port and the third PAD port, the PMOS transistor P1 is connected to the first PAD port and the second PAD port, a cathode of the diode D1 is connected to the first PAD port, and an anode of the diode D1 is connected to the second PAD port, the integrated circuit is characterized in that: the diode separates the PMOS transistor from the NMOS transistor.
2. A high ESD rating integrated circuit as claimed in claim 1, wherein: the PAD port VDD is between GND and VCC.
3. A high ESD rating integrated circuit as claimed in claim 2, wherein: the layout of the diode is U-shaped.
4. A high ESD rating integrated circuit as claimed in claim 2, wherein: the layout of the diode is T-shaped.
5. A high ESD rating integrated circuit as claimed in claim 2, wherein: and the PMOS transistor, the diode, the NMOS transistor and the PAD port are sequentially distributed.
CN202110194975.2A 2021-02-22 2021-02-22 Integrated circuit with high ESD grade Pending CN112786586A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110194975.2A CN112786586A (en) 2021-02-22 2021-02-22 Integrated circuit with high ESD grade

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110194975.2A CN112786586A (en) 2021-02-22 2021-02-22 Integrated circuit with high ESD grade

Publications (1)

Publication Number Publication Date
CN112786586A true CN112786586A (en) 2021-05-11

Family

ID=75761635

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110194975.2A Pending CN112786586A (en) 2021-02-22 2021-02-22 Integrated circuit with high ESD grade

Country Status (1)

Country Link
CN (1) CN112786586A (en)

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