CN118093509B - Chip and method for configuring electronic fuse using serial digital interface - Google Patents
Chip and method for configuring electronic fuse using serial digital interface Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
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Abstract
The present disclosure provides a chip and method for configuring an electronic fuse using a serial digital interface; the chip comprises a serial digital interface, a fuse control module and an electronic fuse; the serial digital interface is configured to receive and temporarily store external first control information and data to be programmed; the first control information is used for controlling the state of the fuse control module; the fuse control module includes: a state machine and a data transmission module; the state machine is connected with the first register and is configured to receive the first control information and generate second control information based on the first control information; the data transmission module is connected with the second register and used for sending the data to be programmed to the electronic fuse; and the electronic fuse is connected with the state machine and the data transmission module and is configured to receive the second control information and read or write based on the second control information. Thus, the electronic fuse can be configured by using the serial digital interface, so that the chip pin resources and the chip area can be saved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a chip and method for configuring an electronic fuse using a serial digital interface.
Background
The beam control chip comprises a radio frequency module, and the beam control chip needs to be calibrated and adjusted before use, for example, a phase shifter or a gain amplifier in the radio frequency module is calibrated. To save the calibration data, a one-time programmable memory (One Time Programmable, OTP) including electronic fuses is required in the beam steering chip to cure the calibration data. Generally, the Electronic fuses may include Electronic fuses (EFuse). The electronic fuse burns the calibration data into the electronic fuse by blowing the electronic fuse. In this way, the calibration data solidified in the electronic fuse can calibrate the phase shifter or gain amplifier in the radio frequency module.
The input/output signal wires of the electronic fuse are led to the outside of the chip through the bonding pads for configuration, so that the chip area and the chip pin resources are occupied. In order to save Chip pin resources, the bonding pads of the electronic fuse are shielded during Chip packaging, so that the electronic fuse can only be configured in a wafer test stage (CP) before packaging, and cannot be configured in a final test stage (FINAL TEST, FT) after packaging. However, the configuration of the electronic fuses is for chip calibration, requiring comprehensive testing of the chip. The wafer test stage is not as comprehensive as the final test stage, so if the bonding pads of the electronic fuses are shielded during chip packaging, the calibration effect is affected although the chip pin resources are saved. Therefore, a scheme is needed, which can save chip pin resources and ensure calibration effect.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a chip and a method for configuring an electronic fuse using a serial digital interface, where the electronic fuse is configured using the serial digital interface, so that the pin resources and the chip area of the chip can be saved, and the calibration effect can be ensured.
Embodiments of the present disclosure provide a chip for configuring an electronic fuse using a serial digital interface, comprising: a serial digital interface, a fuse control module, and an electronic fuse; wherein the serial digital interface comprises: a first register and a second register; the first register is configured to receive and temporarily store external first control information; the first control information is used for controlling the state of the fuse control module; the state of the fuse control module includes: a programming state, a reading state or an idle state; the second register is configured to receive and temporarily store external data to be programmed; the fuse control module includes: a state machine; the state machine is connected with the first register and is configured to receive the first control information and generate second control information based on the first control information; the electronic fuse is connected with the state machine and the second register, and is configured to receive the second control information and read or write based on the second control information.
In the above scheme, the chip further comprises: a clock pin; the clock pin is respectively connected with the serial digital interface and the state machine and is used for sending input clock signals to the serial digital interface and the state machine.
In the above scheme, the chip further comprises: the chip selection signal pin is connected with the serial digital interface and is used for sending a chip selection signal to the serial digital interface; and the input data pin is connected with the serial digital interface and is used for sending external data to the serial digital interface, wherein the external data comprises: the first control information and the data to be programmed; the serial digital interface is further configured to process the external data based on the input clock signal and the chip select signal.
In the above scheme, the chip further comprises: a simulation module; the electronic fuse is connected with the analog module and is further configured to output the programming result of the data to be programmed to the analog module and feed back the programming result to the serial digital interface; the serial digital interface further includes: a third register; the third register is connected with the electronic fuse and configured to receive and temporarily store the feedback programming result, and judge whether the electronic fuse is successfully programmed based on the programming result.
In the above solution, the serial digital interface further includes: a fourth register; the fourth register is configured to receive and temporarily store the real-time state of the state machine; the real-time state of the state machine is used for judging whether the state of the state machine is consistent with the state corresponding to the first control information.
In the above scheme, the electronic fuse includes: a plurality of fuse modules; the serial digital interface further includes: a fifth register; the fifth register is configured to receive and temporarily store externally transmitted address information; the address information is used for indicating the position of the fuse module; the state machine is connected with the fifth register and is further configured to read or burn the corresponding fuse module according to the address information.
In the above scheme, the serial digital interface further includes: a data transmission module; the data transmission module is connected with the second register and the electronic fuse and is configured to send the data to be programmed in the second register to the electronic fuse.
In the above scheme, the data transmission module includes: a serial-parallel conversion module; the serial-parallel conversion module is configured to receive the data to be programmed, perform parallel-serial conversion operation on the data to be programmed, and output serial data to be programmed.
In the above solution, the second control information includes: a waveform; the waveform includes: a programming waveform and a reading waveform.
In the above solution, the external data further includes: third control information; the serial digital interface further includes: a sixth register; the sixth register is connected with the simulation module and is configured to receive and temporarily store the third control information and transmit the third control information to the simulation module; the third control information is used for controlling the working state of the simulation module.
The embodiment of the disclosure also provides a method for configuring the electronic fuse by using the serial digital interface, which comprises the following steps: receiving and temporarily storing external first control information; the first control information is used for controlling the state of the fuse control module; the state of the fuse control module includes: a programming state, a reading state or an idle state; receiving and temporarily storing external data to be programmed; generating second control information based on the first control information; wherein the second control information is used for controlling the operation of the electronic fuse; and reading or programming the electronic fuse according to the second control information.
In the above scheme, an input clock signal is received through a clock pin, the first control information is resolved based on the input clock signal, and the second control information is generated based on the input clock signal.
In some embodiments of the present disclosure, a chip includes: a serial digital interface, a fuse control module, and an electronic fuse; the serial digital interface includes: a first register and a second register; the first register is configured to receive and temporarily store external first control information, and the first control information is used for controlling the state of the fuse control module; the second register is configured to receive and temporarily store external data to be programmed; the fuse control module includes: a state machine and a data transmission module; the state machine is connected with the first register and is configured to receive the first control information and generate second control information based on the first control information; the data transmission module is connected with the second register and used for sending the data to be programmed to the electronic fuse; and the electronic fuse is connected with the state machine and the data transmission module, receives the second control information and reads or writes based on the second control information. In this way, the fuse control module is arranged in the chip, the fuse control module generates second control information which can be identified by the electronic fuse based on the first control information in the serial digital interface, and the fuse control module can also transmit the data to be programmed temporarily stored in the serial digital interface to the electronic fuse, so that the configuration of the serial digital interface to the electronic fuse is realized, the electronic fuse does not need to be configured through the outside of the chip, and therefore, the chip does not need to be provided with a pin for configuring the electronic fuse independently, and the chip pin resource and the chip area can be saved. Meanwhile, because the electronic fuse is configured through the serial digital interface, a multiplexing circuit is not required to be arranged so that the serial digital interface and the electronic fuse are multiplexed with pins, the multiplexing circuit is prevented from affecting the speed of the serial data interface, and the data transmission speed is ensured. In addition, because the pins of the serial digital interface are not shielded after the chip is packaged, when the chip is calibrated by adopting the scheme, the electronic fuse can be configured in a final test stage without configuring the electronic fuse in a wafer test stage. The final test stage is more comprehensive in test, a better electronic fuse configuration effect can be achieved, and the chip calibration effect is better.
Drawings
Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a serial digital interface according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of a serial digital interface according to an embodiment of the disclosure;
Fig. 4 is a schematic structural diagram of a fuse control module according to an embodiment of the disclosure;
FIG. 5 is a state jump schematic of a state machine provided by an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a second structure of a chip according to an embodiment of the disclosure;
fig. 7 is a schematic diagram III of a chip according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram of a chip according to an embodiment of the disclosure;
Fig. 9 is a flowchart of a configuration method provided in an embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 is a schematic diagram of an alternative architecture of a chip 100 configured for an electronic fuse provided in an embodiment of the present disclosure, the chip 100 may include a serial digital interface 10, a fuse control module 20, and an electronic fuse 30. The chip 100 may receive external data using the serial digital interface 10 to configure the electronic fuse 30. The serial digital interface 10 is used for transmitting and analyzing external data, and temporarily storing the analyzed external data. The external data may include first control information and data to be programmed. The first control information includes information to control the state of the fuse control module 20. The first control information may be an instruction for controlling the state of the fuse control module 20. The data to be programmed is the data to be programmed into the electronic fuse 30.
In the disclosed embodiment, the serial digital interface 10 includes a first register 110 and a second register 120. The first register 110 is configured to receive and register external first control information, and the second register 120 is configured to receive and register external data to be programmed.
The fuse control module 20 may configure the electronic fuse 30 with the first control information and the data to be programmed. For example, the fuse control module 20 may parse the related data in the first register 110 and the second register 120 to parse the first control information and the data to be programmed required for configuring the electronic fuse 30. The states of the fuse control module 20 include a programming state, a reading state or an idle state, wherein the programming state is a state in which the fuse control module 20 writes the electronic fuse 30, the reading state is a state in which the fuse control module 20 controls reading the electronic fuse 30, and the idle state is a state in which the fuse control module 20 does not work.
The structure of fuse control module 20 includes a state machine 210. In the embodiment of the present disclosure, the state machine 210 is configured to control the electronic fuse 30 to perform different operations based on the first control information, where the operations include programming, reading, and the like. The state machine 210 is connected to the first register 110, and is configured to receive the first control information, and generate second control information based on the first control information, so as to convert the first control information temporarily stored in the first register 110 into a control signal (second control information) that can be recognized by the electronic fuse 30, where the second control information includes information for controlling the state of the electronic fuse 30.
In the embodiment shown in fig. 1, the fuse control module 20 may further include a data transmission module 220 connected to the second register 120 for sending the data to be programmed in the serial digital interface 10 to the electronic fuse 30.
In the disclosed embodiment, the electronic fuse 30 is used to store data that is used to calibrate an analog module (not shown in fig. 1) in the chip 100. In some embodiments, the analog module may be a radio frequency module, and the data may be used to calibrate and debug a phase shifter or a gain amplifier in the radio frequency module, for example, to calibrate the gain of the gain amplifier in the radio frequency module, so as to ensure the consistency of the gain of the chip 100 when leaving the factory. The electronic fuse 30 is configured to receive the second control information and to read or burn based on the second control information. The second control information is a control signal that can be identified by the electronic fuse 30, and the second control information can control the electronic fuse 30 to perform programming or reading, for example, when the second control information controls the electronic fuse 30 to perform programming, the data to be programmed is programmed into the electronic fuse 30.
It can be appreciated that the embodiments of the present disclosure provide the fuse control module 20 in the chip 100, and the fuse control module 20 generates the second control information recognizable by the electronic fuse 30 based on the first control information in the serial digital interface 10. The fuse control module 20 can also control the electronic fuse 30 to be programmed or read according to the data to be programmed temporarily stored in the serial digital interface 10, so as to implement the configuration of the serial digital interface 10 to the electronic fuse 30. That is, the disclosed embodiments utilize pins and registers of the serial digital interface 10 to respectively transfer and store data configuring the electronic fuse 30. In this way, the chip 100 does not have to be provided with pins separately for configuring the electronic fuse 30, thereby enabling chip pin resources and chip area to be saved.
Meanwhile, the pins of the serial digital interface 10 are multiplexed in the configuration electronic fuse 30, and the pins of the serial digital interface 10 are not shielded in the packaging process; in this way, the present disclosure can configure the electronic fuse 30 at the final test stage, and thus, the calibration effect of the chip can be improved. In addition, the multiplexing circuit is not required to be mounted on the pins of the serial digital interface 10, so that the pins of the serial digital interface 10 can be multiplexed in the electronic fuse 30, and the transmission efficiency of the pins of the serial digital interface 10 is prevented from being influenced.
Fig. 2 and 3 are schematic structural views of an alternative serial digital interface 10 according to an embodiment of the present disclosure, where the serial digital interface 10 mainly includes an input interface, an output interface, and an internal structure. The digital interface 10 may further include an input interface including mainly an interface to receive a reset signal RST, a chip select signal CSB, an input clock signal CKI interface 162, an input data signal SDI interface 161, etc., and an output interface including mainly an interface to transmit an output clock signal CKO interface, an output data signal SDO interface 163, and calibration data, as shown in fig. 2. The interface of the calibration data may be used to output the first control information to the fuse control module 20. In the embodiment of the present disclosure, the input data signal SDI interface 161 is connected to the input data Pin pin_2 of the chip 100, and the chip 100 may receive the first control information and the data to be programmed through the input data Pin pin_2; the input clock signal CKI interface 162 is connected to the clock Pin pin_1 of the chip 100, and is configured to receive the input clock signal CKI; the chip select signal CSB interface is connected to a chip select signal pin of the chip 100 for receiving the chip select signal CSB.
As shown in fig. 3, the internal structure of the serial digital interface 10 may include a shift register 171, a decoder 172, and a storage unit 173. The shift register module 171 has a capability of shifting data bit by bit, allowing data to be transferred in units of bits. The input data signal SDI is external data including first control information and data to be programmed, and is transmitted from the upper computer program to the shift register 171 through an input data pin corresponding to the input data signal SDI interface 161, and then the shift register 171 temporarily stores the input data Signal (SDI) for subsequent data processing. The decoder 172 is configured to parse the external data, and in some embodiments, the decoder 172 parses the data in the shift register 171 according to a protocol during temporary storage of the input data Signal (SDI). The Reset Signal (RST), the input clock signal (CKI), and the input chip select signal (CSB) are transmitted into the serial data interface 10 through corresponding pins, and commonly control the data decoding process of the decoder 172. The decoder 172 correspondingly stores the decoded data into the corresponding register of the storage unit 173 according to the parsing content, where the decoded data includes the first control information and the data to be programmed. The storage unit 173 is used for storing data, and the storage unit 173 may include a plurality of registers each having one address. The first register 110 and the second register 120 in fig. 1 may each be a register in the storage unit 173. For example, the registers in the memory unit 173 may be D Flip-flops (D Flip-Flop).
In the disclosed embodiment, referring to fig. 3, the serial digital interface 10 is further configured to receive third control information, which is transmitted to the analog module 40 and not transmitted to the electronic fuse 30. The third control information includes information for adjusting the operation state of the analog module 40, and is used for adjusting the analog module 40 when the chip 100 operates after the product leaves the factory. The working state of the analog module 40 refers to a state that can be adjusted when working after leaving the factory, and the analog module 40 processes different signals in different working states. For example, the analog module 40 may be a radio frequency module, and the phase shifter or the gain amplifier in the analog module 40 may be adjusted based on the third control information, so as to adjust the phase and the amplitude of the radio frequency signal for beam forming control. At this time, the different working states indicate that the radio frequency module adjusts the phase of the radio frequency signal differently, or that the radio frequency module adjusts the amplitude of the radio frequency signal differently. The serial digital interface 10 may receive the third control information through an interface transmitting an input data Signal (SDI) and directly transmit the parsed third control information to the analog module 40. In this way, the serial digital interface 10 not only can calibrate the analog module 40 by configuring the electronic fuse 30 before the chip leaves the factory, but also can adjust the analog module 40 after the chip leaves the factory, thereby realizing the function multiplexing of the serial digital interface 10 and saving hardware resources.
In the embodiment of the present disclosure, the third control information is also external data. The shift register 171 temporarily stores the third control information, the decoder 172 analyzes the external data, and the decoded data is stored in the sixth register 170 in the storage unit 173 according to the analysis content. The sixth register 170 is coupled to the analog block 40 and the decoded data includes third control information. The storage unit 173 transmits the third control information in the sixth register 170 to the analog module 40.
Fig. 4 is a schematic diagram of an alternative fuse control module 20 according to an embodiment of the present disclosure, where the state machine 210 in the fuse control module 20 may be a mole (Moore) state machine or a miller (Mealy) state machine. The first control information received by the state machine 210 may be a state control code, which may conveniently control the state of the state machine 210, or may conveniently be transmitted through the serial digital interface 10. The state control code may be encoded in a time sequence encoding (Sequential), gray encoding (Gray), and One hot (One hot) manner. For example, when the state control code is coded using time-series coding, the code corresponding to the idle state is "11" and the code corresponding to the reset state is "01", and the code corresponding to the read state is "10". The state machine 210 may perform state skipping based on the received first control information, and generate second control information in a state corresponding to the first control information. The first control information and the second control information have a corresponding relationship, and the state machine 210 may generate the corresponding second control information according to the first control information. For example, state machine 210 may be implemented by a flip-flop, which may include two inputs. For example, the Flip-Flop may be a JK Flip-Flop (JK Flip-Flop) or an SR Flip-Flop (SR Flip-Flop). The two inputs of the flip-flop may receive the state control code and the input clock signal, respectively, and implement state transitions based on the control of the state control code and the input clock signal. For example, if the state corresponding to the first control information is "01", the state machine 210 is in the writing state, and generates the waveform of the corresponding second control information.
In the embodiment of the present disclosure, the second control information may be a waveform, which may conveniently control the electronic fuse 30. The waveforms may be a programming waveform and a reading waveform to control the electronic fuse 30 to perform programming or reading. It should be noted that, configuring the electronic fuses requires transmitting a desired waveform to the electronic fuses in the electronic fuses. The morphology and amplitude of the desired waveform of the electronic fuse may be affected by the design parameters and operating conditions of the electronic fuse. In the present embodiment, the state machine 210 of the fuse control module 20 is used to generate the required waveforms without providing waveforms for configuring the electronic fuses by an external host computer program, that is: the embodiment of the disclosure does not need to set pins of the upper computer program configuration waveform.
In the embodiment of the disclosure, the state machine 210 may perform state skipping based on the received state control code, and generate a waveform in a state corresponding to the state control code. For example, in the case where the state corresponding to the state control code received by the state machine 210 is the writing state, the state machine 210 jumps to the writing state, and then the state machine 210 generates a corresponding writing waveform under the control of the input clock signal, where the data stream corresponding to the data to be written may be combined with the writing waveform, for example, the data stream corresponding to the data to be written may be located after the writing waveform. That is, the state machine 210 is capable of generating a waveform recognizable by the electronic fuse 30 based on the state control code. As such, the chip 100 of the present disclosure may internally generate waveforms required to configure the electronic fuse 30 using the state machine 210.
Fig. 5 is a State transition diagram of an alternative State machine provided by an embodiment of the present disclosure, where the State machine 210 in fig. 5 may have 4 states (states): idle state, read state, burn-in state, and reset state. The state machine 210 may be different depending on the manufacturer of the electronic fuse 30, and is not limited to only 4 states, which is not limiting here. The state machine 210 may include a plurality of output interfaces, each outputting a corresponding one of the waveforms. For example, the state machine 210 may include multiple output interfaces that may be used to deliver different waveforms, such as a burn waveform and a read waveform, respectively.
It should be noted that, the working principle of the state machine is as follows: based on the triggering of the Event (Event), the Action (Action) corresponding to the Event is executed after the Event occurs. An event is a trigger condition or password to perform some action. For example, the state machine 210 receives the state control code "01" and the input clock signal as one event, and after the state machine 210 receives the state control code "01" and the input clock signal, the action of generating the programming waveform is performed. In the embodiment of the present disclosure, the upper computer program may write the corresponding state control code to the first register 110 in the serial digital interface 10. Taking four states included in the state machine 210 in fig. 5 as an example, a state jump of the state machine 210 is described: the state machine 210 defaults to an idle state and other states may jump to an idle state. The host program may control the state machine 210 to make a state jump by writing a state control code to the first register 110 in the serial digital interface 10. In the case where the state machine 210 is in any one of the states, the state machine 210 generates waveforms required for the functions of the electronic fuse 30 corresponding to that state. For example, if the state machine 210 is in a burn state based on the input clock signal and the triggering of the state status code, the state machine 210 generates a burn waveform and sends the burn waveform to the electronic fuse 30. If the state machine 210 is stuck in a certain state, the upper computer program can send a reset instruction to reset through the serial digital interface 10. After the state machine 210 receives the reset instruction, the state machine 210 resets and then jumps to the idle state. After the state machine 210 finishes the writing operation or the reading operation, the state machine 210 automatically returns to the idle state and resets. For example, after the corresponding writing waveform or reading waveform is sent, the state machine 210 may jump to the idle state with the number of times counted by the clock reaching the preset number as a trigger condition.
In the embodiment of the present disclosure, referring to fig. 1 and 4, the data transmission module 220 is connected to the second register 120 and is used for sending the data to be programmed to the electronic fuse 30. For example, when the state machine 210 enters the writing state, the data transmission module 220 may transmit the data to be written in the second register 120 to the electronic fuse 30 through the output interface of the state machine 210, and temporarily store the data to be written in the register of the electronic fuse 30; then, after the electronic fuse 30 receives the writing waveform, the data to be written is written into the electronic fuse 30.
In the disclosed embodiment, referring to fig. 1, the electronic fuse 30, the connection state machine 210 and the data transmission module 220 are configured to receive the second control information and read or write based on the second control information. For example, if the second control information received by the electronic fuse 30 is a programming waveform, the corresponding electronic fuse in the electronic fuse 30 is programmed according to the programming waveform, so that the data to be programmed is solidified. The second control information received by the electronic fuse 30 is a read waveform, the solidified data in the electronic fuse 30 is read according to the read waveform, the read data is temporarily stored in the shift register 171, and then the read data is transmitted to the upper computer program through the pin 163. That is, the chip 100 may internally generate waveforms required to configure the electronic fuse 30 using the state machine 210.
In some embodiments of the present disclosure, referring to fig. 1, the chip 100 further includes: clock Pin pin_1. The clock Pin pin_1 is connected to the serial digital interface 10 and the state machine 210, respectively, and is used for transmitting an input clock signal to the serial digital interface 10 and transmitting the input clock signal to the state machine 210. For example, as shown in fig. 2, the input clock signal common to the serial digital interface 10 and the state machine 210 may be an input clock signal (CKI) received by the serial digital interface 10.
In the embodiment of the present disclosure, in conjunction with fig. 1 and 2, the clock Pin pin_1 connects the serial digital interface 10 and the state machine 210, respectively, and simultaneously transmits an input clock signal to the serial digital interface 10 and the state machine 210. The serial digital interface 10 controls the process of data decoding by inputting a clock signal. The state machine 210 controls the process of state transitions by inputting a clock signal. The serial digital interface 10 may convey the received input clock signal (CKI) to the state machine 210. That is, the state machine 210 multiplexes the input clock signals (CKI) of the serial digital interface 10, and can simultaneously control the operation of the serial digital interface 10 and the state machine 210 using one input clock signal, thereby saving resources. In this embodiment, the Reset Signal (RST), the input clock signal (CKI) and the input chip select signal (CSB) together control the serial digital interface 10 to parse external data, and the serial digital interface 10 can be fault tolerant, so that multiplexing the input clock signal (CKI) by the state machine 210 does not affect the serial digital interface 10.
It should be noted that, the state machine 210 generates a writing waveform or a reading waveform, and needs to receive an input clock signal, and the state corresponding to the state control code received by the state machine 210 is a writing state or a reading state. However, when the electronic fuse 30 is not configured, the state corresponding to the state control code received by the state machine 210 is the idle state, and at this time, the state machine 210 is in the idle state, and the state machine 210 receives the input clock signal and does not generate the programming waveform or the reading waveform. Therefore, the receiving of the input clock signal (CKI) by the fuse control module 20 will not affect the normal operation of the fuse control module 20, and will not affect the data to be programmed solidified by the electronic fuse 30. That is, multiplexing the input clock signal (CKI) by the state machine 210 does not affect the data to be programmed solidified by the electronic fuse 30.
It will be appreciated that the state machine 210 in the disclosed embodiment multiplexes the input clock signals of the serial digital interface 10. In this way, the chip 100 does not have to be provided with a clock pin separately for configuring the electronic fuse 30, thereby enabling further savings in chip pin resources and chip area.
Fig. 6 is a schematic diagram of another alternative chip provided in the embodiment of the disclosure, and it should be noted that the third register 130 may be a register in the memory unit 173 in fig. 3.
In some embodiments of the present disclosure, referring to fig. 6, the serial digital interface 10 further includes: a third register 130. The electronic fuse 30 is configured to write the data to be written based on the second control information, and output the result of the writing to an analog circuit such as the analog module 40 for calibration. The electronic fuse 30 may also feed back the programming result to the serial digital interface 10. For example, in the process of transferring the cured data to be written to the analog module 40, the chip 100 may copy the result of writing (which may be understood as the cured data to be written) out of the third register 130 in the serial digital interface 10 and return the result to the third register. The third register 130 is connected to the electronic fuse 30, and is configured to receive and temporarily store the programming result, and is used for determining whether the programming of the electronic fuse 30 is successful. For example, the chip 100 may output the programming result generated in configuring the electronic fuse 30 to the host program through the pin corresponding to the output data signal SDO interface 163. Therefore, the upper computer program can judge whether the electronic fuse 30 is successfully programmed by comparing the programming result with the data to be programmed.
Fig. 7 is a schematic structural diagram of another alternative chip provided in an embodiment of the disclosure. In some embodiments of the present disclosure, referring to fig. 7, the serial digital interface 10 further includes a fourth register 140. The fourth register 140 is configured to receive and register the real-time state of the state machine 210. It should be noted that, the fourth register 140 may be a register in the storage unit 173 in fig. 3; the real-time state of the state machine 210 is used for judging whether the state of the state machine 210 is consistent with the state corresponding to the first control information.
In the embodiment of the present disclosure, in conjunction with fig. 4 and 7, the fuse control module 20 further includes a status register 230, where the status register 230 is used to store the real-time status of the state machine 210. The fourth register 140 may be coupled to the status register 230 to receive and register the real-time status of the state machine 210. In this way, the serial digital interface 10 can determine whether the state machine 210 is operating normally by comparing whether the real-time state of the state machine 210 is consistent with the state corresponding to the state control code.
Fig. 8 is a schematic diagram of an alternative chip provided by an embodiment of the present disclosure, where the electronic fuse 30 may include one or more fuse modules. For example, the electronic fuse 30 includes a fuse module 310a, a fuse module 310b, and a fuse module 310c. One or more electronic fuses may be included in each fuse module, for example, one or more electronic fuses may be included in fuse module 310 a. Each fuse block may correspond to a logic value, one for characterizing the data of one data bit stored.
In some embodiments of the present disclosure, referring to fig. 8, the host computer program may utilize the data after curing of the electronic fuse 30 to verify the rf module. If an error occurs in the configuration process of the electronic fuse 30, the accuracy of the verification of the radio frequency module is affected. In addition, since the electronic fuse 30 cannot be repeatedly arranged, the chip 100 becomes a waste chip, and the chip yield is reduced.
To improve the yield of the chip 100, redundant electronic fuses may be provided in the electronic fuse 30 of embodiments of the present disclosure. The electronic fuse 30 includes a plurality of fuse modules. For example, the electronic fuse 30 includes a fuse module 310a, a fuse module 310b, and a fuse module 310c. The upper computer program may configure the fuse modules 310a, 310b, and 310c one by one, or may simultaneously configure the fuse modules 310a, 310b, and 310c. The fuse block 310a, the fuse block 310b, and the fuse block 310c may be configured with the same data, and may also be connected to the same logic operation block (not shown in the figure). In this way, the logic operation module performs a logic operation on the plurality of logic values output from the fuse modules 310a, 310b and 310c, and takes the logic operation results of the fuse modules 310a, 310b and 310c as the final logic value of the electronic fuse 30.
The serial digital interface 10 further includes: and a fifth register 150. The fifth register 150 is configured to receive and temporarily store externally transmitted address information. The address information may be transferred to the fifth register 150 through an input data pin corresponding to the input data signal SDI interface 161. The address information is used to indicate the location of the fuse module, or address information is used to indicate which fuse module, e.g., the address information is indicated as fuse module 310a. The state machine 210 is connected to the fifth register 150, and the state machine 210 is further configured to read or write the corresponding fuse module according to the address information. For example, if the address information indicates the fuse module 310a, the state machine 210 writes the fuse module 310a according to the address information.
It is understood that the electronic fuse 30 in the embodiments of the present disclosure includes a plurality of fuse modules 310. In this way, in the case that a part of the electronic fuses in the electronic fuse 30 fail, it can be further ensured that the data stored in the electronic fuse 30 meets the target, the probability of the electronic fuse 30 failing is reduced, and the yield of the electronic fuse 30 and the chip 100 is improved.
In some embodiments of the present disclosure, referring to fig. 8, the data transmission module 220 is a serial-parallel conversion module. The serial-parallel conversion module is configured to receive data to be programmed, perform serial-parallel operation on the data to be programmed, and output serial data to be programmed.
In an embodiment of the present disclosure, referring to fig. 8, the fuse control module 20 may include a data transmission module 220. The data transmission module 220 may be a serial-parallel conversion module. The data to be programmed by the electronic fuse 30 is input in series, but the data to be programmed temporarily stored in the serial digital interface 10 is transferred to the fuse control module 20 in parallel, so that the parallel-transferred data to be programmed needs to be converted into a serial signal by the serial-parallel conversion module.
Fig. 9 is a schematic flowchart of an alternative configuration method provided in an embodiment of the present disclosure, which will be described in conjunction with the steps shown in fig. 9, and may be used to operate the chip 100 described above, and may be executed by an upper computer program.
S101, receiving and temporarily storing first control information; the first control information is used for controlling the state of the fuse control module; the states of the fuse control module include a programming state, a reading state, or an idle state.
S102, receiving and temporarily storing data to be programmed.
S103, generating second control information based on the first control information; wherein when the second control information is used to control operation of the electronic fuse.
And S104, reading or programming the electronic fuse based on the second control information.
In the embodiment of the present disclosure, referring to fig. 8, before the chip 100 leaves the factory, the host program may configure the electronic fuse 30 through the serial data interface 10 and the fuse control module 20, that is: the calibration data is solidified into the electronic fuse 30. The electronic fuse 30 may then send calibration data to the analog module 40 to calibrate the analog module 40.
Specifically, the host program may write the first control information (e.g., the status control code) into the first register 110 and write the data to be programmed (e.g., the calibration data) into the second register 120 by writing the data into the serial digital interface 10. At this time, the code of the state control code is "01", and the state corresponding to the state control code is the writing state.
Then, the state machine 210 in the fuse control module 20 enters a programming state based on the state control code and the trigger of the input clock signal, and generates a corresponding programming waveform. And sends the programming waveform to the electronic fuse 30. In the process of generating and sending the programming waveform by the state machine 210, the data transmission module 220 may simultaneously transmit the data to be programmed (for example, calibration data) to the electronic fuse 30 through the output interface of the state machine 210.
Finally, the electronic fuse 30 burns the corresponding electronic fuse based on the received burning waveform and the data to be burned (for example, calibration data), and completes the solidification of the data to be burned (for example, calibration data). And, the electronic fuse 30 will send the data to be programmed after curing to the analog module 40.
In addition, in the process of transferring the cured data to be programmed to the analog module 40, the chip 100 may copy the result of programming (which may be understood as the cured data to be programmed) out of a path and return the result to the third register 130 in the serial digital interface 10. The third register 130 is connected to the electronic fuse 30 to receive and temporarily store the writing result. Then, the third register 130 outputs the programming result to the upper computer program through the pin corresponding to the output data signal SDO interface 163. The upper computer program can judge whether the electronic fuse 30 is successfully programmed by comparing the programming result with the data to be programmed.
In some embodiments of the present disclosure, S103 in fig. 9 may be further implemented through S201, and will be described in connection with the steps.
S201, receiving an input clock signal through a clock pin, analyzing first control information based on the input clock signal, and generating second control information based on the input clock signal.
In the disclosed embodiment, referring to fig. 1, in the process of transmitting external data through the serial digital interface 10, an input clock signal functions to synchronize the transmission of the data. The serial digital interface 10 receives an input clock signal through a clock pin and parses the first control information based on the input clock signal. For example, the input clock signal determines the time interval and rate of data transfer, and the serial digital interface 10 may sample and parse external data according to the edges (rising or falling edges) of the input clock signal, ensuring that the external data is transferred accurately and completely. The serial digital interface 10 receives an input clock signal through the clock Pin pin_1, determines a clock cycle corresponding to the first control information based on the input clock signal, and parses the first control information and stores the first control information in the first register 110 in the corresponding clock cycle. The parsing and storing process of the data to be programmed can be understood by referring to the first control information, which is not described herein.
In the disclosed embodiment, referring to fig. 1, the function of the state machine 210 in the fuse control module 20 to receive an input clock signal is to synchronize and control state transitions of the state machine 210. The input clock signal provides a uniform time reference such that the state machine 210 performs operations in a predetermined order within each clock cycle. For example, by inputting a clock signal, the state machine 210 may update the internal state and generate waveforms, etc., every clock cycle. The state machine 210 may generate the second control information based on the input clock signal. For example, when the state corresponding to the state control code is the programming state, the state machine 210 enters the programming state based on the input clock signal and the trigger of the state control code, and generates the programming waveform under the control of the input clock signal.
The present disclosure also provides a computer-readable storage medium having stored thereon a computer program or instructions that, when executed, cause a computer to perform a configuration method as in the above-described embodiments. In addition, the configuration method in the embodiment may be executed by an external control module, and the external control module may be an upper computer program.
Note that the computer readable storage medium may be a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable programmable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable programmable Read Only Memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-Only Memory, EEPROM), a magnetic random access Memory (Ferromagnetic Random Access Memory, FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc-Read Only Memory (CD-ROM), or the like; but may be various electronic devices such as mobile phones, computers, tablet devices, personal digital assistants, etc., that include one or any combination of the above-mentioned memories.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.
Claims (11)
1. A chip for configuring an electronic fuse using a serial digital interface, comprising: the device comprises a serial digital interface, a fuse control module, an electronic fuse and an analog module; wherein,
The serial digital interface includes: a first register, a second register, and a sixth register;
the first register is configured to receive and temporarily store external first control information; the first control information is used for controlling the state of the fuse control module; the state of the fuse control module includes: a programming state, a reading state or an idle state;
the second register is configured to receive and temporarily store external data to be programmed;
The fuse control module comprises a state machine, is connected with the first register, and is configured to receive the first control information and generate second control information based on the first control information;
The electronic fuse is connected with the state machine, the second register and the simulation module, and is configured to receive the second control information, read or write based on the second control information and output the writing result of the data to be written to the simulation module;
The sixth register is connected with the simulation module and is configured to receive and temporarily store external third control information and transmit the third control information to the simulation module; the third control information is used for controlling the working state of the simulation module.
2. The chip of claim 1, further comprising: a clock pin;
The clock pin is respectively connected with the serial digital interface and the state machine and is used for sending input clock signals to the serial digital interface and the state machine.
3. The chip of claim 2, further comprising:
the chip selection signal pin is connected with the serial digital interface and is used for sending a chip selection signal to the serial digital interface;
And the input data pin is connected with the serial digital interface and is used for sending external data to the serial digital interface, wherein the external data comprises: the first control information and the data to be programmed;
The serial digital interface is further configured to process the external data based on the input clock signal and the chip select signal.
4. The chip of claim 3, wherein the serial digital interface further comprises: a third register;
the electronic fuse is further configured to feed back the programming result to the serial digital interface;
The third register is connected with the electronic fuse and configured to receive and temporarily store the feedback programming result, and judge whether the electronic fuse is successfully programmed based on the programming result.
5. The chip of claim 1, wherein the serial digital interface further comprises: a fourth register;
The fourth register is configured to receive and temporarily store the real-time state of the state machine;
the real-time state of the state machine is used for judging whether the state of the state machine is consistent with the state corresponding to the first control information.
6. The chip of claim 1, wherein the electronic fuse comprises: a plurality of fuse modules; the serial digital interface further includes: a fifth register;
The fifth register is configured to receive and temporarily store externally transmitted address information; the address information is used for indicating the position of the fuse module;
The state machine is connected with the fifth register and is further configured to read or burn the corresponding fuse module according to the address information.
7. The chip of claim 1, wherein the fuse control module further comprises: a data transmission module;
the data transmission module is connected with the second register and the electronic fuse and is configured to send the data to be programmed in the second register to the electronic fuse.
8. The chip of claim 7, wherein the data transmission module comprises: a serial-parallel conversion module;
The serial-parallel conversion module is configured to receive the data to be programmed, perform parallel-serial conversion operation on the data to be programmed, and output serial data to be programmed.
9. The chip of claim 1, wherein the second control information comprises: a waveform; the waveform includes: a programming waveform and a reading waveform.
10. A method of configuring an electronic fuse using a serial digital interface, comprising:
Receiving and temporarily storing external first control information; the first control information is used for controlling the state of the fuse control module; the state of the fuse control module includes: a programming state, a reading state or an idle state;
Receiving and temporarily storing external data to be programmed;
Generating second control information based on the first control information; wherein the second control information is used for controlling the operation of the electronic fuse;
Reading or programming the electronic fuse based on the second control information;
outputting the programming result of the data to be programmed to an analog module;
Receiving and temporarily storing external third control information, and transmitting the third control information to the simulation module; the third control information is used for controlling the working state of the simulation module.
11. The method of claim 10, wherein an input clock signal is received via a clock pin, wherein the first control information is parsed based on the input clock signal, and wherein the second control information is generated based on the input clock signal.
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| US6342807B1 (en) * | 2000-06-26 | 2002-01-29 | Microchip Technology Incorporated | Digital trimming of analog components using non-volatile memory |
| CN112650701B (en) * | 2020-12-16 | 2021-10-26 | 中国电子科技集团公司第五十八研究所 | Simplified serial transmission circuit |
| CN114385546A (en) * | 2021-12-10 | 2022-04-22 | 厦门码灵半导体技术有限公司 | Chip comprising eFuse module, electronic device and chip burning control method |
| CN114372432B (en) * | 2021-12-17 | 2023-01-13 | 贵州振华风光半导体股份有限公司 | Digital fuse trimming system and method based on SPI serial interface |
| CN116431161A (en) * | 2023-02-17 | 2023-07-14 | 中国电子科技集团公司第五十八研究所 | Disposable fuse trimming circuit based on SPI communication protocol |
| CN117219146A (en) * | 2023-09-15 | 2023-12-12 | 山东云海国创云计算装备产业创新中心有限公司 | Safety start-oriented on-chip efuse read-write control device and method |
| CN117558328B (en) * | 2024-01-11 | 2024-04-19 | 上海安其威微电子科技有限公司 | Electronic fuse, control method, and computer-readable storage medium |
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| CN102163180A (en) * | 2011-01-20 | 2011-08-24 | 电子科技大学 | I2C bus interface circuit module and control method thereof |
| CN112416824A (en) * | 2020-12-03 | 2021-02-26 | 上海集成电路研发中心有限公司 | Efuse read-write controller, chip, electronic equipment and control method |
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