CN118092582A

CN118092582A - Apparatus and method for multi-chip clock synchronization

Info

Publication number: CN118092582A
Application number: CN202311581776.2A
Authority: CN
Inventors: 李宰焕; 金润会; 金志慧; 丁承讚; 郑贤洙
Original assignee: LX Semicon Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2022-11-25
Filing date: 2023-11-23
Publication date: 2024-05-28

Abstract

The present disclosure relates to an apparatus and method for multi-chip clock synchronization. The present disclosure relates to a multi-chip clock synchronization apparatus and method capable of reducing an operation frequency and power consumption when a plurality of chips share a clock for multi-chip clock synchronization, and the multi-chip clock synchronization apparatus may include: a reference clock supply unit connected to the plurality of chips and supplying a reference clock of a first frequency to each chip; and a target clock generating unit generating a target clock of a second frequency based on the reference clock of the first frequency, wherein the reference clock supplying unit may generate the reference clock of the first frequency lower than the second frequency of the target clock by N times to supply the generated reference clock to the respective chips, and the target clock generating unit may multiply the first frequency of the reference clock by N times to generate the target clock of the second frequency when the reference clock of the first frequency is input.

Description

Apparatus and method for multi-chip clock synchronization

Technical Field

The present disclosure relates to a multi-chip clock synchronization apparatus and method capable of reducing an operating frequency and power consumption when a plurality of chips share a clock for multi-chip clock synchronization.

Background

In general, a display panel may be composed of a plurality of pixels arranged in a matrix form, each pixel may be composed of sub-pixels such as R (red), G (green), and B (blue), and each sub-pixel may display an image on the display panel while emitting light in a gray scale corresponding to image data.

Recently, display panels are becoming larger, and as the display panels are becoming larger, the number of driving chips in the display panels is also increasing to support high resolution and high frame rate.

Therefore, in the case of devices using a plurality of chips (e.g., a display panel and a touch panel), clock signal generation and clock signal synchronization between chips among the plurality of chips are becoming important issues for increasing the operation speed.

As a clock sharing method for clock signal synchronization, a method of supplying the same clock to chips among a plurality of chips when an external oscillator generates a clock so that the plurality of chips share a clock source has been used in the related art.

However, this method in the prior art has problems: since an external oscillation element is used, it is disadvantageous in terms of cost, and since a plurality of chips share an oscillation frequency, an input/output operation frequency and power consumption increase.

In addition, as another clock sharing method for clock signal synchronization, a method of supplying the same clock to a plurality of slave chips when an oscillator inside a master chip generates the clock so that the plurality of slave chips share a clock source has been used in the related art.

However, this approach also has problems: since the slave chips share the oscillation frequency, the input/output operation frequency and power consumption increase.

Therefore, it is necessary to develop a multi-chip clock synchronization apparatus capable of reducing input/output operation frequency and power consumption in the future.

Disclosure of Invention

Technical problem

The present disclosure is directed to solving the above problems and other problems.

The present disclosure is directed to providing a multi-chip clock synchronization apparatus and method capable of reducing an input/output operation frequency and power consumption when performing clock synchronization by individually supplying a low-frequency reference clock to each of a plurality of chips and multiplying the low frequency of the reference clock in each chip by N times to generate and share a target clock.

Technical proposal

A multi-chip clock synchronization apparatus according to an embodiment of the present disclosure may include: a reference clock supply unit connected to the plurality of chips and supplying a reference clock of a first frequency to each chip; and a target clock generating unit that generates a target clock of a second frequency based on the reference clock of the first frequency, wherein the reference clock supplying unit may generate the reference clock of the first frequency lower than the second frequency of the target clock by N times to supply the generated reference clock to the respective chips, and the target clock generating unit may multiply the first frequency of the reference clock by N times to generate the target clock of the second frequency when the reference clock of the first frequency is input.

The multi-chip clock synchronization method according to an embodiment of the present disclosure is a multi-chip clock synchronization method of an apparatus including a reference clock supply unit and a target clock generation unit, and may include: generating, by the reference clock supply unit, a reference clock of a first frequency that is N times lower than a second frequency of the target clock; supplying, by a reference clock supply unit, a reference clock of a first frequency to each of a plurality of chips; generating, by the target clock generating unit, a target clock of a second frequency by multiplying a low frequency of the reference clock in each chip by N times when the reference clock of the first frequency is input to each chip; and synchronizing clocks of the plurality of chips based on the target clock of the second frequency by the target clock generating unit.

The display device according to an embodiment of the present disclosure may include: a touch panel in which a plurality of touch sensors are provided; a touch driving device that drives the touch sensor; and a multi-chip clock synchronization device applying a target clock to the plurality of chips of the touch driving device to synchronize clocks of the plurality of chips, wherein the multi-chip clock synchronization device may include a reference clock supply unit connected to the plurality of chips and supplying a reference clock of a first frequency to the respective chips, and a target clock generation unit generating a target clock of a second frequency based on the reference clock of the first frequency input to the respective chips, the reference clock supply unit may generate a reference clock of a first frequency lower than the second frequency of the target clock by N times to supply the generated reference clock to the respective chips, and the target clock generation unit may multiply the first frequency of the reference clock by N times to generate the target clock of the second frequency when the reference clock of the first frequency is input.

Advantageous effects

According to embodiments of the present disclosure, a multi-chip clock synchronization apparatus may reduce input/output operation frequency and power consumption when performing clock synchronization by individually supplying a low-frequency reference clock to each of a plurality of chips and multiplying the low frequency of the reference clock in each chip by N times to generate and share a target clock.

Drawings

Fig. 1 to 3 are diagrams for schematically describing a multi-chip clock synchronization apparatus according to the present disclosure;

Fig. 4 is a diagram for describing a multi-chip clock synchronization apparatus according to a first embodiment of the present disclosure;

fig. 5 is a diagram for describing the target clock generation unit in fig. 4;

fig. 6 is a diagram for describing a multi-chip clock synchronization apparatus according to a second embodiment of the present disclosure;

fig. 7 is a diagram for describing the target clock generation unit in fig. 6;

fig. 8 is a diagram for describing a multi-chip clock synchronization apparatus according to a third embodiment of the present disclosure;

Fig. 9 and 10 are diagrams for describing a display device including a multi-chip clock synchronization device according to the present disclosure; and

Fig. 11 to 13 are flowcharts for describing a multi-chip clock synchronization method according to the present disclosure.

Detailed Description

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are denoted by the same reference numerals regardless of the drawing numbers, and repetitive description thereof will be omitted. The component suffixes "module" and "portion" used in the following description are given or mixed together only in consideration of ease of authoring the present specification, and do not themselves have meanings or roles distinguished from each other. In addition, in describing the embodiments disclosed in the present specification, when it is determined that detailed descriptions of related well-known techniques unnecessarily obscure the gist of the embodiments disclosed in the present specification, the detailed descriptions thereof will be omitted. Furthermore, the drawings are only for the convenience of understanding the embodiments disclosed in the present specification, and the technical scope disclosed in the present specification is not limited by the drawings, but should be construed to include all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure.

Terms including ordinal numbers such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. The term is used merely to distinguish one component from another.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element but intervening elements may be present therebetween. In contrast, it will be understood that when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no other intervening components present.

Fig. 1 to 3 are diagrams for schematically describing a multi-chip clock synchronization apparatus according to the present disclosure.

The multi-chip clock synchronization apparatus of the present disclosure is an apparatus for synchronizing clocks of all chips in an apparatus using a plurality of chips, and is applicable to various apparatuses using a plurality of chips.

As shown in fig. 1 to 3, the multi-chip clock synchronization apparatus of the present disclosure may include a reference clock supply unit 100 connected to a plurality of chips and supplying a reference clock of a first frequency to each chip, and a target clock generation unit 200 generating a target clock of a second frequency based on the reference clock of the first frequency input to each chip.

Here, the reference clock supply unit 100 may generate a reference clock of a first frequency N times lower than a second frequency of the target clock to supply the generated reference clock to the respective chips, and the target clock generation unit 200 may generate the target clock of the second frequency when multiplying the first frequency of the reference clock by N times when the reference clock of the first frequency is input.

As one embodiment, as shown in fig. 2, the reference clock supply unit 100 may generate a reference clock outside the plurality of chips 300 to equally supply the reference clock of the first frequency to the plurality of chips 300, and the target clock generation unit 200 may be separately provided inside the respective chips 310 to generate the target clock of the second frequency for the respective chips 310.

Next, the reference clock supply unit 100 may include an oscillation element.

For example, the oscillating element may include an RC oscillator, an LC oscillator, and a crystal oscillator.

In addition, as shown in fig. 2, the target clock generation unit 200 may be provided in the same number as the number of the plurality of chips, and may be provided inside the respective chips 310 to correspond one-to-one to the respective chips 310.

In addition, the target clock generation unit 200 may include: a phase frequency detector that detects a phase difference between a reference clock and a multiplied-by-N clock when the reference clock of the first frequency and the multiplied-by-N clock are input; a voltage controlled oscillator that controls a phase of the multiplied N-times clock based on the phase difference detected by the phase frequency detector to output a target clock of a second frequency; and a clock multiplier that multiplies the frequency of the clock whose phase is controlled by the voltage-controlled oscillator by N times to feed back the multiplied clock to the phase frequency detector by N times.

Here, the target clock generating unit 200 may further include a filter unit electrically connected between the phase frequency detector and the voltage controlled oscillator to remove noise from the clock signal.

In addition, the plurality of target clock generating units 200 may be provided to correspond to each of the plurality of chips, and the plurality of target clock generating units 200 may multiply the frequency of the target clock by the same multiple to generate the same target clock of the second frequency.

Further, as another embodiment, as shown in fig. 3, the reference clock supply unit 100 may generate a reference clock of a first frequency from a master chip among a plurality of chips 300 including one master chip and a plurality of slave chips, and equally supply the reference clock of the first frequency to the plurality of slave chips through clock output terminals of the master chip, and the target clock generation unit 200 may be separately provided inside the master chip and the slave chips to generate a target clock of a second frequency for each chip 310.

Here, the reference clock supply unit 100 may include a vibrator, a vibrator driver driving the vibrator to output a vibration frequency, and a clock distribution part dividing the vibration frequency based on a preset division ratio to generate a reference clock of a first frequency.

In this case, one end of the vibrator may be connected to an input terminal of the main chip, and the other end is connected to an output terminal of the main chip.

As an example, the vibrator may include a crystal oscillator.

In addition, the reference clock supply unit 100 may be separately provided inside the master chip and the slave chips, the reference clock supply unit 100 provided inside the master chip may be turned on to be enabled to generate the reference clock, and the reference clock supply unit 100 provided inside each of the plurality of slave chips may be turned off to be disabled to not generate the reference clock.

Here, the reference clock supply unit 100 of the master chip may transmit the reference clock to the clock input terminal of each slave chip through the clock output terminal of the master chip, and the reference clock input to the slave chip may be input to the target clock generation unit 200 provided inside the slave chip.

In some cases, the reference clock supply unit 100 may be separately provided inside the master chip and the slave chips, the reference clock supply unit 100 provided inside the master chip may be turned on to be enabled to generate the reference clock, and the reference clock supply unit 100 provided inside each of the plurality of slave chips may be turned off and may buffer the reference clock input from the master chip to supply it to the target clock generation unit 200.

Here, the reference clock supply unit 100 of the master chip may transmit the reference clock to the input terminal of each slave chip for connection to the vibrator through the clock output terminal of the master chip, and the reference clock may be input to the vibrator driver for buffering the clock of the reference clock supply unit 100 provided inside the slave chip.

Next, a plurality of target clock generating units 200 may be provided to correspond to each of one master chip and a plurality of slave chips, and the plurality of target clock generating units 200 may multiply the frequencies of the target clocks by the same multiple to generate the same target clocks of the second frequency.

Accordingly, in the present disclosure, by individually supplying low-frequency reference clocks to each of a plurality of chips and multiplying the low frequencies of the reference clocks in each chip by N times to generate and share a target clock, it is possible to reduce input/output operation frequency and power consumption when performing clock synchronization.

Fig. 4 is a diagram for describing a multi-chip clock synchronization apparatus according to a first embodiment of the present disclosure.

As shown in fig. 4, a multi-chip clock synchronization apparatus according to a first embodiment of the present disclosure may include: a reference clock supply unit 100 that supplies a reference clock f_ref of a first frequency to each chip 310 of the plurality of chips 300; and a target clock generation unit 200 that generates a target clock f_sys of a second frequency based on the reference clock of the first frequency input to each chip.

Here, the reference clock supply unit 100 may be disposed outside the plurality of chips 300 and generate the reference clock of the first frequency to equally supply the reference clock of the first frequency to the respective chips 310 of the plurality of chips 300.

In addition, the target clock generation unit 200 may be separately provided inside each chip 310, and may generate a target clock of a second frequency based on the reference clock of the first frequency when the reference clock of the first frequency is input for each chip 310.

Here, the reference clock supply unit 100 may include an oscillation element. For example, the oscillating element may include an RC oscillator, an LC oscillator, and a crystal oscillator.

In addition, when generating the reference clock of the first frequency, the reference clock supply unit 100 may determine the first frequency of the reference clock based on at least one condition of whether or not jitter is generated in the target clock generation unit 200 and the total number of the respective chips 310 in the plurality of chips 300.

For example, when the number of the plurality of chips increases, the reference clock supply unit 100 may determine the first frequency of the reference clock to be lower.

The reason is that as the number of the plurality of chips increases, the clock transmission speed decreases, and thus power consumption may increase.

Accordingly, in the present disclosure, when the number of the plurality of chips increases, the first frequency of the reference clock may be determined to be lower, thereby reducing power consumption due to clock transmission.

In addition, the reference clock supply unit 100 may determine a minimum value of the first frequency of the reference clock based on the jitter generation of the target clock generation unit 200.

For example, if jitter is generated when the target clock generation unit 200 multiplies the first frequency of the reference clock by N times, the reference clock supply unit 100 may determine the first frequency lower by N times as the lowest frequency of the reference clock.

The reason is that if the first frequency of the reference clock is too low, jitter may be generated when the target clock generating unit 200 multiplies the first frequency of the reference clock.

Accordingly, in the present disclosure, the minimum value of the first frequency of the reference clock may be determined in consideration of the multiplication frequency of the jitter generated in the target clock generating unit 200.

Accordingly, the present disclosure can minimize jitter generation in a target clock generation unit while reducing power consumption due to clock transmission.

In addition, when the reference clocks are supplied to the plurality of chips, the reference clock supply unit 100 may simultaneously transmit the same reference clock to the plurality of chips.

In some cases, when the reference clocks are supplied to the plurality of chips, the reference clock supply unit 100 may transmit the same reference clock to the plurality of chips with a time difference.

As another case, when the reference clocks are supplied to the plurality of chips, the reference clock supply unit 100 may sequentially transmit the same reference clock to the plurality of chips.

As an example, the reference clock supply unit 100 may sequentially transmit the same reference clock to the plurality of chips based on preset priorities of the plurality of chips.

Next, when the reference clocks are supplied to the plurality of chips, the reference clock supply unit 100 may supply the reference clock f_ref through the clock input terminal CK 315 of each chip 310.

In addition, the target clock generation unit 200 may be provided in the same number as the total number of the respective chips 310 in the plurality of chips 300, and may be provided inside the respective chips 310 to correspond one-to-one to the respective chips 310.

Next, the target clock generation unit 200 may generate a target clock of the second frequency (where f_sys is a target clock frequency of the system, f_ref is a reference clock frequency, and N is a natural number) by the equation f_sys=f_ref×n.

Here, the target clock generation unit 200 may change the N value according to a set value of the pre-stored firmware.

Accordingly, in the first embodiment of the present disclosure, the low frequency reference clock may be supplied to the target clock generating unit 200 provided inside the plurality of chips by the reference clock supplying unit 100 provided outside the plurality of chips including the plurality of chips and multiplied in the target clock generating unit 200 of each chip, thereby generating and sharing the target clock.

Accordingly, in the first embodiment of the present disclosure, a low-frequency reference clock is transmitted, thereby reducing input/output operation frequency and power consumption.

Fig. 5 is a diagram for describing the target clock generation unit in fig. 4.

In the first embodiment of the present disclosure, a plurality of target clock generating units may be provided to correspond to respective chips of the plurality of chips, respectively, and the plurality of target clock generating units may multiply the frequencies of the target clocks by the same multiple to generate the target clocks of the same second frequency.

As shown in fig. 5, the target clock generation unit may include a phase frequency detector 210, a voltage controlled oscillator 220, and a clock multiplier 230.

In some cases, the target clock generation unit may further include a filter unit electrically connected between the phase frequency detector 210 and the voltage controlled oscillator 220 to remove noise from the clock signal.

Here, when the reference clock f_ref of the first frequency and the multiplied N-times clock are input, the phase frequency detector 210 may detect a phase difference between the reference clock and the multiplied N-times clock.

In addition, the voltage controlled oscillator 220 may control the phase of the multiplied N-times clock based on the phase difference detected by the phase frequency detector 210 to output the target clock of the second frequency.

Next, the clock multiplier 230 may multiply the frequency of the clock whose phase is controlled by the voltage controlled oscillator 220 by N times to feed back the multiplied clock to the phase frequency detector 210 by N times.

Here, the clock multiplier 230 may generate the target clock of the second frequency by the equation f_sys=f_ref×n (where f_sys is the target clock frequency of the system, f_ref is the reference clock frequency, and N is a natural number).

In this case, if the N value is changed according to the set value of the pre-stored firmware when multiplying the frequency of the target clock by N times, the clock multiplier 230 may multiply the frequency of the target clock based on the changed N value.

In addition, the target clock generation unit of the present disclosure may modify various circuit designs based on a Phase Locked Loop (PLL) circuit.

Fig. 6 is a diagram for describing a multi-chip clock synchronization apparatus according to a second embodiment of the present disclosure.

As shown in fig. 6, a multi-chip clock synchronization apparatus according to a second embodiment of the present disclosure may include: a clock supply unit 100 that supplies a reference clock f_ref of a first frequency to the master chip 410 and the plurality of slave chips 420; and a target clock generating unit 200 that generates a target clock f_sys of a second frequency based on the reference clock of the first frequency.

Here, the reference clock supply unit 100 may be disposed on a master chip 410 among a plurality of chips including one master chip 410 and a plurality of slave chips 420, and generate a reference clock F-REF of a first frequency to equally supply the reference clock of the first frequency to the target clock generation unit 200 of the master chip 410 and the target clock generation units 200 of the respective slave chips 420.

In addition, the target clock generation unit 200 may be separately provided inside the master chip 410 and the slave chip 420, and may generate the target clock based on the reference clock of the first frequency when the reference clock of the first frequency is input from the master chip 410.

Here, the reference clock supply unit 100 may include a vibrator 130, a vibrator driver 110 driving the vibrator 130 to output a vibration frequency, and a clock distribution part 120 dividing the vibration frequency based on a preset division ratio to generate a reference clock of a first frequency.

In this case, one end of the vibrator 130 may be connected to the input terminal XI 412 of the main chip 410, and the other end is connected to the output terminal XO 413 of the main chip 410.

As an example, vibrator 130 may include a crystal oscillator.

In addition, the clock distribution part 120 may generate a reference clock of the first frequency by the equation f_ref=f_ XOCS/R (where f_ref is a reference clock frequency, f_ XOCS is a vibration frequency, and R is a frequency division ratio).

Here, the reference clock supply unit 100 may change the R value according to a set value of the pre-stored firmware.

In addition, the reference clock supply unit 100 may be separately provided inside the master chip 410 and the slave chips 420, the reference clock supply unit 100 provided inside the master chip 410 may be turned on to generate the reference clock, and the reference clock supply unit 100 provided inside each of the plurality of slave chips 420 may be turned off to be disabled not to generate the reference clock.

Here, the reference clock supply unit 100 of the master chip 410 may transmit the reference clock to the clock input terminal CK 425 of each slave chip 420 through the clock output terminal CK 415 of the master chip 410, and the reference clock input to the slave chip 420 may be input to the target clock generation unit 200 provided inside the slave chip 420.

In this case, the reference clock supply unit 100 provided inside each slave chip 420 is turned off to be deactivated, and thus the input terminal XI 422 and the output terminal XO 423 of the slave chip 420 for connecting the vibrator may be disconnected to block the electrical connection with the external element.

In addition, when generating the reference clock of the first frequency, the reference clock supply unit 100 may determine the first frequency of the reference clock based on at least one condition of the total number of the plurality of slave chips 420 and whether jitter is generated in the target clock generation unit 200.

For example, when the number of the plurality of slave chips 420 increases, the reference clock supply unit 100 may determine the first frequency of the reference clock to be lower.

The reason is that as the number of the plurality of slave chips increases, the clock transmission speed decreases, and thus power consumption may increase.

Accordingly, in the present disclosure, when the number of the plurality of slave chips increases, the first frequency of the reference clock may be determined to be lower, thereby reducing power consumption due to clock transmission.

In addition, when the reference clocks are supplied to the plurality of slave chips 420, the reference clock supply unit 100 of the master chip 410 may simultaneously transmit the same reference clock to the plurality of slave chips 420.

In some cases, when the reference clocks are supplied to the plurality of slave chips 420, the reference clock supply unit 100 of the master chip 410 may transmit the same reference clock to the plurality of slave chips 420 with a time difference.

As another case, when the reference clocks are supplied to the plurality of slave chips 420, the reference clock supply unit 100 of the master chip 410 may sequentially transmit the same reference clock to the plurality of slave chips 420.

As an example, the reference clock supply unit 100 of the master chip 410 may sequentially transmit the same reference clock to the plurality of slave chips 420 based on preset priorities of the plurality of slave chips 420.

Next, when the reference clocks are supplied to the plurality of slave chips 420, the reference clock supply unit 100 of the master chip 410 may supply the reference clock f_ref through the clock input terminal CK 425 of each slave chip 420.

In addition, the target clock generation unit 200 may be provided in the same number as the total number of one master chip 410 and a plurality of slave chips 420, and may be provided inside each chip to correspond to each chip one by one.

Accordingly, in the second embodiment of the present disclosure, the low frequency reference clock may be supplied to the target clock generating unit 200 provided inside each of the master chip 410 and the plurality of slave chips 420 by the reference clock supplying unit 100 provided inside the master chip 410 and the low frequency of the reference clock may be multiplied in the target clock generating unit 200 of each chip, thereby generating and sharing the target clock.

Accordingly, in the second embodiment of the present disclosure, a low-frequency reference clock is transmitted, thereby reducing input/output operation frequency and power consumption, and a vibrator of an active element is used inside the main chip 410, without using an external passive element, thereby reducing design costs.

Fig. 7 is a diagram for describing the target clock generation unit in fig. 6.

In the second embodiment of the present disclosure, the plurality of target clock generating units 200 may be provided to correspond to one master chip and a plurality of slave chips, respectively, and the plurality of target clock generating units 200 may multiply the frequencies of the target clocks by the same multiple to generate the same target clocks of the second frequency.

As shown in fig. 7, the target clock generation unit 200 may include a phase frequency detector 210, a voltage controlled oscillator 220, and a clock multiplier 230.

In some cases, the target clock generation unit 200 may further include a filter unit electrically connected between the phase frequency detector 210 and the voltage controlled oscillator 220 to remove noise from the clock signal.

Here, the reference clock f_ref of the first frequency may be input through the clock distribution part 120, and the clock distribution part 120 divides the vibration frequency f_osc based on a preset division ratio to generate the reference clock of the first frequency.

The clock distribution portion 120 may generate a reference clock of the first frequency by the equation f_ref=f_ XOCS/R (where f_ref is the reference clock frequency, f_ XOCS is the vibration frequency, and R is the frequency division ratio).

In this case, when the R value is changed according to the set value of the pre-stored firmware, the clock distribution part 120 may divide the vibration frequency f_osc based on the changed R value.

In this case, when the N value is changed according to the set value of the pre-stored firmware when multiplying the frequency of the target clock by N times, the clock multiplier 230 may multiply the frequency of the target clock based on the changed N value.

Fig. 8 is a diagram for describing a multi-chip clock synchronization apparatus according to a third embodiment of the present disclosure.

As shown in fig. 8, a multi-chip clock synchronization apparatus according to a third embodiment of the present disclosure may include: a clock supply unit 100 that supplies a reference clock f_ref of a first frequency to the master chip 410 and the plurality of slave chips 420; and a target clock generating unit 200 that generates a target clock f_sys of a second frequency based on the reference clock of the first frequency.

In this case, one end of the vibrator 130 may be connected to an input terminal 412 of the main chip 410, and the other end is connected to an output terminal 413 of the main chip 410.

As an example, vibrator 130 may include a crystal oscillator.

In addition, the reference clock supply unit 100 may be separately provided inside the master chip 410 and the slave chips 420, the reference clock supply unit 100 provided inside the master chip 410 may be turned on to be enabled to generate the reference clock, the reference clock supply unit 100 provided inside each of the plurality of slave chips 420 may be turned off and the reference clock input from the master chip 410 may be buffered to be supplied to the target clock generation unit 200.

Here, the reference clock supply unit 100 of the master chip 410 may transmit the reference clock to the input terminal XI 422 of each slave chip 420 for connection to the vibrator through the clock output terminal CK 415 of the master chip 410, and the reference clock may be input to the vibrator driver 110 for buffering the clock of the reference clock supply unit 100 provided inside the slave chip 420.

In this case, each slave chip 420 may be electrically connected only to the input terminal XI 422 for connecting the vibrator for inputting the reference clock from the master chip 410, and the output terminal XO 423 for connecting the vibrator may be disconnected to block the electrical connection with the external element.

In the third embodiment of the present disclosure, each slave chip 420 may reduce noise of the reference clock by receiving the reference clock to the input terminal XI 422 for connecting the vibrator and buffering the reference clock by the vibrator driver 110 for buffering the clock.

Accordingly, in the third embodiment of the present disclosure, the remaining components and operations are the same as those of the second embodiment of the present disclosure except for the feature of receiving the reference clock to the input terminal XI 422 for connecting the vibrator and buffering the reference clock by the vibrator driver 110 for buffering the clock in each slave chip 420, and thus a detailed description will be omitted.

Accordingly, in the third embodiment of the present disclosure, the target clock may be generated and shared by supplying the low-frequency reference clock to the target clock generating unit 200 through the reference clock supplying unit 100 provided inside the master chip 410 via the vibrator driver 110 and the clock distribution part 120 provided inside each of the master chip 410 and the plurality of slave chips 420 and multiplying the low frequency of the reference clock in the target clock generating unit 200 of each chip.

Accordingly, in the third embodiment of the present disclosure, a low-frequency reference clock is transmitted, thereby reducing input/output operation frequency and power consumption, and a vibrator of an active element is used inside the main chip 410, without using an external passive element, thereby reducing design costs, and noise of a target clock is reduced through buffering of the reference clock.

Fig. 9 and 10 are diagrams for describing a display device including a multi-chip clock synchronization device according to the present disclosure.

As shown in fig. 9 and 10, the display device may include a panel 10, a data driving device 20, a gate driving device 30, a touch driving device 40, a data processing device 50, a multi-chip clock synchronizing device 60, and the like.

Here, at least one of the data driving device 20, the gate driving device 30, the touch driving device 40, the data processing device 50, and the multi-chip clock synchronizing device 60 may be included in another device.

For example, the data driving device 20 may be included in the touch driving device 40, and the gate driving device 30 may be included in the data driving device 20.

As another case, some configurations of only one driving device may be included in another driving device.

As an example, in the multi-chip clock synchronization apparatus 60, some configurations such as the reference clock supply unit and the target clock generation unit may be included in at least one of the data driving apparatus 20, the gate driving apparatus 30, the touch driving apparatus 40, and the data processing apparatus 50.

In addition, the data driving device 20 may drive the data lines DL connected to the pixels P, the gate driving device 30 may drive the gate lines GL connected to the pixels P, and the touch driving device 40 may drive the touch sensors TS disposed on the panel 10.

The data driving device 20 may supply data voltages to the data lines DL to display images in the respective pixels P of the panel 10.

In addition, the data driving device 20 may receive image data and a Data Control Signal (DCS) from the data processing device 50, and generate data voltages to drive the respective pixels according to gray values of the respective pixels indicated by the image data.

Next, the gate driving device 30 may supply a scan signal to the gate line GL to turn on and off the transistors located in the respective pixels P.

In addition, the gate driving device 30 may receive a Gate Control Signal (GCS) including a plurality of clock signals from the data processing device 50, generate a scan signal using the clock signals, and supply the scan signal to the Gate Line (GL).

Next, the panel 10 may include a display panel 112, and further include a Touch Screen Panel (TSP) 111.

Here, the display panel 112 and the touch screen panel 111 may share some components with each other.

A plurality of Touch Sensors (TS) may be disposed on the panel 10, and the touch driving device 40 may drive the Touch Sensors (TS) using touch driving signals.

Next, the data processing device 50 may control the timing of each of the driving devices 20, 30, and 40 by the control signals GCS, DCS, and TCS.

In addition, the touch driving device 40 may generate a sensing value of the Touch Sensor (TS) according to a response signal formed in the Touch Sensor (TS) in response to the touch driving signal and calculate touch coordinates of an object using the sensing values of the plurality of Touch Sensors (TS), and the calculated touch coordinates may be transmitted to another device such as a host for use.

Next, as shown in fig. 9, the multi-chip clock synchronization device 60 may apply a target clock to the plurality of chips of the touch driving device 40 to synchronize clocks of the plurality of chips.

Here, the multi-chip clock synchronization apparatus may include a reference clock supply unit connected to the plurality of chips and supplying the reference clock of the first frequency to the respective chips, and a target clock generation unit generating the target clock of the second frequency based on the reference clock of the first frequency input to the respective chips.

In this case, the reference clock supply unit may generate a reference clock of a first frequency lower than the second frequency of the target clock by N times to supply the generated reference clock to the respective chips, and the target clock generation unit may multiply the first frequency of the reference clock by N times to generate the target clock of the second frequency when the reference clock of the first frequency is input.

In the multi-chip clock synchronizing device 60, the reference clock supply unit may generate the reference clock outside the plurality of chips to equally supply the reference clock of the first frequency to the plurality of chips, and the clock generation unit may be separately provided inside the respective chips to generate the target clock of the second frequency for the respective chips.

In some cases, in the multi-chip clock synchronizing device 60, the reference clock supply unit may generate the reference clock of the first frequency from a master chip among a plurality of chips including one master chip and a plurality of slave chips and equally supply the reference clock of the first frequency to the plurality of slave chips through clock output terminals of the master chip, and the target clock generation unit may be separately provided inside the master chip and the slave chips to generate the target clock of the second frequency for each chip.

In addition, as shown in fig. 10, the multi-chip clock synchronization device 60 may apply the target clock to devices including a plurality of chips (e.g., the data driving device 20, the gate driving device 30, the touch driving device 40, and the data processing device 50) to synchronize clocks of the plurality of chips.

Here, the multi-chip clock synchronizing device 60 may be provided individually in each driving device, generate and supply a target clock required for each driving device, and synchronize clocks of a plurality of chips included in each driving device.

Accordingly, the multi-chip clock synchronization device 60 of the present disclosure can reduce the input/output operation frequency and power consumption when performing clock synchronization of the respective driving devices by individually supplying the low-frequency reference clocks to the respective chips and multiplying the low frequencies of the reference clocks in the respective chips by N times to generate and share the target clocks.

Fig. 11 is a clock synchronization method of a multi-chip clock synchronization apparatus according to a first embodiment of the present disclosure, in which a reference clock supply unit 100 may be disposed outside a plurality of chips 300, and a target clock generation unit 200 may be separately disposed inside each chip 310.

As shown in fig. 11, the reference clock supply unit 100 may generate a reference clock of a first frequency N times lower than a second frequency of the target clock (S110).

Next, the reference clock supply unit 100 may supply the generated reference clock of the first frequency to each chip 310 of the plurality of chips 300.

Next, when the reference clock of the first frequency is input to each chip 310, the target clock generation unit 200 may multiply the first frequency of the reference clock by N times in each chip (S120) to generate the target clock of the second frequency (S130).

Next, in the target clock generation unit 200, the plurality of chips 300 may be all synchronized to the target clock of the same frequency by supplying the generated target clock of the second frequency to the respective chips (S140).

Fig. 12 is a clock synchronization method of a multi-chip clock synchronization apparatus according to a second embodiment of the present disclosure, in which a reference clock supply unit 100 and a target clock generation unit 200 may be disposed inside a master chip 410 and a plurality of slave chips 420, respectively.

Here, the reference clock supply unit 100 disposed inside the master chip 410 may be turned on to generate the reference clock, and the reference clock supply unit 100 disposed inside each of the plurality of slave chips 420 may be turned off to be disabled not to generate the reference clock.

In addition, the target clock generating unit 200 provided inside the master chip 410 may be turned on to be enabled to generate a target clock, and the target clock generating unit 200 provided inside each of the plurality of slave chips 420 may be turned on to be enabled to generate a target clock.

As shown in fig. 12, in the second embodiment of the present disclosure, the reference clock supply unit 100 of the main chip 410 may generate a reference clock of a first frequency N times lower than a second frequency of the target clock (S210).

Here, when driving the vibrator to output the vibration frequency, the reference clock supply unit 100 of the main chip 410 may divide the vibration frequency based on a preset division ratio to generate the reference clock of the first frequency.

Next, the reference clock supply unit 100 of the master chip 410 may supply the generated reference clock of the first frequency to each of the plurality of slave chips 420.

Here, the reference clock supply unit 100 of the master chip 410 may transmit the reference clock to the clock input terminal of each slave chip 420 through the clock output terminal of the master chip 410, and the reference clock input to the slave chip 420 may be input to the target clock generation unit 200 provided inside the slave chip 420.

Next, when the reference clock of the first frequency is input, the target clock generation unit 200 of the master chip 410 and the target clock generation units 200 of the respective slave chips 420 may multiply the first frequency of the reference clock by N times (S220) to generate the target clock of the second frequency (S230).

Next, in the target clock generation unit 200, by supplying the generated target clock of the second frequency to each of the master chip 410 and the plurality of slave chips 420, one master chip 410 and the plurality of chips 420 may all be synchronized to the target clock of the same frequency (S240).

Fig. 13 is a clock synchronization method of a multi-chip clock synchronization apparatus according to a third embodiment of the present disclosure, in which a reference clock supply unit 100 and a target clock generation unit 200 may be disposed inside a master chip 410 and a plurality of slave chips 420, respectively.

Here, the reference clock supply unit 100 disposed inside the master chip 410 may be turned on to be enabled to generate the reference clock, and the reference clock supply unit 100 disposed inside each of the plurality of slave chips 420 may be turned off and may buffer the reference clock input from the master chip 410 to be supplied to the target clock generation unit 200.

Here, the reference clock supply unit 100 of the master chip 410 may transmit the reference clock to the input terminal of each slave chip 420 for connection to the vibrator through the clock output terminal of the master chip 410, and the reference clock may be input to the vibrator driver for buffering the clock of the reference clock supply unit 100 provided inside the slave chip 420.

In addition, the target clock generating unit 200 provided inside the master chip 410 may be turned on to be enabled to generate a target clock, and the target clock generating unit 200 provided inside each of the plurality of slave chips 420 may also be turned on to be enabled to generate a target clock.

As shown in fig. 13, in the third embodiment of the present disclosure, the reference clock supply unit 100 of the main chip 410 may generate a reference clock of a first frequency N times lower than a second frequency of the target clock (S310).

Here, the reference clock supply unit 100 of the master chip 410 may transmit the reference clock to the input terminal of each slave chip 420 for connection to the vibrator through the clock output terminal of the master chip 410, and the reference clock may be input to the vibrator driver 110 for buffering the clock of the reference clock supply unit 100 provided inside the slave chip 420.

Next, each slave chip 420 may reduce noise of the reference clock by receiving the reference clock to an input terminal for connecting a vibrator and buffering the reference clock by a vibrator driver for buffering the clock (S320).

In addition, the buffered reference clock may be input to the target clock generating unit 200 provided inside the slave chip 420.

Next, when the reference clock of the first frequency is input, the target clock generation unit 200 of the master chip 410 and the target clock generation units 200 of the respective slave chips 420 may multiply the first frequency of the reference clock by N times (S330) to generate the target clock of the second frequency (S340).

Next, in the target clock generation unit 200, by supplying the generated target clock of the second frequency to each of the master chip 410 and the plurality of slave chips 420, one master chip 410 and the plurality of chips 420 may all be synchronized to the target clock of the same frequency (S350).

The present disclosure described above may be implemented as computer readable code on a program recording medium. The computer readable medium includes all types of recording apparatuses storing data readable by a computer system. As examples of the computer readable medium, there are a Hard Disk Drive (HDD), a Solid State Disk (SSD), a Silicon Disk Drive (SDD), ROM, RAM, CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. In addition, the computer may include a processor of the artificial intelligence device.

Claims

1. A multi-chip clock synchronization apparatus, the multi-chip clock synchronization apparatus comprising:

a reference clock supply unit connected to the plurality of chips and configured to supply a reference clock having a first frequency to each of the plurality of chips; and

A target clock generation unit configured to generate a target clock having a second frequency based on the reference clock of the first frequency,

Wherein the reference clock supply unit is configured to generate the reference clock having the first frequency lower than the second frequency of the target clock by a factor of N to supply the generated reference clock to each of the plurality of chips, and

The target clock generation unit is configured to multiply the first frequency of the reference clock by N times to generate the target clock having the second frequency when the reference clock of the first frequency is input.

2. The multi-chip clock synchronization apparatus according to claim 1, wherein the reference clock supply unit is configured to generate the reference clock outside the plurality of chips such that the reference clock is equally supplied to the plurality of chips, and

The target clock generation unit is provided individually inside each of the plurality of chips,

The target clock generation unit provided inside each of the plurality of chips is configured to generate the target clock having the second frequency for each of the plurality of chips.

3. The multi-chip clock synchronization apparatus of claim 2, wherein the target clock generation unit provided inside each of the plurality of chips comprises:

A phase frequency detector configured to receive the reference clock and the multiplied-by-N clock, and detect a phase difference between the reference clock and the multiplied-by-N clock;

a voltage controlled oscillator configured to control a phase of a multiplied N-times clock based on the phase difference detected by the phase-frequency detector to output the target clock having the second frequency; and

A clock multiplier configured to multiply a frequency of a clock of a phase controlled by the voltage controlled oscillator by N times to feed back the multiplied clock to the phase frequency detector by N times.

4. The multi-chip clock synchronization apparatus of claim 1, wherein the plurality of chips comprises a master chip and a plurality of slave chips,

The main chip includes the reference clock supply unit,

The master chip is configured to generate the reference clock and supply the reference clock to the plurality of slave chips through clock output terminals of the master chip, and

The target clock generation unit is provided separately inside each of the master chip and the plurality of slave chips, and is configured to generate the target clock having the second frequency for each of the plurality of chips.

5. The multi-chip clock synchronization apparatus of claim 4, wherein the reference clock supply unit comprises:

A vibrator;

a vibrator driver configured to drive the vibrator to output a vibration frequency; and

And a clock distribution section configured to divide the vibration frequency based on a preset division ratio to generate the reference clock having the first frequency.

6. The multi-chip clock synchronization apparatus of claim 4, wherein the reference clock supply unit is provided separately inside each of the master chip and the plurality of slave chips,

The reference clock supply unit provided inside the main chip is turned on to be enabled to generate the reference clock, and

The reference clock supply unit provided inside each of the plurality of slave chips is turned off to be deactivated so as not to generate the reference clock.

7. The multi-chip clock synchronization apparatus of claim 6, wherein the reference clock supply unit of the master chip is configured to transmit the reference clock to the clock input terminal of each of the plurality of slave chips through the clock output terminal of the master chip, and

The reference clock input to each of the plurality of slave chips is input to the target clock generating unit provided inside each of the plurality of slave chips.

8. The multi-chip clock synchronization apparatus of claim 5, wherein the reference clock supply unit is provided separately inside each of the master chip and the plurality of slave chips,

The reference clock supply unit provided inside each of the plurality of slave chips is turned off, and is configured to buffer the reference clock input from the master chip to supply it to the target clock generation unit.

9. The multi-chip clock synchronization apparatus according to claim 8, wherein the reference clock supply unit of the master chip transmits the reference clock to input terminals of the respective slave chips for connection to the vibrator through the clock output terminals of the master chip, and

The reference clock is input to the vibrator driver for buffering a clock of the reference clock supply unit provided inside the slave chip.

10. A multi-chip clock synchronization method, the multi-chip clock synchronization method comprising the steps of:

generating a reference clock having a first frequency N times lower than a second frequency of the target clock;

supplying the reference clock having the first frequency to each of a plurality of chips;

Generating the target clock having the second frequency by multiplying the first frequency of the reference clock in each chip by N times when the reference clock of the first frequency is input to each of the plurality of chips; and

The clocks of the plurality of chips are synchronized based on a target clock having the second frequency.