CN118074682A - Comparison circuit leveling method - Google Patents
Comparison circuit leveling method Download PDFInfo
- Publication number
- CN118074682A CN118074682A CN202211480883.1A CN202211480883A CN118074682A CN 118074682 A CN118074682 A CN 118074682A CN 202211480883 A CN202211480883 A CN 202211480883A CN 118074682 A CN118074682 A CN 118074682A
- Authority
- CN
- China
- Prior art keywords
- leveling
- comparison circuit
- resistor
- branch
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012360 testing method Methods 0.000 claims abstract description 20
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000035945 sensitivity Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Hall/Mr Elements (AREA)
Abstract
The invention provides a comparison circuit leveling method, which comprises the following steps: respectively connecting a leveling resistor and a test switch in series on two input pins of the comparison circuit to form two pin branches, and grounding the two pin branches through the same adjustable resistor; adjusting the adjustable resistor to enable the current on the two input pins to reach a preset current range; the leveling resistors on the two pins are adjusted for a plurality of times, and the output of the comparison circuit is read for a plurality of times after each adjustment; counting the read results after each leveling to obtain the proportion of the first state in the read results to the total read times; and taking the adjusting result of the corresponding leveling resistor when the proportion accords with a preset range as a final result. The leveling method for the comparison circuit can level the two pins of the comparison circuit, thereby reducing the reading deviation of the comparison circuit and improving the reading accuracy.
Description
Technical Field
The invention relates to the technical field of electronic device testing, in particular to a leveling method for a comparison circuit.
Background
The comparison circuit is generally a circuit that compares the output of the target device with the output of the reference device and outputs a comparison result, and in general, the comparison circuit can identify whether the output signal value of the reference device is greater than the output signal value of the reference device or less than the output signal value of the reference device. However, since the comparison circuit has certain deviation in the preparation process, different comparison circuits produce different results when comparing the same pair of target device and reference device. Taking a magnetic memory array as a target device and a sense amplifier as a comparison circuit as an example, reading information in a single MTJ (magnetic random access memory) depends on the difference value between a parallel state resistance Rp and an anti-parallel state resistance Rap, and 1 MRAM (magnetic random access memory) formed by the MTJ array has certain statistical distribution standards of Rp and Rap (Rp and Rap distribution curves do not overlap), and proper reference resistance needs to be determined to accurately judge the stored information in a bit; the array bit reads out the 1 state or 0 state stored in the array through a sense amplifier (SA for short), and the SA is formed by combining a plurality of NMOS tubes and PMOS tubes; normally, the array comprises n SA modules, wherein one end of each SA module is an array end, and the other end of each SA module is a reference resistor; due to the technical problem, certain parameter deviation exists between the MOS tubes, so that the comparison effect of SA is affected; when certain fluctuation exists in the process, the reference end and the end to be detected are assumed to be completely consistent, and certain deviation exists in the comparison results of different SAs, so that the reading accuracy of the chip is affected.
Disclosure of Invention
The leveling method for the comparison circuit can level the two pins of the comparison circuit, thereby reducing the reading deviation of the comparison circuit and improving the reading accuracy.
The invention provides a comparison circuit leveling method, which comprises the following steps:
Respectively connecting a leveling resistor and a test switch in series on two input pins of the comparison circuit to form two pin branches, and grounding the two pin branches through the same adjustable resistor;
Adjusting the adjustable resistor to enable the current on the two input pins to reach a preset current range;
the leveling resistors on the two pins are adjusted for a plurality of times, and the output of the comparison circuit is read for a plurality of times after each adjustment;
Counting the read results after each leveling to obtain the proportion of the first state in the read results to the total read times;
and taking the adjusting result of the corresponding leveling resistor when the proportion accords with a preset range as a final result.
Optionally, adjusting the adjustable resistance includes:
and adjusting the adjustable resistor to be between a first resistance value and a second resistance value corresponding to an application target of the comparison circuit.
Optionally, the comparison circuit is a sense amplifier, the application target is a magnetic memory bit, the first resistance is a parallel state resistance of the magnetic tunnel junction, and the second resistance is an anti-parallel state of the magnetic tunnel junction.
Optionally, reading the output of the comparison circuit multiple times includes: and reading the output of the comparison circuit more than ten times.
Optionally, taking the adjustment result of the leveling resistor corresponding to the ratio meeting the preset range as a final result, including:
And taking the adjusting result of the leveling resistor corresponding to the proportion of 30% -70% as a leveling result.
Optionally, when the proportion accords with the preset range, the corresponding proportion of each adjusting result is differed from 50% when the adjusting result of the corresponding leveling resistor is multiple, and the adjusting result with the smallest difference is taken as the final result.
Optionally, the leveling resistor includes a plurality of first MOS transistors that are arranged in parallel, and by turning on and off the plurality of first MOS transistors, the resistance value of the leveling resistor can be increased or decreased according to a predetermined interval.
Optionally, the leveling resistor controls the on and off of the first MOS transistor through a control module, the control module includes voltage output branches corresponding to the first MOS transistor one to one, one end of each voltage output branch is connected with a voltage source, and the other end of each voltage output branch is grounded; each voltage output branch comprises a branch NMOS tube and a branch PMOS tube which are arranged in series, the common ends of the branch NMOS tube and the branch PMOS tube output voltage outwards to control the connection and disconnection of the corresponding first MOS tube, and the branch NMOS tube and the branch PMOS tube of the same branch control the connection and disconnection through the same signal.
Optionally, the adjustable resistor is a polysilicon resistor, a well resistor or a metal resistor.
Optionally, the test switch is a MOS transistor, a gate of the MOS transistor is connected to a test start control line, and the test start signal controls on and off of the MOS transistor.
In the technical scheme provided by the invention, the proportion of the data states output by the comparison circuit is leveled, under normal conditions, the comparison circuit can output two different states when comparing current or voltage, namely, the first state is output when the signal value of the first input pin is larger than the signal value of the second input pin, the second state is output when the signal value of the first pin is smaller than the signal value of the second input pin, and only when the signal value of the first pin is similar to or even the signal value of the second pin is the same as the signal value of the first pin, the difference of the two signal values is smaller than the recognition precision of the comparison circuit, at the moment, when the output of the comparison circuit is read, the read result is in an uncertain state, and according to the probability, the smaller the difference of the two signal values is, the distribution probability of the two results is approaching to the same in the reading process. Therefore, in the technical scheme provided by the invention, the leveling result of the comparison circuit is determined by judging the proportion of the first state to the total reading times, so that the leveling state of the comparison circuit can be accurately determined.
Drawings
FIG. 1 is a flow chart of a method for leveling a comparison circuit according to an embodiment of the invention;
FIG. 2 is a graph showing the probability of reading of the first state and the second state as the leveling resistance is adjusted in a comparison circuit leveling method according to another embodiment of the present invention;
FIG. 3 is a schematic diagram showing a leveling resistor in a comparison circuit leveling method according to another embodiment of the present invention;
fig. 4a and fig. 4b are control modules corresponding to leveling resistors on two pins of a comparison circuit in a comparison circuit leveling method according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a comparison circuit leveling method, as shown in fig. 1, comprising the following steps:
Step 100, respectively connecting a leveling resistor and a test switch in series on two input pins of a comparison circuit to form two pin branches, and grounding the two pin branches through the same adjustable resistor;
In some embodiments, as shown in fig. 2, a leveling resistor is provided on the pins of the comparison circuit, the leveling resistor being variable, the current or voltage of both input pins being able to be changed by adjustment of the leveling resistor. The adjustable resistor is variable, and the current of the two pins can be changed by adjusting the adjustable resistor, so that the current or the voltage of the two pins is in a set test range. The comparison circuit may be a circuit that compares the magnitude of current or voltage arbitrarily and outputs the comparison result. The test switch is used for controlling a test mode or an application mode, and when the test switch is conducted, a target device, such as a magnetic storage array, is shielded, and a comparison circuit is connected with the adjustable resistor to conduct a test. When the test switch is turned off, the target device is turned on with the comparison circuit, and the adjustable resistor is turned off with the comparison circuit, so that the target device is compared.
Step 200, adjusting the adjustable resistor to enable the current on the two input pins to reach a preset current range;
In some embodiments, the current on the two output pins may change when the adjustable resistor is adjusted, and the adjustment of the adjustable resistor is stopped when the current on the two output pins reaches a predetermined circuit range. For example, when the target device is a magnetic memory array, the adjustable resistance may be adjusted so that the current on both output pins is similar to the read current of the magnetic memory array.
Step 300, adjusting the leveling resistance on the two pins for a plurality of times, and reading the output of the comparison circuit for a plurality of times after each adjustment;
In some embodiments, taking a magnetic memory array as a target device and taking a sense amplifier as a comparison circuit for example, reading information in a single MTJ depends on the difference between the parallel state resistance Rp and the antiparallel state resistance Rap, while 1 MRAM composed of MTJ arrays, there is a certain statistical distribution standard of Rp and Rap (Rp and Rap distribution curves do not overlap), and it is necessary to determine an appropriate reference resistance to accurately determine the stored information in a bit. The array bit reads out the 1 state or 0 state stored in the array through a sense amplifier (SA for short), and the SA is formed by combining a plurality of NMOS tubes and PMOS tubes; normally, the array comprises n SA modules, wherein one end of each SA module is an array end, and the other end of each SA module is a reference resistor; due to the technical problem, certain parameter deviation exists between the MOS tubes, so that the comparison effect of SA is affected; when certain fluctuation exists in the process, the reference end and the end to be detected are assumed to be completely consistent, and certain deviation exists in the comparison results of different SAs, so that the reading accuracy of the chip is affected; therefore, in the present embodiment, the leveling resistance on the two pins is adjusted to compensate for the resistance deviation on the two pins.
Step 400, counting the read results after each leveling to obtain the proportion of the first state in the read results to the total read times;
In some embodiments, when comparing current or voltage, the comparison circuit can output two different states, namely, the first state is output when the signal value of the first input pin is larger than the signal value of the second input pin, the second state is output when the signal value of the first pin is smaller than the signal value of the second input pin, and only when the signal value of the first pin is close to or even the same as the signal value of the second pin, the difference between the two signal values is smaller than the recognition precision of the comparison circuit, at this time, when the output of the comparison circuit is read, the read result is in an uncertain state, and according to probability, the smaller the difference between the two signal values is, the distribution probability of the two results in the reading process is more approximately equal.
And 500, taking the adjustment result of the corresponding leveling resistor when the proportion accords with a preset range as a final result.
In some embodiments, the closer the ratio of the first state is to 50%, the better the leveling result is indicated, but a range of values is set in this embodiment due to the influence of the step of the resistance change during the leveling resistance adjustment and considering the influence of the leveling efficiency. The range value may be, for example, 50% ± 20%.
In the technical scheme provided by the embodiment of the invention, the proportion of the data states output by the comparison circuit is leveled, and under normal conditions, the comparison circuit can output two different states when comparing current or voltage, namely, the first state is output when the signal value of the first input pin is larger than the signal value of the second input pin, the second state is output when the signal value of the first pin is smaller than the signal value of the second input pin, and only when the signal value of the first pin is similar or even identical to the signal value of the second pin, the difference of the two signal values is smaller than the recognition precision of the comparison circuit, at the moment, when the output of the comparison circuit is read, the read result is in an uncertain state, and according to probability, the smaller the difference of the two signal values is, the distribution probability of the two results in the reading process is more approximate to the same. As shown in fig. 3, P0 and P1 are probability curves of the first state and the second state, respectively, under different adjustment results, and when the adjustment results are close to the intersection point of the two curves, the comparison circuit can be considered to be leveled. Therefore, in the technical scheme provided by the invention, the leveling result of the comparison circuit is determined by judging the proportion of the first state to the total reading times, so that the leveling state of the comparison circuit can be accurately determined.
As an alternative embodiment, adjusting the adjustable resistance includes:
and adjusting the adjustable resistor to be between a first resistance value and a second resistance value corresponding to an application target of the comparison circuit.
In some embodiments, taking a magnetic memory array as the target device and a sense amplifier as the comparison circuit for example, the reference resistance thereof typically needs to be set to a value between the parallel and anti-parallel states of the magnetic tunnel junction in order to identify the parallel and anti-parallel states of the magnetic tunnel junction during the comparison. In the leveling process, the resistance value of the reference resistor is taken as a leveling target, namely, the adjustable resistor is set between the first resistance value and the second resistance value. When the magnetic memory array is used as a target device and the sense amplifier is used as a comparison circuit, the resistance value of the adjustable resistor is between the parallel state resistance value and the anti-parallel state resistance value of the magnetic tunnel junction. As a preferred embodiment, the adjustable resistor may be an average value of the first resistance value and the second resistance value.
As an alternative embodiment, the comparison circuit is a sense amplifier, the application target is a magnetic memory bit, the first resistance is a parallel state resistance of the magnetic tunnel junction, and the second resistance is an anti-parallel state of the magnetic tunnel junction.
As an alternative embodiment, the reading the output of the comparison circuit a plurality of times includes: and reading the output of the comparison circuit more than ten times.
As an alternative embodiment, the adjusting result of the leveling resistance corresponding to the ratio meeting the predetermined range is taken as a final result, which includes:
And taking the adjusting result of the leveling resistor corresponding to the proportion of 30% -70% as a leveling result.
In some embodiments, the sensitivity of the comparison circuit may be adjusted according to the specific value, and the ratio range may be narrowed by 50% when the sensitivity of the comparison circuit is lower, and may be enlarged by 50% when the sensitivity of the comparison circuit is higher. For example, when the sensitivity of the comparison circuit is low, a range of 50% ± 5% may be selected as the satisfactory range, and when the sensitivity of the comparison circuit is low, a range of 30% to 70% may be selected as the satisfactory range.
As an alternative embodiment, when there are a plurality of adjustment results of the leveling resistor corresponding to the ratio meeting the predetermined range, the ratio corresponding to each adjustment result is differed from 50%, and the adjustment result with the smallest difference is taken as the final result.
In some embodiments, since the range value is set, it is unavoidable that a plurality of leveling results all conform to the range setting, and at this time, according to the leveling principle described in the foregoing embodiments, the leveling result corresponding to the proportion closest to 50% is taken as the final result.
As an optional implementation manner, the leveling resistor includes a plurality of first MOS transistors arranged in parallel, and the resistance value of the leveling resistor can be increased or decreased according to a predetermined interval by turning on and off the plurality of first MOS transistors. Of course, other resistances with logically changed resistance values may be used as the leveling resistor in the present embodiment.
As an alternative implementation manner, as shown in fig. 4a and fig. 4b, fig. 4a and fig. 4b are control modules corresponding to leveling resistors on two pins of a comparison circuit, the leveling resistors control on and off of the first MOS transistor through the control modules, the control modules include voltage output branches corresponding to the first MOS transistor one by one, one end of each voltage output branch is connected with a voltage source, and the other end of each voltage output branch is grounded; each voltage output branch comprises a branch NMOS tube and a branch PMOS tube which are arranged in series, the common ends of the branch NMOS tube and the branch PMOS tube output voltage outwards to control the connection and disconnection of the corresponding first MOS tube, and the branch NMOS tube and the branch PMOS tube of the same branch control the connection and disconnection through the same signal.
As an alternative embodiment, the adjustable resistor is a polysilicon resistor, a well resistor, or a metal resistor.
As an optional implementation manner, the test switch is a MOS transistor, a gate of the MOS transistor is connected to a test start control line, and the test start signal controls on and off of the MOS transistor.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A method of leveling a comparison circuit, the method comprising:
Respectively connecting a leveling resistor and a test switch in series on two input pins of the comparison circuit to form two pin branches, and grounding the two pin branches through the same adjustable resistor;
Adjusting the adjustable resistor to enable the current on the two input pins to reach a preset current range;
the leveling resistors on the two pins are adjusted for a plurality of times, and the output of the comparison circuit is read for a plurality of times after each adjustment;
Counting the read results after each leveling to obtain the proportion of the first state in the read results to the total read times;
and taking the adjusting result of the corresponding leveling resistor when the proportion accords with a preset range as a final result.
2. The method of claim 1, wherein adjusting the adjustable resistance comprises:
and adjusting the adjustable resistor to be between a first resistance value and a second resistance value corresponding to an application target of the comparison circuit.
3. The method of claim 2, wherein the comparison circuit is a sense amplifier, the application target is a magnetic memory bit, the first resistance is a parallel state resistance of a magnetic tunnel junction, and the second resistance is an anti-parallel state of the magnetic tunnel junction.
4. The method of claim 1, wherein reading the output of the comparison circuit multiple times comprises: and reading the output of the comparison circuit more than ten times.
5. The method according to claim 1, wherein the adjusting result of the leveling resistance corresponding to the ratio meeting the predetermined range is taken as a final result, comprising:
And taking the adjusting result of the leveling resistor corresponding to the proportion of 30% -70% as a leveling result.
6. The method according to claim 5, wherein when there are a plurality of adjustment results of the leveling resistor corresponding to the ratio meeting a predetermined range, the ratio corresponding to each adjustment result is differed from 50%, and the adjustment result with the smallest difference is taken as the final result.
7. The method according to claim 1, wherein the leveling resistor comprises a plurality of first MOS transistors arranged in parallel, and the resistance of the leveling resistor can be increased or decreased at predetermined intervals by turning on and off the plurality of first MOS transistors.
8. The method of claim 6, wherein the leveling resistor controls the on and off of the first MOS transistor through a control module, the control module comprises voltage output branches corresponding to the first MOS transistor one to one, one end of each voltage output branch is connected with a voltage source, and the other end of each voltage output branch is grounded; each voltage output branch comprises a branch NMOS tube and a branch PMOS tube which are arranged in series, the common ends of the branch NMOS tube and the branch PMOS tube output voltage outwards to control the connection and disconnection of the corresponding first MOS tube, and the branch NMOS tube and the branch PMOS tube of the same branch control the connection and disconnection through the same signal.
9. The method of claim 1, wherein the tunable resistor is a polysilicon resistor, a well resistor, or a metal resistor.
10. The method of claim 1, wherein the test switch is a MOS transistor, a gate of the MOS transistor is connected to a test start control line, and the test start signal controls on and off of the MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211480883.1A CN118074682A (en) | 2022-11-23 | 2022-11-23 | Comparison circuit leveling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211480883.1A CN118074682A (en) | 2022-11-23 | 2022-11-23 | Comparison circuit leveling method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118074682A true CN118074682A (en) | 2024-05-24 |
Family
ID=91094350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211480883.1A Pending CN118074682A (en) | 2022-11-23 | 2022-11-23 | Comparison circuit leveling method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118074682A (en) |
-
2022
- 2022-11-23 CN CN202211480883.1A patent/CN118074682A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101204659B1 (en) | The method of adaptively programming, testing and sorting magnetic random access memory array | |
| KR100951333B1 (en) | Storage device using resistance varying storage element and reference resistance value decision method for the device | |
| US20030090285A1 (en) | System for testing integrated circuit devices | |
| US10008246B2 (en) | Memory and reference circuit calibration method thereof | |
| US8351239B2 (en) | Dynamic sense current supply circuit and associated method for reading and characterizing a resistive memory array | |
| CN108257633B (en) | MRAM chip and reading method of memory cell thereof | |
| US10861574B2 (en) | Apparatus for memory device testing and field applications | |
| US8213213B2 (en) | Reference current generator for resistance type memory and method thereof | |
| US11817159B2 (en) | Circuit for detecting anti-fuse memory cell state and memory | |
| KR100656456B1 (en) | Apparatus and method for on die termination of semiconductor memory | |
| US6806691B2 (en) | Regulator circuit for independent adjustment of pumps in multiple modes of operation | |
| CN118074682A (en) | Comparison circuit leveling method | |
| US6785163B2 (en) | Trim circuit and method for tuning a current level of a reference cell in a flash memory | |
| US6563740B2 (en) | Electronic circuit and method for testing and refreshing non-volatile memory | |
| US6667908B2 (en) | Reading circuit for a non-volatile memory | |
| CN113948142A (en) | Anti-fuse memory cell state detection circuit and memory | |
| TWI571876B (en) | Resistive memory apparatus and memory cell thereof | |
| KR100370152B1 (en) | Circuit for programming of multi-level flash memory | |
| CN111724830A (en) | Voltage enhancement type reading amplifying circuit | |
| US20230016004A1 (en) | Anti-fuse circuit and circuit testing method | |
| TWI822395B (en) | Flash memory device and program method thereof | |
| US20040085794A1 (en) | Memory cell sensing system and method | |
| US8085056B2 (en) | Circuit for testing internal voltage of semiconductor memory apparatus | |
| US9466366B1 (en) | Resistive memory and memory cell thereof | |
| CN117976019A (en) | Flash memory device and programming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |