CN118072806A - Memory detection method, integrated circuit device, storage medium, and laser radar - Google Patents
Memory detection method, integrated circuit device, storage medium, and laser radar Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
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Abstract
The embodiment of the application discloses a memory detection method, an integrated circuit device, a storage medium and a laser radar, and relates to the technical field of integrated circuits. The memory detection method is applied to an integrated circuit device, the integrated circuit device comprises a memory, the memory comprises a plurality of preset memory partitions, and the method comprises the following steps: determining a current detection partition, wherein the current detection partition is one storage partition in a plurality of preset storage partitions; receiving an access command for a memory initiated by an access terminal; detecting the current detection partition; and in the process of starting the detection of the current detection partition and finishing the detection of the current detection partition, if the access command is the access command for the area outside the current detection partition of the memory, sending the access command to the memory. According to the technical scheme provided by the embodiment of the application, the current situation that the performance of the chip is influenced because the current memory can not be accessed continuously for a long time can be improved.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a memory detection method, an integrated circuit device, a storage medium, and a laser radar.
Background
The laser radar chip is a core component of the laser radar and is responsible for collecting, processing and transmitting all laser radar information, so that it is very important to ensure the functional safety of the laser radar chip in the whole life cycle and in the use process. The laser radar chip comprises a memory, and the real-time work of the laser radar enables the memory to be accessed with data frequently; to ensure that data access is performed smoothly, it is necessary to ensure that the storage area of the memory is valid, and therefore, it is necessary to detect the validity of the memory.
In the related technical scheme, an MBIST (Memory Build IN SELF TEST) technology is adopted to detect the Memory of the laser control chip. Specifically, a BIST unit circuit is added to the periphery of the memory circuit inside the memory, a test stimulus instruction to the memory is generated by the BIST unit circuit, and whether a failure area exists in the memory is determined according to the test result. After all areas of the memory are continuously detected and valid, the data access of the memory is performed; however, by the technical scheme, the laser radar chip memory can not be accessed continuously for a long time, and the performance of the laser radar chip is affected, so that the normal operation of the laser radar can be affected.
Disclosure of Invention
The embodiment of the application provides a memory detection method, a device, a storage medium and a laser radar, which are used for improving the current situation that the performance of a chip is influenced because the current memory can not be accessed continuously for a long time. The technical scheme is as follows:
In a first aspect, an embodiment of the present application provides a memory detection method, which is applied to an integrated circuit device, where the integrated circuit device includes a memory, and the memory includes a plurality of preset memory partitions, and the method includes:
determining a current detection partition, wherein the current detection partition is one of the plurality of preset storage partitions;
Receiving an access command for the memory initiated by an access terminal;
detecting the current detection partition;
And in the process of starting the detection of the current detection partition and finishing the detection of the current detection partition, if the access command is the access command for the area outside the current detection partition of the memory, sending the access command to the memory.
In a second aspect, an embodiment of the present application provides an integrated circuit device, the integrated circuit device including a memory, the memory including a plurality of preset memory partitions, the integrated circuit device further including:
A current detection partition determining unit, configured to determine a current detection partition, where the current detection partition is one of the plurality of preset storage partitions;
the address remapping unit is electrically connected with the memory, and is used for receiving an access command for the memory initiated by an access terminal, and sending the access command to the memory when the access command is an access command for an area outside the current detection partition of the memory in the process from the detection of the current detection partition to the completion of the detection of the current detection partition; and
And the MBIST unit is electrically connected with the memory and is used for detecting the current detection partition.
In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method described above.
In a fourth aspect, an embodiment of the present application provides a lidar, which may include: a processor, a memory, the memory divided into a plurality of memory partitions; wherein the memory stores a computer program adapted to be loaded by the processor to cause the lidar to perform the steps of the method described above.
The technical scheme provided by the embodiments of the application has the beneficial effects that at least:
the embodiment of the application divides the storage space of the memory into a plurality of storage partitions so that other storage partitions of the memory can be accessed in the process from the beginning of detection to the end of detection in one of the storage partitions, namely the current detection partition. In consideration of different specifications of memories, the access command and the test command may be performed at the same time or at different times in a front-back interleaving manner.
Compared with the mode of detecting the memory and then accessing the memory after the detection of the memory is finished in the related art, the memory detection method provided by the embodiment of the application can access the memory in the area outside the current detection partition between the detection start and the detection end; therefore, the application can improve the current situation that the current memory can not be accessed for a long time, so that the performance of the chip is affected.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic structure of an integrated circuit device provided according to a related art;
FIG. 2 illustrates a flow diagram of a memory detection method provided in accordance with some embodiments of the application;
FIG. 3 is a flow chart of a memory detection method according to other embodiments of the present application;
FIG. 4 illustrates a schematic diagram of an integrated circuit device provided in accordance with some embodiments of the application;
FIG. 5 illustrates a schematic diagram of an integrated circuit device provided in accordance with further embodiments of the present application;
FIG. 6 illustrates a schematic diagram of an integrated circuit device provided in accordance with further embodiments of the present application;
FIG. 7 illustrates a schematic structure of an integrated circuit device provided in accordance with further embodiments of the present application;
Fig. 8 shows a schematic structural diagram of a lidar according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
First, terms related to one or more embodiments of the present specification will be explained.
MBIST (Memory Build IN SELF TEST, memory built-in self test) technique: the automatic test is performed by using a BIST circuit specially designed in the chip, so that the embedded module with a complex circuit structure, such as the embedded memory, can be comprehensively tested. The MBIST circuit is used for arranging a circuit module for generating a test vector and a comparison module for detecting a test result in the chip, and sending the test result out of the chip through a test pin of the chip after the test is completed.
And (3) electric connection: the different components in the circuit structure are directly or indirectly connected through copper foil or lead and other physical circuits capable of transmitting electric signals.
The laser radar main control chip is a core component of the laser radar and is responsible for collecting, processing and transmitting laser radar information. Therefore, it is very important to ensure the functional safety of the laser radar main control chip in the use process. And the memory is used as an important component of the laser radar main control chip, and how to detect the failure of the memory in the use process of the laser radar main control chip is important to the functional safety of the laser radar. Moreover, since the lidar is operated in real time, the detection behavior of the memory is required to not affect the normal operation of the lidar.
Based on the above, the embodiment of the application provides a memory detection method, an integrated circuit device, a storage medium and a vehicle-mounted chip. According to the technical scheme of the embodiment of the application, the storage space of the memory is divided into a plurality of storage partitions, so that other storage partitions of the memory can be accessed in the process from the beginning of detection to the end of detection in one of the storage partitions, namely the current detection partition. In consideration of different specifications of memories, the access command and the test command may be performed at the same time or at different times in a front-back interleaving manner.
Compared with the mode of detecting the memory and then accessing the memory after the detection of the memory is finished in the related art, the memory detection method provided by the embodiment of the application can access the memory in the area outside the current detection partition between the detection start and the detection end; therefore, the application can improve the current situation that the current memory can not be accessed for a long time, so that the performance of the chip is affected.
The following describes in detail the technical scheme of the memory detection method according to the embodiment of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic structure of an integrated circuit device provided according to the related art.
As shown in fig. 1, the integrated circuit device includes MBIST module 110 and memory 120.MBIST module 110 is configured to detect a failure of memory 120.MBIST module 110 includes a test command generation circuit 112, a BIST control circuit 114, and a response analysis circuit 116, wherein test command generation circuit 112 is configured to generate test commands for testing memory 120 using a predetermined test algorithm, and the content of the test commands generated by the circuits implemented by different test algorithms is also different; the BIST control circuit 114 may be implemented by a state machine, the BIST control circuit 114 being used to control read and write operations to the memory 120; the response analysis circuit 116 may be implemented as a comparator, and the response analysis circuit 116 detects a failure of the memory 120 by comparing the actual response of the memory 120 to a known normal memory response.
It should be noted that, the integrated circuit device of the embodiment of the present application may be a vehicle-mounted Chip including a memory, for example, a vehicle-mounted laser radar Chip, or may be other suitable chips, for example, an MCU (MicroController Unit, micro control unit) Chip or an SoC (System on Chip) Chip, which is also within the scope of the embodiment of the present application.
Based on the application scenario shown in fig. 1, the following will describe in detail the memory detection method provided in the embodiment of the present disclosure with reference to fig. 2 to 3. It should be noted that the above application scenario is only shown for the convenience of understanding the spirit and principle of the present specification, and the embodiments of the present specification are not limited in this respect. Rather, embodiments of the present description may be applied to any scenario where applicable.
Fig. 2 is a flow chart illustrating a memory detection method according to some embodiments of the application. The memory detection method is applied to an integrated circuit device, wherein the integrated circuit device comprises a memory, and the memory comprises a plurality of preset memory partitions. That is, each memory partition is a subset of the memory space of the memory, and the size of each memory partition may or may not be identical. The memory detection method includes steps S210 to S240. The memory detection method in the exemplary embodiment will be described in detail with reference to the accompanying drawings.
Referring to fig. 2, in step S210, a current detection partition is determined, wherein the current detection partition is one of a plurality of preset memory partitions.
In an example embodiment, partition address information for a plurality of memory partitions of a memory of the integrated circuit device is obtained, and a current detected partition is selected from the plurality of memory partitions based on the partition address information. For example, the memory further includes a preset storage unit, where the preset storage unit is configured to store a segment of address information corresponding to each storage partition; the step S210 may include: and acquiring a section of address information from a preset storage unit so as to determine the storage partition corresponding to the address information as the current detection partition. Alternatively, the current detected partition may be selected from a plurality of memory partitions in the following two ways.
Mode one:
Sequentially selecting one section of address information of the memory from a preset memory unit according to the partition sequence of the memory partitions, and determining the memory partition corresponding to the selected address information as the current detection partition.
Mode two:
And selecting a section of address information corresponding to one of the undetected memory partitions from a preset memory unit according to the access frequency of each of the plurality of memory partitions, determining the memory partition corresponding to the selected address information as the current detection partition, for example, taking the remaining memory partition which is not detected and has the lowest access frequency as the current detection partition.
In step S220, an access command for a memory initiated by an access terminal is received.
In an example embodiment, the access terminal is the initiator of the memory access and the access terminal may be a MASTER unit, such as a processor unit, on the bus. The access command may be a data read command or a data write command for the memory, for example, if the access command is a data read command for the memory initiated by the processor unit, the integrated circuit device receives the data read command for the memory initiated by the processor unit.
In step S230, the current detection partition is detected.
In an example embodiment, a test command for a current detection partition of the memory is generated by using a predetermined detection algorithm, the memory is controlled to detect the current detection partition by the test command, an output result obtained by the detection is compared with an expected result, and whether the current detection partition fails or not is determined according to the comparison result. In this embodiment, the entire inspection process for the current inspection partition requires the testing of multiple test commands.
The predetermined detection algorithm may include MSCAN (Memory SCAN) algorithm, march algorithm, walking algorithm, etc., and may be other suitable detection algorithm, such as a skip algorithm, which is not limited in particular by the embodiment of the present application.
In step S240, in the process from the start of the detection of the current detection partition to the completion of the detection of the current detection partition, if the access command is an access command for an area outside the current detection partition of the memory, the access command is sent to the memory.
In an example embodiment, in a process from starting detection of a current detection partition to completing detection of the current detection partition, if an access command for a memory is received, determining whether the access command is an access command for an area outside the current detection partition of the memory; if the access command is an access command for an area outside the currently detected partition of the memory, the access command is sent to the memory. If the access command is an access command for a current detection partition of the memory, the access command cannot reach the current detection partition because the current detection region is the memory partition being detected; in particular by blocking or transmitting access commands to other devices.
According to the exemplary embodiment of fig. 2, the storage space of the memory is divided into a plurality of storage partitions, so that during one of the storage partitions, i.e. the current detection partition, from the beginning of the detection to the end of the detection, the other storage partitions of the memory can also be accessed. Considering that the specification forms of the memories are different, for example, the memories are multiported memories, the access command and the test command can be performed at the same time; for example, the memory is a memory accessed by a single port, the access command and the test command may be performed at different times in a front-to-back interleaving manner, and for example, a command merging unit connected to the port may be configured to receive the access command and the test command. Compared with the mode of detecting the memory and then accessing the memory after the detection of the memory is finished in the related art, the memory detection method provided by the embodiment of the application can access the memory in the area outside the current detection partition between the detection start and the detection end; therefore, the application can improve the current situation that the current memory can not be accessed for a long time, so that the performance of the chip is affected.
In some embodiments, the memory is a single communication port memory, such that if there is a test command for the current detected partition and an access command for an area outside the current detected partition, only two commands can be made to access the memory sequentially. In order to reduce the influence of the detection on the normal memory access as much as possible, the step S230 specifically includes a step S231 and a step S232. Step S231: it is determined whether the memory is in an idle state, wherein the idle state is a state in which the memory is not accessed. In this embodiment, whether the memory is accessed at this time is determined according to whether the integrated circuit device receives an access command initiated by the access terminal for an area of the memory outside the current detection partition; since the access command for the currently detected partition does not reach the memory, this is not considered here. Specifically, if an access command initiated by an access terminal for an area of the memory outside the current detection partition is received, determining that the memory is not in an idle state; if the access command initiated by the access terminal for the area of the memory outside the current detection partition is not received, determining that the memory is in an idle state. Step S232: if the memory is in an idle state, a test command is sent to the memory to test the current detection partition, wherein the access command is sent to the memory at a different time than the test command is sent to the memory. Since it can be determined that the current memory has no access command to access when the memory is in an idle state, the current detected partition can be detected. According to the embodiment, the idle state is judged firstly, then whether the access command accesses the memory is preferentially ensured by determining whether to perform detection or not, and meanwhile, the memory idle time is utilized for detection, so that two purposes are achieved.
Considering that the above detection method is actually a method of access priority and detection is performed once, there are cases where the detection time is too long but the detection process is still progressing slowly. To ameliorate this deficiency, the method further includes steps S250-S260. Step S250, obtaining the detection time length of the detection of the memory for the current round. In some embodiments, the integrated circuit device further comprises a timing unit; the timing unit is used for recording the duration from the last detection end to the current moment, in other words, the detection duration of the current round of detection on the memory. Step S260: and determining whether access of the access terminal to the memory is refused or not according to the number of the memory partitions which are currently detected and the detection time length. Specifically, the number of memory partitions currently completing detection and the detection duration can be referred to determine the speed of detection; for example, when the detection duration is long enough and the number of detections does not reach the number matching the detection duration, it may be determined that the current detection speed is too slow, and then the access to the memory by the access terminal may be denied, so as to ensure the progress of the detection process. In some embodiments, a first preset duration and a preset number may be set; the first preset duration is a time interval value smaller than the maximum detection time of the memory, wherein the maximum detection time refers to the maximum detection time value in the previous detection round, and the maximum detection time value can be the detection duration when the memory has faults or the detection duration when the memory has no faults; the preset number is then a positive integer value that is less than the number of memory partitions. If the detection time length is greater than or equal to the first preset time length and the number of the storage partitions which are currently detected is less than or equal to the preset number, the detection progress is slow, and the access of the access terminal to the area outside the current detection partition of the memory is further refused; otherwise, the detection progress is normal. In other embodiments, a second predetermined duration and predetermined number may also be set; the second preset duration is the maximum detection time value in the previous detection round or a preset value approximately equal to the time interval of the whole detection round. Wherein reference to "substantially equal" in this document means within 15% of each other. Based on the above, if the ratio of the detection duration to the second preset duration is greater than or equal to the preset ratio, and the number of the memory partitions currently completing detection is less than or equal to the preset number, the detection progress is slow, and the access of the access terminal to the area outside the current detection partition of the memory is further refused; otherwise, the detection progress is normal.
According to the technical scheme in the above-mentioned example embodiment, when the detection duration is long and the number of storage partitions that complete detection is small, the access priority is adjusted to the detection priority by rejecting the access of the access terminal to the memory, so that the memory detection efficiency can be improved.
Fig. 3 is a flow chart of a method for detecting a memory according to other embodiments of the present application, where an integrated circuit device includes the above-mentioned memory and another temporary redundant memory unit.
Referring to fig. 3, in step S310, a current detection zone is determined.
In the example embodiment, the implementation process and implementation effect of step S310 are similar to those of step S210, and are not described herein.
In step S320, the data of the current detection partition is migrated to the temporary redundant memory location.
In an example embodiment, before the step of detecting the current detection partition, data of the current detection partition is migrated to the temporary redundant storage unit, so that the current detection partition can be detected on the basis of ensuring data security of the current detection partition.
The memory and the temporary redundancy unit may be the same type of memory, for example, the memory and the temporary redundancy unit may be the same type of accessor of SRAM (Static Random Access Memory ). The memory and the temporary redundant memory unit may also be different types of memories, for example, the memory is an SRAM memory, and the temporary redundant memory unit is a DRAM (Random Access Memory ) memory.
It should be noted that although the memory and the temporary redundancy memory unit are described as a DRAM or SRAM memory, it should be understood by those skilled in the art that the memory and the temporary redundancy memory unit may be other suitable types of memories, such as SDRAM (Synchronous Dynamic Random Access Memory ), etc., which are also within the scope of the embodiments of the present application.
In step S330, an access command for a memory initiated by an access terminal is received.
In step S340, the current detection partition is detected.
In step S350, if the access command is an access command for an area other than the currently detected partition of the memory, the access command is sent to the memory.
In step S360, if the access command is an access command for the current detected partition, the access command is sent to the temporary redundant storage unit.
Thus, in the detection process of the current detection partition, not only the area outside the current detection partition can be accessed as described above, but also the current detection partition can be accessed by replacing the temporary redundant storage unit, and only the access to the memory is converted into the access to the temporary memory. Therefore, the memory detection method provided by the embodiment of the application has less influence on the memory access and the performance of the integrated circuit device. It should be noted that the temporary redundant memory unit is intended to temporarily store the data content of the current detection partition, and the size thereof is not necessarily the same as that of each memory partition, as long as the former is ensured to be larger than the latter.
In step S370, the data of the current detection partition is migrated from the temporary redundant memory unit back to the current detection partition.
In an example embodiment, after the step of detecting the current detection partition, the memory detection method further includes: the data of the current sense partition is migrated from the temporary redundant storage unit back to the current sense partition.
According to the technical solution in the exemplary embodiment of fig. 3, on the one hand, the memory is divided into a plurality of memory partitions to be detected, and each memory partition of the memory can be detected segment by segment; on the other hand, by setting the temporary redundant storage unit, the data corresponding to the current detection partition is copied to the temporary redundant storage unit, and the received access command for the current detection partition is sent to the temporary redundant storage unit, so that the access command for the current detection partition can be processed through the temporary redundant storage unit, and the failure of the memory can be detected in real time in the using process of the vehicle-mounted chip, and meanwhile, the performance of the vehicle-mounted chip is not influenced.
Fig. 4 illustrates a schematic structure of an integrated circuit device provided in accordance with some embodiments of the application.
Referring to fig. 4, in an exemplary embodiment, the integrated circuit device 400 includes a memory 405, the memory 405 including a plurality of preset memory partitions, the integrated circuit device 400 further including: a current detection partition determining unit 410, configured to determine a current detection partition, where the current detection partition is one of a plurality of preset storage partitions; an address remapping unit 415, electrically connected to the memory 405, and configured to receive an access command for the memory 405 initiated by the access terminal 402, and send the access command to the memory 405 when the access command is an access command for an area outside the current detection partition of the memory 405 in a process from starting detection of the current detection partition to completing detection of the current detection partition; and MBIST unit 420, electrically coupled to memory 405, for detecting a current detection partition.
According to the solution in the exemplary embodiment of fig. 4, the storage space of the memory is divided into a plurality of storage partitions, so that during one of the storage partitions, i.e. the current detection partition, from the beginning of the detection to the end of the detection, the other storage partitions of the memory can also be accessed. In consideration of different specifications of memories, the access command and the test command may be performed at the same time or at different times in a front-back interleaving manner. Compared with the mode of detecting the memory and then accessing the memory after the detection of the memory is finished in the related art, the memory detection method provided by the embodiment of the application can access the memory in the area outside the current detection partition between the detection start and the detection end; therefore, the application can improve the current situation that the current memory can not be accessed for a long time, so that the performance of the chip is affected.
Fig. 5 shows a schematic structural diagram of an integrated circuit device according to further embodiments of the present application.
Referring to fig. 5, in an example embodiment, integrated circuit device 400 further includes a temporary redundant storage unit 425 and a data migration unit 430. The data migration unit 430 is electrically connected to the memory 405 and the temporary redundant storage unit 425, respectively, and the data migration unit 430 is configured to migrate data of the current detection partition between the current detection partition and the temporary redundant storage unit 425; the address remapping unit 415 is further configured to send the access command to the temporary redundancy storage unit 425 when the access command is an access command for the currently detected partition.
According to the technical solution in the exemplary embodiment of fig. 5, before detecting the current detection partition, copying data corresponding to the current detection partition to a temporary redundant storage unit, in the process of detecting the current detection partition, an access command for the current detection partition is sent to the temporary redundant storage unit to access, and after the detection of the current detection partition is completed, moving the data of the current detection partition from the temporary redundant storage unit back to an address end corresponding to the current detection partition; therefore, the memory can be detected on the premise of not affecting the performance of the vehicle-mounted chip, and the functional safety of the vehicle-mounted chip is improved.
Fig. 6 illustrates a schematic structure of an integrated circuit device provided in accordance with further embodiments of the present application.
Referring to fig. 6, in an exemplary embodiment, the integrated circuit device 400 further includes a preset storage unit 435, where the preset storage unit 435 stores a piece of address information corresponding to each memory partition; the current detection partition determining unit 410 is configured to obtain a piece of address information from the preset storage unit 435, so as to determine a storage partition corresponding to the address information as the current detection partition. In an example embodiment, a memory is partitioned into a plurality of memory partitions at a predetermined granularity. The predetermined granularity may be one granularity level of a plurality of granularity levels, for example, the plurality of granularity levels may be 2kb, 4kb, 6kb, and 8kb, the predetermined granularity is determined from the plurality of granularity levels according to the processing performance of the on-vehicle chip, the memory 210 is divided into a plurality of memory partitions according to the predetermined granularity, for example, if the processing performance of the on-vehicle chip is higher, a higher granularity level is selected as the predetermined granularity level; if the processing performance of the vehicle-mounted chip is low, a low granularity level is selected as the preset granularity level.
According to the technical scheme in the above example embodiment, the memory is divided into a plurality of memory partitions to be detected according to the predetermined granularity, the selected current detection partition is detected, and the memory partition with the predetermined granularity can be selected according to the processing performance of the vehicle-mounted chip to detect, so that the influence of the memory detection on the performance of the vehicle-mounted chip can be reduced.
Furthermore, in an example embodiment, the integrated circuit device 400 further comprises the idle state determination unit;
The idle state judging unit is used for acquiring an access command sent by the access terminal so as to determine whether the memory is in an idle state according to the access command, wherein the idle state is a state when the memory is not accessed; the MBIST unit is electrically connected with the idle state unit and is used for sending a test command to the memory when the memory is in an idle state so as to test the current detection partition.
Further, in an example embodiment, the idle state judgment unit is connected with the address remapping unit; the idle state judging unit is used for judging whether the memory is in an idle state according to whether the address remapping unit currently receives an access command sent by the access terminal for an area outside the current detection partition.
According to the technical scheme in the above example embodiment, a test command for the current detection partition is generated, and when the memory is in an idle state, the test command is sent to the memory to test the current detection partition, so that the memory can be detected when the memory is in the idle state, and the influence on the performance of the vehicle-mounted chip can be further reduced.
Furthermore, in the example embodiment, integrated circuit device 400 further includes: the timing unit is used for acquiring the detection duration of the current wheel for the memory detection; the command blocking unit is used for rejecting the access of the access terminal to the memory when the detection duration is greater than or equal to a first preset duration and the number of the memory partitions which are currently detected is less than or equal to a preset number, or rejecting the access of the access terminal to the memory when the ratio of the detection duration to a second preset duration is greater than or equal to a preset ratio and the number of the memory partitions which are currently detected is less than or equal to a preset number; and the command merging unit is respectively and electrically connected with the command blocking unit, the MBIST unit and the memory so as to receive the access command or the detection command output by the MBIST unit and send the access command or the detection command to the memory.
According to the technical scheme in the above example embodiment, when the detection duration is long and the number of the storage partitions which are detected is small, the access terminal is refused to access the memory, so that the memory detection efficiency can be improved.
Fig. 7 illustrates a schematic structure of an integrated circuit device provided in accordance with further embodiments of the present application.
Referring to fig. 7, the integrated circuit device includes: the apparatus includes a preset storage unit 705, a timing unit 710, a current detection partition determination unit 715, an address remapping unit 725, a temporary redundancy storage unit 730, an idle state judgment unit 735, an MBIST unit 740, a command merging unit 745, a failure alarm unit 750, a data migration unit 755, and a memory 760.
The preset storage unit 705 is configured to store a block address segment of each test of the memory. For example, the memory, such as the on-chip memory partition, is divided according to the size of the temporary redundant memory unit 730, with the size of the memory space as a standard, until the entire memory is divided, and then address information of the divided memory partitions is stored in the preset memory unit 705. Before the integrated circuit device operates normally, address information of the divided partitions needs to be stored in the preset storage unit 705, and then the integrated circuit device can be started up normally. It should be noted that the temporary redundant memory unit is intended to temporarily store the data content of the current detection partition, and the size thereof is not necessarily the same as that of each memory partition, as long as the former is ensured to be larger than the latter.
The timing unit 710 is configured to obtain a detection duration of the current round for the memory detection, and output a feedback signal when a time from a last detection completion time is greater than a predetermined time threshold, for example, a maximum failure occurrence detection interval time, and the number of detected memory partitions is less than a preset number, so that the integrated circuit device denies access to the memory from the access terminal, and simultaneously starts a detection request for the memory, and sends request information to the current detection partition determining unit 715.
In an exemplary embodiment, the timing unit 710 is configured to record a duration from the last detection end to the current time, in other words, a detection duration of the current round of detection for the memory. And determining whether access of the access terminal to the memory is refused or not according to the number of the memory partitions which are currently detected and the detection time length. Specifically, the number of memory partitions currently completing detection and the detection duration can be referred to determine the speed of detection; for example, when the detection duration is long enough and the number of detections does not reach the number matching the cover detection duration, then the current detection speed may be determined to be too slow, and then the access of the access terminal to the memory may be denied, so as to ensure the progress of the detection process. In some embodiments, a first preset duration and a preset number may be set; the first preset duration is a time interval value smaller than the maximum detection time of the memory, wherein the maximum detection time refers to the maximum detection time value in the previous detection round, and the maximum detection time value can be the detection duration when the memory has faults or the detection duration when the memory has no faults; the preset number is then a positive integer value that is less than the number of memory partitions. If the detection time length is greater than or equal to the first preset time length and the number of the storage partitions which are currently detected is less than or equal to the preset number, the detection progress is slow, and the access of the access terminal to the area outside the current detection partition of the memory is further refused; otherwise, the detection progress is normal. In other embodiments, a second predetermined duration and predetermined number may also be set; the second preset duration is the maximum detection time value in the previous detection round or a preset value approximately equal to the time interval of the whole detection round. Based on the above, if the ratio of the detection duration to the second preset duration is greater than or equal to the preset ratio, and the number of the memory partitions currently completing detection is less than or equal to the preset number, then the detection progress is indicated to be slower, and the access terminal is further denied to access the area outside the current detection partition of the memory; otherwise, the detection progress is normal.
The current detection partition determining unit 715 is configured to, after receiving a detection request for the memory, sequentially detect each storage partition of the memory according to the partition order of the plurality of storage partitions.
For example, the current detection partition determination unit 715 supplies partition information of the current detection partition to the data migration unit 755, the address remapping unit 725, and the MBIST control unit 740.
The data migration unit 755 is configured to copy the received data in the address partition of the current detection partition to the temporary redundancy storage unit 730 before the detection starts, and to move the data of the temporary redundancy storage unit back to the current detection partition of the memory after the detection is completed. Then, the data replication of the address segment of the next memory partition is started, and the cycle is continued until the whole memory completes detection.
The address remapping unit 725 is configured to determine whether the access address of the current access command is in a test address segment of the current detection partition, and if the access address belongs to the test address segment, send the access command to the temporary redundancy storage unit 730.
MBIST unit 740 is configured to generate test commands, i.e., test stimulus data, for the address field of the currently detected partition, and determine whether the memory fails according to the response of the memory, and if so, report the failure to failure alarm unit 750.
Access port 725 is the initiator of the memory access, access port 725 may typically be a MASTER unit on the bus, such as a processor unit, and access port 725 sends the initiated memory access command to address remapping unit 725.
The idle state determining unit 735 is responsible for receiving the access command to the memory sent from the address remapping unit 725, determining whether there is an access action currently, if there is no access action, determining that the memory is in an idle state, and sending the idle state to the MBIST unit 740.
MBIST unit 740 is configured to generate test commands, i.e., test stimulus data, for the address field of the currently detected partition, and determine whether the memory fails based on the memory response. If the memory fails, a failure alarm unit 750 is reported. Further, the sending of the test command needs to determine whether the memory is currently in an idle state, and the test command is sent to the command merging unit 745 if the memory is in the idle state.
The command merging unit 745 is configured to merge the test command of MBIST and the access command of the access terminal, and send the merged access command to the memory 760.
According to the technical solution in the exemplary embodiment of fig. 7, on the one hand, the memory is divided into a plurality of memory partitions to be detected, and each memory partition of the memory can be detected segment by segment; on the other hand, by setting the temporary redundant storage unit, copying the data corresponding to the current detection partition to the temporary redundant storage unit, and sending the received access command for the current detection partition to the temporary redundant storage unit, the access command for the current detection partition can be processed through the temporary redundant storage unit, so that the failure of the memory can be detected in real time in the using process of the vehicle-mounted chip, and the performance of the vehicle-mounted chip is not influenced; on the other hand, compared with the mode of detecting the memory and then accessing the memory after the detection of the memory is finished in the related art, the memory detection method provided by the embodiment of the application can access the memory in the area outside the current detection partition between the detection start and the detection end; therefore, the present situation that the current memory is continuously unable to be accessed for a long time, so that the performance of the chip is affected can be improved.
It should be noted that, the memory detection method provided in the above embodiment and the integrated circuit device embodiment belong to the same concept, and the implementation process is detailed in the integrated circuit device embodiment, which is not repeated here.
It should be noted that, in the integrated circuit device provided in the foregoing embodiment, only the division of the foregoing functional modules is used as an example when executing the memory detection method, and in practical application, the foregoing functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the functions described above. The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of instructions, where the instructions are adapted to be loaded by a processor and execute the memory detection method according to the foregoing embodiment, and a specific execution process may refer to a specific description of the foregoing embodiment, which is not repeated herein.
The present application also provides a computer program product, where at least one instruction is stored, where the at least one instruction is loaded by the processor and executed by the processor, where a specific execution process may refer to a specific description of the foregoing embodiment, and a detailed description is omitted herein.
Referring to fig. 8, a schematic structural diagram of a lidar is provided in an embodiment of the present application. As shown in fig. 8, the lidar 800 may include: at least one processor 801 and a memory 802, the memory 802 being divided into a plurality of memory partitions.
Wherein the processor 801 may include one or more processing cores. The processor 801 connects various portions of the overall lidar 800 using various interfaces and lines, performs various functions of the lidar 800 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 802, and invoking data stored in the memory 802. Alternatively, the processor 801 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 801 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 801 and may be implemented on a single chip.
The Memory 802 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 802 includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). Memory 802 may be used to store instructions, programs, code, sets of codes, or instruction sets. The memory 802 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the storage data area may store data or the like referred to in the above respective method embodiments. The memory 802 may also optionally be at least one storage device located remotely from the aforementioned processor 801. As shown in fig. 8, an operating system, a network communication module, an input-output interface module, and a memory detection application program may be included in the memory 802, which is one type of computer storage medium.
In the lidar 800 shown in fig. 8, the processor 801 may be configured to invoke a memory detection application stored in the memory 802 to cause the lidar 800 to specifically perform the following operations:
determining a current detection partition, wherein the current detection partition is one of the plurality of preset storage partitions;
Receiving an access command for the memory initiated by an access terminal;
detecting the current detection partition;
And in the process of starting the detection of the current detection partition and finishing the detection of the current detection partition, if the access command is the access command for the area outside the current detection partition of the memory, sending the access command to the memory.
The foregoing is a schematic solution of a lidar according to an embodiment of the present specification. It should be noted that, the technical solution of the lidar and the technical solution of the integrated circuit device belong to the same concept, and details of the technical solution of the lidar, which are not described in detail, can be referred to the description of the technical solution of the integrated circuit device.
In addition, the application also provides a laser radar which comprises the integrated circuit device. By including the above-described integrated circuit device, it is also possible to improve the current situation that the memory is not currently accessible for a long time, so that the performance of the chip is affected.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it should be noted that, unless expressly specified and limited otherwise, "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. Furthermore, in the description of the present application, unless otherwise indicated, "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, or the like.
The foregoing disclosure is illustrative of the present application and is not to be construed as limiting the scope of the application, which is defined by the appended claims.
Claims (15)
1. A memory inspection method for an integrated circuit device, the integrated circuit device comprising a memory including a plurality of predetermined memory partitions, the method comprising:
determining a current detection partition, wherein the current detection partition is one of the plurality of preset storage partitions;
Receiving an access command for the memory initiated by an access terminal;
detecting the current detection partition;
And in the process of starting the detection of the current detection partition and finishing the detection of the current detection partition, if the access command is the access command for the area outside the current detection partition of the memory, sending the access command to the memory.
2. The method of claim 1, wherein the integrated circuit device further comprises a temporary redundant memory cell;
Before the step of detecting the current detection partition, the method further comprises: migrating the data of the current detection partition to the temporary redundant storage unit;
After the step of detecting the current detection partition, the method further comprises: and migrating the data of the current detection partition from the temporary redundant storage unit back to the current detection partition.
3. The method according to claim 2, wherein the method further comprises:
and if the access command is the access command for the current detection partition, sending the access command to the temporary redundant storage unit.
4. The method of claim 1, wherein the integrated circuit device includes a preset memory unit storing a piece of address information corresponding to each of the memory partitions;
the determining the current detection zone includes: and acquiring a section of address information from the preset storage unit so as to determine the storage partition corresponding to the address information as the current detection partition.
5. The method of claim 1, wherein detecting the current detection partition comprises:
Determining whether the memory is in an idle state, wherein the idle state is a state in which the memory is not accessed; and
And if the memory is in an idle state, sending a test command to the memory to test the current detection partition, wherein the sending of the access command to the memory and the sending of the test command to the memory are performed at different time.
6. The method of claim 5, wherein the determining whether the memory is in an idle state comprises:
If an access command initiated by the access terminal for the area of the memory outside the current detection partition is received, determining that the memory is not in an idle state; and
And if the access command initiated by the access terminal for the area of the memory outside the current detection partition is not received, determining that the memory is in an idle state.
7. The method according to claim 1, wherein the method further comprises:
Acquiring the detection time length of the detection of the memory by the round;
And if the detection time length is greater than or equal to a first preset time length and the number of the storage partitions which are currently detected is less than or equal to a preset number, rejecting the access of the access terminal to the area outside the current detection partition of the memory, or if the ratio of the detection time length to a second preset time length is greater than or equal to a preset ratio and the number of the storage partitions which are currently detected is less than or equal to a preset number, rejecting the access of the access terminal to the area outside the current detection partition of the memory.
8. An integrated circuit device comprising a memory, the memory comprising a plurality of preset memory partitions, the integrated circuit device further comprising:
A current detection partition determining unit, configured to determine a current detection partition, where the current detection partition is one of the plurality of preset storage partitions;
the address remapping unit is electrically connected with the memory, and is used for receiving an access command for the memory initiated by an access terminal, and sending the access command to the memory when the access command is an access command for an area outside the current detection partition of the memory in the process from the detection of the current detection partition to the completion of the detection of the current detection partition; and
And the MBIST unit is electrically connected with the memory and is used for detecting the current detection partition.
9. The integrated circuit device of claim 8, wherein the integrated circuit device further comprises:
a temporary redundant memory unit; and
The data migration unit is electrically connected with the memory and the temporary redundant storage unit respectively and is used for migrating the data of the current detection partition between the current detection partition and the temporary redundant storage unit;
the address remapping unit is further configured to send the access command to the temporary redundancy storage unit when the access command is an access command for the current detection partition.
10. The integrated circuit device of claim 9, further comprising a preset storage unit, wherein the preset storage unit stores a segment of address information corresponding to each of the memory partitions;
the current detection partition determining unit is used for acquiring a piece of address information from the preset storage unit so as to determine the storage partition corresponding to the address information as the current detection partition.
11. The integrated circuit device according to claim 8, further comprising the idle state determination unit;
The idle state judging unit is used for acquiring an access command sent by the access terminal to determine whether the memory is in an idle state according to the access command, wherein the idle state is a state when the memory is not accessed;
the MBIST unit is electrically connected with the idle state judging unit, and is used for sending a test command to the memory when the memory is in an idle state so as to test the current detection partition.
12. The integrated circuit device of claim 8, further comprising:
the timing unit is used for acquiring the detection duration of the current wheel for the memory detection; and
The command blocking unit is used for rejecting the access of the access terminal to the memory when the detection duration is greater than or equal to a first preset duration and the number of the memory partitions which are currently detected is less than or equal to a preset number, or rejecting the access of the access terminal to the memory when the ratio of the detection duration to a second preset duration is greater than or equal to a preset ratio and the number of the memory partitions which are currently detected is less than or equal to a preset number; and
And the command merging unit is respectively and electrically connected with the command blocking unit, the MBIST unit and the memory so as to receive the access command or the detection command output by the MBIST unit and send the access command or the detection command to the memory.
13. A computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the steps of the method according to any one of claims 1 to 7.
14. A lidar, comprising: a processor, a memory, the memory divided into a plurality of memory partitions; wherein the memory stores a computer program adapted to be loaded by the processor for causing the lidar to perform the steps of the method according to any of claims 1 to 7.
15. A lidar comprising an integrated circuit device according to any of claims 8 to 12.
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