CN118072776A

CN118072776A - Data transmission method, device, host and storage medium

Info

Publication number: CN118072776A
Application number: CN202410465951.XA
Authority: CN
Inventors: 杨琪凡; 耿万培
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2024-04-18
Filing date: 2024-04-18
Publication date: 2024-05-24

Abstract

The disclosure provides a data transmission method, a device, a host and a storage medium, wherein the data transmission method comprises the following steps: executing multiple data processing operations, and recording the identification of delay codes used by each data processing operation based on the execution result of each data processing operation; the identification comprises a zeroth identification which is used for identifying the delay code used by the data processing operation as available when the data processing operation is successfully executed, and a first identification which is used for identifying the delay code used by the data processing operation as unavailable when the data processing operation is failed to execute; when a plurality of continuous zeroth identifiers exist in the recorded identifiers, selecting the zeroth identifier from the plurality of continuous zeroth identifiers, and taking a delay code corresponding to the selected zeroth identifier as a target delay code; and executing the data processing operation by using the target delay code. By adopting the technical scheme, the stability in the data transmission processing process can be improved.

Description

Data transmission method, device, host and storage medium

Technical Field

Embodiments of the present disclosure relate to the field of communications technologies, and in particular, to a data transmission method, a data transmission device, a host, and a storage medium.

Background

With the rapid development of electronic information technology, multimedia data is increasing, and a storage system providing a larger storage capacity is becoming particularly important. The embedded memory has the characteristics of high integration, small volume, low power consumption, low cost and the like, and is widely applied to various storage scenes such as mobile equipment, consumer electronic products and the like; the embedded memory may include an embedded multimedia controller (eMMC), a secure digital card (SD), and the like.

For embedded memories, a clock signal is typically used to sample the data signal during the processing of the data transfer, where the stability of the clock signal determines the processing quality of the data transfer.

However, even the same embedded memory may have an influence on a clock signal due to a change in an operating environment (e.g., a change in a temperature of the operating environment, an operating voltage, etc.) due to an influence of process deviation, thereby failing to sample a data signal.

Under the background, how to provide a technical solution to improve the stability in the data transmission processing process is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of the above technical problems, the present disclosure provides a data transmission method, a device, a host, and a storage medium, which can improve stability in a data transmission process.

The present disclosure provides a data transmission method, including:

Executing multiple data processing operations, and recording the identification of delay codes used by each data processing operation based on the execution result of each data processing operation; the identification comprises a zeroth identification which is used for identifying the delay code used by the data processing operation as available when the data processing operation is successfully executed, and a first identification which is used for identifying the delay code used by the data processing operation as unavailable when the data processing operation is failed to execute;

when a plurality of continuous zeroth identifiers exist in the recorded identifiers, selecting the zeroth identifier from the plurality of continuous zeroth identifiers, and taking a delay code corresponding to the selected zeroth identifier as a target delay code;

And executing the data processing operation by using the target delay code.

Optionally, the data transmission method further includes:

According to the sequence of executing each time of data processing operation, sorting the recorded zeroth mark and the first mark to obtain a mark sequence table;

when a plurality of continuous zeroth identifiers exist in the identifiers of the record, selecting the zeroth identifier from the plurality of continuous zeroth identifiers, and taking a delay code corresponding to the selected zeroth identifier as a target delay code, wherein the method comprises the following steps:

determining a region with continuous zeroth marks in the mark sequence table;

Selecting a zeroth mark from the determined area, and sequentially recording the selected zeroth mark to obtain a corresponding selection window;

and taking the delay code corresponding to the zeroth identification positioned at the preset position of the selection window as a target delay code when each time of data processing operation is executed.

Optionally, the selection window is multiple;

The step of using the delay code corresponding to the zeroth identifier located at the preset position of the selection window as a target delay code when executing each time of data processing operation includes:

selecting the selected window with the largest number containing the zeroth mark from the selected windows as a target window;

and taking the delay code corresponding to the zeroth mark positioned at the preset position of the target window as the target delay code.

Optionally, before performing the step of determining that there is a region of consecutive zeroth identification in the identification sequence list, the method further comprises:

Judging whether the total number of the zeroth mark and the first mark contained in the mark sequence table is the same as the number of times of executing data processing operation, and executing the step of determining that at least a continuous zeroth mark area exists in the mark sequence table when the total number of the zeroth mark and the first mark is the same as the number of times of executing data processing operation; otherwise, continuing to record the identification of the delay code used by the subsequent data processing operation.

Optionally, the data processing operation comprises a data writing operation;

The identification sequence table comprises a zeroth identification corresponding to the successful execution of the data writing operation and a first identification corresponding to the failed execution of the data writing operation.

Optionally, the data processing operation comprises a data read operation;

The identification sequence table comprises a zeroth identification corresponding to the successful execution of the data reading operation and a first identification corresponding to the failed execution of the data reading operation.

Optionally, the data processing operation comprises a data writing operation;

The executing the multiple data processing operations, and based on the execution result of each data processing operation, recording the identification of the delay code used by each data processing operation, including:

carrying out time delay processing on the clock signal for a plurality of times according to the time delay time lengths corresponding to the time delay codes, wherein one time delay time length corresponding to one time delay code is used for carrying out time delay processing on the clock signal in one time data writing operation, and the time delay time lengths corresponding to the time delay codes are different;

After data writing operation is executed under each time of delay processing of a clock signal, verification information corresponding to each time of data writing operation is obtained, and the verification information is used for judging whether the data writing operation can be executed successfully or not;

And recording the identification of the delay code used by each data writing operation according to the verification information corresponding to each data writing operation.

Optionally, the recording the identifier of the delay code used by each data writing operation according to the verification information corresponding to each data writing operation includes:

For any data writing operation, when the check information corresponding to the data writing operation is determined to be the same as the preset check information, the identification of the delay code used by the data writing operation is recorded as a zeroth identification, and when the check information corresponding to the data writing operation is determined to be different from the preset check information, the identification of the delay code used by the data writing operation is recorded as a first identification.

Optionally, the performing the data processing operation using the target delay code includes:

And carrying out delay processing on the clock signal according to the delay time length corresponding to the target delay code so as to execute data writing operation.

Optionally, the data processing operation comprises a data read operation;

determining a transmission mode type for performing a plurality of data read operations;

Carrying out multiple time delay processing on the clock signals corresponding to the transmission mode type according to the time delay time lengths corresponding to the time delay codes, wherein one time delay time length corresponding to one time delay code is used for carrying out one time delay processing on the clock signals corresponding to the transmission mode type in one data reading operation, and the time delay time lengths corresponding to the time delay codes are different;

After executing data reading operation under each time delay processing of the clock signal corresponding to the transmission mode type, obtaining a reading result corresponding to each time of data reading operation, wherein the reading result is used for judging whether the data reading operation is successfully executed when the transmission mode type is adopted;

and recording the identification of the delay code used by each data reading operation according to the corresponding reading result of each data reading operation.

Optionally, the data read operation includes reading data stored in the first memory;

the determining a transmission mode type for performing a plurality of data read operations includes:

And determining the type of a transmission mode for executing data reading operation according to the data transmission rate for reading the data stored in the first memory.

Optionally, the determining a transmission mode type for performing a data read operation according to a data transmission rate for reading the data stored in the first memory includes:

when the data transmission rate of the data stored in the first memory is the same as the set rate, determining that the transmission mode type is a first transmission mode;

and determining the transmission mode type as a second transmission mode when the data transmission rate of the data stored in the first memory is different from the set rate.

Optionally, when determining that the transmission mode type is the first transmission mode, determining that a clock signal corresponding to the first transmission mode is a synchronous clock signal, where the synchronous clock signal is from a party providing read data;

And performing multiple time delay processing on the clock signal corresponding to the transmission mode type according to the time delay time lengths corresponding to the multiple time delay codes, wherein the time delay processing comprises the following steps:

And carrying out multiple time delay processing on the synchronous clock signal according to the time delay time lengths corresponding to the time delay codes, wherein one time of data reading operation uses the time delay time length corresponding to one time delay code to carry out one time delay processing on the synchronous clock signal, and the time delay time lengths corresponding to the time delay codes are different.

Optionally, when determining that the transmission mode type is the second transmission mode, determining that a clock signal corresponding to the second transmission mode is an initial clock signal, where the initial clock signal is an acquired original clock signal;

And carrying out delay processing on the initial clock signal for a plurality of times according to delay time lengths corresponding to the delay codes, wherein one time of data reading operation uses the delay time length corresponding to one delay code to carry out one time of delay processing on the initial clock signal, and the delay time lengths corresponding to the delay codes are different.

Optionally, after performing the data read operation under each time delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each time of data read operation includes:

for any one data read operation,

Judging whether a preset first sampling instruction is supported to be sent or not when the data stored in the first memory is read;

If so, executing data reading operation under the delay processing of the clock signal corresponding to the transmission mode type according to a preset first sampling instruction so as to obtain a reading result of the data reading operation related to the first sampling instruction;

otherwise, according to a preset second sampling instruction, executing data reading operation under the delay processing of the clock signal corresponding to the transmission mode type so as to obtain a reading result of the data reading operation related to the second sampling instruction.

Optionally, the data read operation is to read the data stored in the second memory;

and when the data stored in the second memory is determined to be read, determining that the transmission mode type is a third transmission mode.

Optionally, when determining that the transmission mode type is a third transmission mode, determining that a clock signal corresponding to the third transmission mode is an initial clock signal, where the initial clock signal is an acquired original clock signal;

Optionally, after performing the data read operation under each time delay processing on the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each time of data read operation includes:

for any one data read operation,

Judging whether a preset third sampling instruction is supported to be sent or not when the data stored in the second memory is read in a third transmission mode;

If so, executing data reading operation under the delay processing of an initial clock signal according to the preset third sampling instruction so as to obtain a reading result of the data reading operation related to the third sampling instruction;

Otherwise, according to a preset fourth sampling instruction, executing data reading operation under the delay processing of the initial clock signal so as to obtain a reading result of the data reading operation related to the fourth sampling instruction.

Optionally, recording the identification of the delay code used by each data reading operation according to the corresponding reading result of each data reading operation, including:

For any data reading operation, when the reading result is determined to be the same as the preset reading result, the delay code used for executing the data reading operation is recorded as a zeroth identifier, and when the reading result is determined to be different from the preset reading result, the delay code used for executing the data reading operation is recorded as a first identifier.

and carrying out delay processing on the clock signal corresponding to the transmission mode type according to the delay time length corresponding to the target delay code so as to execute data reading operation.

Correspondingly, the disclosure also provides a data transmission device, which comprises:

The first processing unit is configured to execute a plurality of data processing operations and record the identification of a delay code used by each data processing operation based on the execution result of each data processing operation; the identification comprises a zeroth identification which is used for identifying the delay code used by the data processing operation as available when the data processing operation is successfully executed, and a first identification which is used for identifying the delay code used by the data processing operation as unavailable when the data processing operation is failed to execute; according to the identification selection signal, taking the delay code corresponding to the selected zeroth identification as a target delay code, and executing the data processing operation;

and a second processing unit configured to select a zeroth identifier from the plurality of consecutive zeroth identifiers and generate a corresponding identifier selection signal including a delay code corresponding to the selected zeroth identifier when it is determined that there are a plurality of consecutive zeroth identifiers in the recorded identifiers.

Optionally, the data processing operation comprises a data writing operation;

The first processing unit includes:

The first delay module is configured to perform delay processing on the clock signal for a plurality of times according to delay time lengths corresponding to a plurality of delay codes, wherein one time of delay processing is performed on the clock signal by one time of delay time length corresponding to one delay code in one data writing operation, and the delay time lengths corresponding to the delay codes are different;

The first processing module is configured to acquire verification information corresponding to each data writing operation after executing the data writing operation under each time delay processing of the clock signal, wherein the verification information is used for judging whether the data writing operation can be successfully executed; and recording the identification of the delay code used by each data writing operation according to the verification information corresponding to each data writing operation.

Optionally, the first delay module includes: a plurality of first delays, a first logic operator, and a first selector, wherein:

The first delays are sequentially connected, wherein a first end of a first one of the first delays is suitable for inputting a clock signal, an output end of a last one of the first delays is connected with a first end of the first logic operator, and a second end of each of the first delays is connected with a second end of the first selector;

The first end of the first selector is suitable for inputting a first control signal, and generates a corresponding first selection signal according to the first control signal, wherein the first selection signal is used for controlling the number of first delayers which are used for starting a delay function when a data writing operation is executed;

The second end of the first logic operator is suitable for inputting a second control signal, and the output end of the first logic operator is suitable for outputting the clock signal after delay processing to the first processing module, wherein the second control signal is used for controlling the output time of the clock signal after delay processing.

Optionally, delay time lengths corresponding to the first delays are the same.

Optionally, the first processing unit further includes: and the mode selection module is coupled with the first delay module and is configured to respond to the mode selection signal to control the working state of the first delay module.

Optionally, the data processing operation comprises a data read operation;

The first processing unit includes:

A second processing module configured to determine a type of transmission mode for performing a plurality of data read operations; after executing data reading operation under each time delay processing of the clock signal corresponding to the transmission mode type, acquiring a reading result corresponding to each time of data reading operation, wherein the reading result is used for judging whether the data reading operation is successfully executed or not when the transmission mode type is adopted, and recording the identification of the delay code used by each time of data reading operation according to the reading result corresponding to each time of data reading operation;

And the second delay module is used for carrying out delay processing on the clock signals corresponding to the transmission mode type for a plurality of times according to delay time lengths corresponding to a plurality of delay codes, wherein one data reading operation uses the delay time length corresponding to one delay code to carry out delay processing on the clock signals corresponding to the transmission mode type for one time, and the delay time lengths corresponding to the delay codes are different.

Optionally, the second delay module includes a plurality of second delays, a second logic operator, and a second selector, wherein:

The second delays are sequentially connected, wherein a first end of a first second delay in the second delays is suitable for inputting a clock signal corresponding to the transmission mode type, an output end of a last second delay in the second delays is connected with a first end of the second logic operator, and a second end of each second delay in the second delays is connected with a second end of the second selector;

The first end of the second selector is suitable for inputting a third control signal, and generates a corresponding second selection signal according to the third control signal, wherein the second selection signal is used for controlling the number of second delayers which are used for starting a delay function when the data reading operation is executed;

The second end of the second logic operator is suitable for inputting a fourth control signal, and the output end of the second logic operator is suitable for outputting the clock signal corresponding to the transmission mode type after delay processing to the second processing module, wherein the fourth control signal is used for controlling the output time of the clock signal corresponding to the transmission mode type after delay processing.

The present disclosure also provides a host comprising: at least one processor and at least one memory storing one or more computer-executable instructions that are invoked by the processor to perform a data transmission method as described in any of the preceding examples.

The present disclosure also provides a host storage medium storing one or more computer-executable instructions that when executed implement a data transmission method as described in any of the preceding examples.

By adopting the data transmission scheme provided by the disclosure, based on the execution result of each data processing operation, the zero-th identifier used by the identifier can be recorded when the data processing operation is successfully executed, and the first identifier used by the identifier is unavailable when the data processing operation is failed to be executed, so that when a plurality of continuous zero-th identifiers exist in the recorded identifiers, the zero-th identifier can be selected from the identifiers, the delay code corresponding to the selected zero-th identifier is used as the target delay code, and the data processing operation can be executed based on the target delay code. Since the target delay code is determined from a plurality of continuous and available zeroth identifiers, that is, the target delay code is determined from delay codes used by a plurality of data processing operations which are successfully executed continuously, the zeroth identifiers are used for identifying and identifying the used delay codes as available when the data processing operations are successfully executed, and even if the target delay code is influenced by environmental factors, the target delay code is changed and still available, so that the stability in the data processing process can be improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic diagram of a data sampling;

FIG. 2 shows a schematic diagram of another data sampling;

FIG. 3 illustrates a flow chart of a data transmission method in an example of the present disclosure;

FIG. 4 illustrates a flow chart for determining a target delay code in an example of the present disclosure;

FIG. 5 illustrates a flow chart for determining a target delay code in an application scenario in an example of the present disclosure;

FIG. 6 illustrates a schematic diagram of a process for determining a target delay code in an example of the present disclosure;

FIG. 7 illustrates a flow chart for recording identification of a delay code used for a data write operation in an example of the present disclosure;

FIG. 8 illustrates a flow chart for determining target latency code for a data write operation in an application scenario in an example of the present disclosure;

FIG. 9 illustrates a flow chart for recording identification of a delay code used in a data read operation in an example of the present disclosure;

FIG. 10 illustrates a flow chart for obtaining a read result corresponding to a data read operation in an example of the present disclosure;

FIG. 11 illustrates a flow chart for determining target delay code for a data read operation in an application scenario in an example of the present disclosure;

FIG. 12 illustrates another flow chart for obtaining a read result corresponding to a data read operation in an example of the present disclosure;

FIG. 13 illustrates a flow chart for determining a target latency code for a data read operation in another application scenario in an example of the present disclosure;

Fig. 14 is a schematic diagram showing a structure of a data transmission apparatus in an example of the present disclosure;

Fig. 15 shows a specific structural diagram of a first processing unit in an example of the present disclosure.

Detailed Description

As described in the background art, when the working environment changes (such as a temperature rise and a small change in the working voltage), the clock signal is affected, which may result in that the data signal cannot be sampled.

For a better understanding of the existing schemes by those skilled in the art, the following is an example description in connection with one data processing scenario.

Referring to a schematic diagram of Data sampling shown in fig. 1, as shown in fig. 1, a waveform diagram corresponding to Clock signal and a waveform diagram corresponding to Data signal, which are time-varying, are shown, respectively.

As can be seen from fig. 1, when Clock jumps from low level to high level, data can be sampled to obtain sampling result.

For example, at time t2, clock jumps from low level to high level, while Data is at high level at this time, so that corresponding valid Data can be obtained; at time t4, clock jumps from low level to high level, data is at low level, and the acquired Data is invalid Data.

In the actual Data sampling process, the waveform of Clock will change with the influence of temperature change or other environmental factors, so that Clock is at the time of jumping from low level to high level, and Data cannot be sampled.

As an example, referring to another schematic diagram of Data sampling shown in fig. 2, as shown in fig. 2, the waveform of Clock changes due to interference of environmental factors, for example, the Clock and Data jump from low level to high level at the same time.

However, at times t1, t2, t3, t4, and t5 illustrated in fig. 2, data is in a low level and high level skip state, and it cannot be determined whether Data is in a low level or a high level, and thus a sampling result cannot be obtained according to Clock.

In order to solve the above technical problems, the present disclosure provides a data transmission scheme, based on the execution result of each data processing operation, capable of recording a zeroth identifier that is used for identifying an available delay code when the data processing operation is successfully executed, and a first identifier that is not used for identifying the delay code when the data processing operation is failed to be executed, further when a plurality of continuous zeroth identifiers exist in the recorded identifiers, the zeroth identifier can be selected from the first identifiers, and the delay code corresponding to the selected zeroth identifier is used as a target delay code, and further, based on the target delay code, the data processing operation can be executed.

By adopting the scheme, the target delay code is determined from a plurality of continuous and available zero-th identifiers, namely, the target delay code is determined from delay codes used by a plurality of continuous successful data processing operations, wherein the zero-th identifiers are used for identifying and identifying the used delay codes as available when the data processing operations are successfully executed, and even if the target delay code is changed due to the influence of environmental factors, the target delay code is still available, so that the stability in the data processing process can be improved.

In order for those skilled in the art to better understand the inventive concepts, principles and advantages of the disclosed examples, the following description is given of data transmission schemes in the embodiments of the present disclosure.

Referring to a flowchart of one data transmission method in the presently disclosed example shown in fig. 3, in some examples, as shown in fig. 3, the following steps may be performed:

S11, executing multiple data processing operations, and recording the identification of the delay code used by each data processing operation based on the execution result of each data processing operation.

Specifically, in the process of executing the data processing operation, the delay code is used, so that the execution result of each time of data processing operation after the delay processing can be obtained, and the identification of the delay code used by each time of data processing operation can be determined according to the obtained execution result.

In some examples, the identification of the delay code used by each data processing operation may be determined based on whether the data processing operation performed successfully.

For example, the identification may include a zeroth identification identifying that the delay code used by the data processing operation is available when the data processing operation is successfully executed, and a first identification identifying that the delay code used by the data processing operation is unavailable when the data processing operation is failed to execute.

Wherein, "success" in the examples of the present disclosure may refer to performing a data processing operation, capable of obtaining the same execution result as the set result; the "failure" in the examples of the present disclosure may mean that the data processing operation is performed, the execution result cannot be acquired, or the acquired execution result is different from the set result.

In some alternative examples, the data processing operations may include data write operations that may refer to writing data to a memory having a storage function and data read operations that may refer to reading data from a memory having a storage function.

In some alternative examples, the delay time duration corresponding to each delay code is different when performing the data processing operation.

S12, when a plurality of continuous zeroth identifiers exist in the recorded identifiers, selecting the zeroth identifier from the plurality of continuous zeroth identifiers, and taking the delay code corresponding to the selected zeroth identifier as a target delay code.

Specifically, the zeroth identifier may indicate that a delay code used by any data processing operation is available, and when a plurality of continuous zeroth identifiers exist, it is indicated that in the section of continuous interval, the delay code corresponding to the zeroth identifier is less affected by environmental factors (such as temperature, interference signals, voltage fluctuation and other factors), and even if the environmental factors change, the data processing operation can still be successfully executed, so that when the delay code corresponding to one of the plurality of continuous zeroth identifiers is used as the target delay code, the stability of the target delay code can be improved.

In some alternative examples, when it is determined that there are a plurality of consecutive zeroth identifiers, a delay code corresponding to the zeroth identifier at a preset position may be taken as the target delay code.

As an example, the preset position may refer to an intermediate position of a plurality of consecutive zeroth identification correspondence sections.

S13, executing the data processing operation by using the target delay code.

Specifically, by adopting steps S11 and S12, a target delay code less affected by environmental factors can be obtained, and further, subsequent data processing operations can be performed by using the target delay code, so as to improve stability in the data processing process.

In some alternative examples, subsequent data write operations may be performed using the target delay code.

In some alternative examples, subsequent data read operations may be performed using the target delay code.

By adopting the data transmission mode in the above example, the target delay code is determined from a plurality of continuous and available zeroth identifiers, and the zeroth identifier can represent that the delay code used by any data processing operation is available, even if the target delay code is influenced by environmental factors, the target delay code is changed, the change of the target delay code is smaller, and the target delay code is still available, so that the stability in the data processing process can be improved.

In order for those skilled in the art to better understand and practice the data transmission schemes in the examples of the present disclosure, the following description is provided by way of example with reference to the accompanying drawings.

In some embodiments, when the zero-th identifier for identifying the delay code used by the data processing operation is available and the first identifier for identifying the delay code used by the data processing operation is unavailable are recorded according to whether the data processing operation is successfully executed, a plurality of manners can be adopted, and the delay code corresponding to at least one zero-th identifier is taken as a target delay code.

In some examples, the delay code used is different when each data processing operation is performed, and further when it is determined that the data processing operation is performed successfully, the delay code corresponding to the zeroth recorded identifier is different. The target delay code is determined by the delay code corresponding to the zeroth identifier, so that the data processing operation sequence is executed, the position of the zeroth identifier in the recorded identifier is influenced, and the selection precision of the target delay code is further influenced.

As an alternative example, the zeroth identification and the first identification may be recorded according to the order in which the data processing operations are performed.

For example, the zeroth identifier and the first identifier of the record may be sorted according to the order in which the various data processing operations are performed, resulting in an identifier sequence table.

According to the sequence of each data processing operation, an identification sequence table with zeroth identifications and first identifications which are arranged in sequence can be obtained, the consistency of the data processing operation sequence and the identifications is improved, and the accuracy of the obtained target delay code can be improved.

In this application scenario, referring to a flowchart for determining a target delay code in one of the examples of the present disclosure shown in fig. 4, as an example, in some examples, as shown in fig. 4, the following steps may be performed:

S21, determining the area with continuous zeroth marks in the mark sequence table.

Specifically, when each data processing operation is executed, an identifier corresponding to the execution result is generated, and when a plurality of data processing operations are executed, a plurality of identifiers can be acquired. When the zeroth mark and the first mark are subjected to sorting processing according to the sequence of each data processing operation, the area where the zeroth mark exists in the mark sequence table can be determined by judging whether a plurality of continuous zeroth marks exist or not.

S22, selecting the zeroth mark from the determined area, and sequentially recording the selected zeroth mark to obtain a corresponding selection window.

Specifically, when it is determined that a region in which continuous zeroth identifiers exist in the identifier sequence table, all zeroth identifiers in the region can be extracted, and the zeroth identifiers are sequentially recorded according to the positions of the zeroth identifiers in the identifier sequence table, so that a selection window including zeroth identifiers arranged in sequence can be obtained.

S23, taking the delay code corresponding to the zeroth mark positioned at the preset position of the selection window as a target delay code when executing each data processing operation.

Specifically, with steps S21 and S22, a selection window including the zeroth identifier can be obtained, so that the identifier code corresponding to the zeroth identifier located at the preset position of the selection window can be used as the target delay code.

In some examples, the zeroth identification of the preset position of the selection window may refer to the zeroth identification of the middle position of the selection window.

In some other examples, selecting the zeroth identifier of the preset position of the window may select the zeroth identifier of any position of the window, which is not limited by the examples of this disclosure.

By adopting the scheme of the example, the delay code corresponding to the zeroth identification positioned at the preset position of the selection window is used as the target delay code for executing each data processing operation, when environmental factors change, even if the delay code corresponding to the zeroth identification changes (for example, the delay time length corresponding to the delay code increases or decreases), the delay time length of the delay code corresponding to the zeroth identification which changes is still in the selection window, and when the target delay code corresponding to the selected zeroth identification is used, the data processing operation can be successfully executed, so that the stability in the data processing process is further improved.

It should be noted that, in some examples, if the zeroth identifier does not exist in the identifier sequence table, the device performing the data processing operation or a connection line between the devices may be checked, or the data processing operation may be performed by reducing the frequency of data transmission for performing the data processing operation.

In some embodiments, when multiple data processing operations are performed, and in the manner shown in fig. 4, there may be only one or multiple selection windows formed, so that, according to the number of selection windows, different manners may be adopted, where a delay code corresponding to at least one zeroth identifier is used as a target delay code.

For example, when a selection window is obtained, the delay code of the zeroth mark located at the preset position (for example, the middle position) of the selection window can be directly used as the target delay code.

And when a plurality of selection windows exist, the target identification code can be selected from the selection window with the largest number of zeroth identifications.

As an example, referring to a flowchart for determining a target delay code in an application scenario in the example of the disclosure shown in fig. 5, as shown in fig. 5, the method may include the following steps:

S31, selecting the selected window with the largest number of the zeroth marks from the selected windows as a target window.

Specifically, the more the number of zeroth identifiers included in the selection window is, the smaller the delay code corresponding to the zeroth identifier in the selection window is affected by an environmental factor, the larger the change allowance of the delay code corresponding to each zeroth identifier is, even if the delay code corresponding to the zeroth identifier changes due to the change of the environmental factor (for example, the delay time length corresponding to the delay code increases or decreases), and when the delay code is taken as a target delay code, the data processing operation can still be successfully executed.

S32, taking the delay code corresponding to the zeroth mark positioned at the preset position of the target window as the target delay code.

In some examples, a delay code corresponding to a zeroth identifier located in a middle position of the target window may be used as the target delay code.

By taking the delay code of the zeroth mark positioned at the center of the target window as the target delay code, the target delay code has larger variation allowance, and the stability in the data processing process can be further improved.

When the target window has an even number of zeroth identifiers, the delay code corresponding to any one of the first identifiers located in the middle position may be used as the target delay code. For example, the delay code corresponding to the first identifier located at the intermediate position may be used as the target delay code.

In some examples, a delay code corresponding to a zeroth identifier located at an arbitrary position of the target window may be used as the target delay code.

To facilitate an understanding of the process of acquiring the target delay code through the selection window, the following description is given by way of example.

Referring to FIG. 6, a schematic diagram of a process for determining a target delay code is shown, as shown in FIG. 6, illustrating an identification sequence table formed according to the order in which 64 data processing operations are performed ：1,1,1,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0,0,0.

By judging that at least a continuous zeroth mark exists in the mark sequence table, and according to the sequence of executing data processing operation, 5 selection windows can be obtained, wherein the selection windows are respectively: [0, 0], [0,0,0,0,0,0,0,0,0,0], [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0], [0, 0].

By comparing the number of zeroth marks contained in the 5 selected windows, a target window can be obtained: [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] and the target window may include 25 zeroth marks "0", the delay code corresponding to the zeroth mark "0" of the 13 th bit (i.e., the zeroth mark "0" indicated by the dotted line box in fig. 6) of the target window may be used as the target delay code.

First, the number of zeroth identifiers and first identifiers included in the identifier sequence table illustrated in fig. 6 is illustrated, and may be determined according to the performed data processing operation; second, the symbols of the zeroth identifier "0" and the first identifier "1" are exemplary illustrations, and are used for illustrating that different symbols may be used to identify the execution result, and are not to be construed as limiting the present invention, for example, the symbol "a" may be used to represent the zeroth identifier and the symbol "B" may be used to represent the first identifier, which is not limited by the present disclosure; third, the representation forms of the identifier sequence table, the selection window and the target window are also illustrated by way of example, and are only used for illustrating that the zeroth identifier and the first identifier can be recorded by adopting the scheme in the example of the disclosure, and are not to be construed as limiting the invention.

In some examples of the present disclosure, the selecting window with the largest number of zeroth identifiers is used as the target window for selecting the target delay code, the number of zeroth identifiers directly affects the final selected target delay code, and the number of zeroth identifiers is related to the number of times of performing the data processing operation, so before the step of determining that at least the continuous zeroth identifier area exists, whether the total number of zeroth identifiers and the first identifiers contained in the identifier sequence table is the same as the number of times of performing the data processing operation can be further determined.

For example, the step of determining that at least a region of consecutive zeroth identifications exists in the identification sequence list is performed when it is determined that the total number of zeroth identifications and first identifications contained in the identification sequence list is the same as the number of times the data processing operation is performed.

Also for example, when it is determined that the total number of zeroth and first identifications included in the identification sequence table is different from the number of times the data processing operation is performed, the identification of the delay code used by the subsequent data processing operation is continuously recorded.

When the total number of the zeroth marks and the first marks contained in the mark sequence table is judged to be the same as the number of times of executing the data processing operation, the area for determining that at least the continuous zeroth marks exist in the mark sequence table is executed, the marks corresponding to all the data processing operation can be recorded and executed, the precision of the zeroth marks contained in each selection window can be further improved, and the precision of the acquired target delay code is improved.

In other examples, after the zeroth identifier for identifying the delay code used by the data processing operation is available and the first identifier for identifying the delay code used by the data processing operation is unavailable are recorded, any one of the zeroth identifier codes corresponding to the delay code may be selected as the target delay code, and the method for obtaining the target delay code is not limited by the examples disclosed herein.

In some examples of the present disclosure, data processing operations may be divided into data writing operations and data reading operations based on the direction of data transmission. When determining the type of data processing operation, the schemes in the above examples may be employed to obtain an identification sequence table and a target delay code corresponding to the data writing operation, and an identification sequence table and a target delay code corresponding to the data reading operation.

As an alternative example, the data processing operation may include a data write operation.

In this case, the tag sequence table may include a zeroth tag corresponding when the data read operation is successfully performed and a first tag corresponding when the data write operation is failed.

The delay code corresponding to the zeroth identifier located at the preset position of the selection window can be used as a target delay code when each time of data writing operation is executed.

As an alternative example, the data processing operation may include a data read operation.

In this case, the tag sequence table may include a zeroth tag corresponding when the data read operation is successfully performed and a first tag corresponding when the data read and write operation is failed.

The delay code corresponding to the zeroth identifier located at the preset position of the selection window can be used as a target delay code when each time of data read operation is executed.

In some examples of the present disclosure, different schemes may be employed to record the identity of the delay code used by each data processing operation based on the type of data processing operation.

As an example, the data processing operation may include a data write operation.

Accordingly, referring to a flowchart of an example of the present disclosure shown in fig. 7 for recording the identification of a delay code used for a data write operation, as shown in fig. 7, the following steps may be performed:

s41, carrying out time delay processing on the clock signal for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

In some examples, one data write operation uses one delay time length corresponding to one delay code to perform one delay processing on the clock signal, that is, the number of times the data write operation is performed and the number of times the clock signal is performed may be the same.

In some examples, the delay time duration corresponding to each delay code may be different to delay processing of different durations for each data write operation.

In some alternative examples, each data write operation may have a different delay duration by adjusting the number of devices with delay functions that are coupled to the clock signal transmission path.

S42, after the data writing operation is executed under each time delay processing of the clock signal, the verification information corresponding to each time of data writing operation is obtained.

Specifically, after the clock signal is delayed, a data write operation can be performed, data can be written into a memory having a memory function, and verification information for judging whether the data write operation can be successfully performed can be acquired.

In some examples, the type of verification information acquired may be the same for different types of memory.

For example, when the memory is an eMMC or SD, the check information corresponding to each data write operation may be cyclic redundancy check (Cyclic Redundancy Check, CRC) information.

In some examples, the type of verification information acquired may be different for different types of memory.

It should be noted that, the types of the verification information described in the foregoing schemes are illustrated for indicating that when the input write operation is performed on the memories of different types, the verification information corresponding to the input write operation can be used for verification to determine whether the data write operation is performed successfully, and the present invention is not limited by the description.

S43, according to the verification information corresponding to each data writing operation, recording the identification of the delay code used by each data writing operation.

Specifically, the execution result (for example, the successful execution of the data write operation or the failure execution of the data write operation) of each data write operation may be determined according to the verification information corresponding to each data write operation, and thus the identification of the delay code used by each data write operation may be determined.

For example, when it is determined that the data writing operation is successfully executed according to the verification information corresponding to each data writing operation, the identifier of the delay code used in the data writing operation may be recorded as the zeroth identifier "0"; or when the execution failure of the data writing operation is determined according to the verification information corresponding to each data writing operation, the identification of the delay code used by the data writing operation can be recorded as a first identification '1'.

The clock signal is subjected to one-time delay processing by using the delay time length corresponding to one delay code for one-time data writing operation, and the delay time lengths corresponding to the delay codes are different, so that the actual environment of the data writing operation can be simulated more truly, and the accuracy of the acquired verification information corresponding to each data writing operation is improved.

In some examples, the identification of the delay code used by each data write operation may be determined and recorded according to a relative relationship between the verification information corresponding to the data write operation and the preset verification information.

For example, for any one data writing operation, when it is determined that the check information corresponding to the data writing operation is the same as the preset check information, the identification of the delay code used for the data writing operation is recorded as the zeroth identification "0".

For another example, for any one data writing operation, when it is determined that the verification information corresponding to the data writing operation is different from the preset verification information, the identification of the delay code used for the data writing operation is recorded as the first identification "1".

In some examples, the preset verification information may be determined according to a communication protocol of each type of memory.

For example, when the memory is an eMMC, the preset check information may be "010", and when the check information corresponding to the parsed data write operation is "010", the identifier of the delay code used for the data write operation is recorded as the zeroth identifier "0"; otherwise, the identification of the delay code used for the data writing operation is recorded as a first identification "1".

For example, when the memory is the secure digital card SD, the preset check information may be "010", and when the check information corresponding to the data writing operation after the parsing process is "010", the identifier of the delay code used for the data writing operation is recorded as the zeroth identifier "0"; otherwise, the identification of the delay code used for the data writing operation is recorded as a first identification "1".

The process of recording the identification of the delay code used by each data writing operation can be determined and recorded by adopting the relative relation between the corresponding verification information and the preset verification information according to the data writing operation without manual processing, so that the efficiency and the accuracy of recording the identification of the delay code can be improved.

By adopting the scheme, the zero mark and the first mark of the record can be sequenced according to the sequence of executing each data writing operation, and then the selection window only comprising the zero mark can be determined. According to the number of the zeroth marks contained in the selection window, a target window for selecting a target delay code can be determined, the delay code corresponding to the zeroth mark positioned at the preset position of the target window is used as the target delay code, and further delay processing can be carried out on the clock signal according to the delay time length corresponding to the target delay code so as to execute data writing operation.

In some examples, when recording the identity of the delay code used by each data write operation, the available identity may be selected as the target delay code for performing the data write operation.

As an example, the following steps may be performed to determine a target delay code for performing a data write operation.

A1 According to the sequence of each data writing operation, a writing identification sequence table with a zeroth identification and a first identification which are arranged in sequence is obtained.

A2 Determining an area in the written identity sequence list where at least a consecutive zeroth identity is present.

A3 Selecting the zeroth mark from the determined area, and sequentially recording the zeroth mark to obtain a corresponding selection window.

A4 The delay code corresponding to the zeroth mark at the preset position of the selection window is used as the target delay code when each time of data writing operation is executed.

In some examples, when step A3) is performed, resulting in a plurality of selection windows, A4) may include:

a41 Selecting the most selected window with the zeroth mark from the plurality of selected windows as a target window.

A42 Taking the delay code corresponding to the zeroth mark positioned at the preset position of the target window as the target delay code.

In some examples, the delay code corresponding to the zeroth identifier located in the middle position of the target window may be used as the target delay code.

In some optional examples, before performing step A2), determining whether the total number of zeroth identifiers and first identifiers included in the written identifier sequence table is the same as the number of times of performing the data writing operation may also be performed, and performing step A2) when it is determined that the total number of zeroth identifiers and first identifiers included in the written identifier sequence table is the same as the number of times of performing the data writing operation; otherwise, continuing to record the identification of the delay code used by the subsequent data writing operation.

By adopting the mode, the target delay code corresponding to the data writing operation can be obtained, and further the data writing operation can be executed according to the delay time length corresponding to the target delay code.

In order to facilitate understanding and implementation of the scheme for determining the target delay code used for a data write operation, the following description is given by way of example with reference to the accompanying drawings.

Referring to the flowchart of determining the target delay code for a data write operation in an application scenario in the disclosed example shown in fig. 8, the following steps may be performed as shown in fig. 8:

s51, carrying out time delay processing on the clock signal for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

S52, after the data writing operation is executed under each time delay processing of the clock signal, verification information corresponding to each time of data writing operation is obtained.

S53, whether the verification information corresponding to the data writing operation is the same as the set verification information or not, if so, executing the step S54; if not, step S55 is executed.

S54, recording the zero-th mark which is used by the data writing operation and is used as the mark of the delay code.

S55, recording the identification of the delay code used by the data writing operation as the unavailable first identification.

S56, according to the sequence of executing each data writing operation, sorting the recorded zeroth mark and the first mark to obtain a writing mark sequence table.

S57, writing whether the total number of the identifiers in the identifier sequence table is the same as the number of times of executing the data writing operation, if so, executing the step S58; if not, go on to step S52.

Wherein the total number of identifications includes the number of first identifications and zeroth identifications.

S58, determining the area with continuous zeroth marks in the written mark sequence table.

S59, selecting the zeroth mark from the determined area, and sequentially recording the selected zeroth mark to obtain a corresponding selection window.

S60, selecting the most selected window containing the zeroth mark as a target window.

S61, taking the delay code corresponding to the zeroth mark positioned in the middle of the target window as the target delay code.

And S62, delaying the clock signal according to the delay time corresponding to the target delay code so as to execute the subsequent data writing operation.

The specific implementation of steps S51 to S62 may be referred to the foregoing examples.

It should be noted that, the above example is described by taking a case of having a plurality of selection windows as an example, if only one selection window is included, the delay code corresponding to the zeroth identifier in the middle position of the selection window may be directly used as the target delay code.

With the above-described scheme in the example, the target delay code for performing the subsequent data writing operation can be selected so that the data can be stably written in the memory having the memory function in writing, for example, the input is written in the first memory and the second memory.

In some examples, when the data processing operation comprises a data read operation, different operations may be performed on different types or different communication protocols of memory in determining the corresponding target delay code during the performance of the data read operation.

As an example, referring to a flowchart of an identification of a delay code used for recording a data read operation in the presently disclosed example shown in fig. 9, as shown in fig. 9, the following steps may be performed:

s71, a transmission mode type in which a plurality of data read operations are performed is determined.

In particular, when performing data read operations on different types of memory, the type of transfer mode employed may be different, and thus it is necessary to determine the type of transfer mode in which each data read operation is performed, in order to determine a processing scheme that is compatible with the type of transfer mode.

In some examples, the type of memory performing the current data read operation may be determined based on feedback of the memory to the operation command when performing the enumeration process.

S72, carrying out time delay processing on the clock signal corresponding to the transmission mode type for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

Specifically, when the data read operation is performed, the transmission mode type is different, and the clock signal for performing the delay processing is also different, so that the clock signal for performing the delay processing can be determined according to the transmission mode type.

In some examples, one data read operation uses one delay time length corresponding to one delay code to perform one delay processing on the clock signal corresponding to the transmission mode type, that is, the number of times the data read operation is performed is the same as the number of times the clock signal corresponding to the transmission mode type is performed.

In some examples, the delay time duration corresponding to each delay code may be different to delay processing of different durations for each data read operation.

In some alternative examples, the number of devices with delay functions on the access signal transmission path may be adjusted so that each data read operation has a different delay duration.

S73, after data reading operation is executed under each time delay processing of the clock signal corresponding to the transmission mode type, reading results corresponding to each time of data reading operation are obtained.

Specifically, after the clock signal corresponding to the transmission mode type is delayed, a data read operation can be performed, data can be read out from the memory having the memory function, and a read result for judging whether the data read operation was successfully performed when the current transmission mode type is present can be acquired.

In some examples, the type of read results obtained are different for different types of memory.

For example, when the memory is an eMMC, the read result corresponding to each data read operation may be a tuning sequence (tuning pattern) specified by a protocol related to eMMC; or the read result may be a value stored in a register (e.g., register ext_csd) in the multimedia controller eMMC.

For example, when the memory is a secure digital card SD, the read result corresponding to each data read operation may be a tuning sequence specified by a protocol associated with the secure digital card SD; or may be a value stored in a register (e.g., register CID) in the secure digital card SD.

It should be noted that, first, the type of the read result described in the foregoing scheme is illustrated, and is used to indicate that when performing the input read operation on different types of memories, the corresponding read result can be used to verify to determine whether the data read operation is performed successfully, and the present invention is not limited by the foregoing description; second, for different types of memories, the specific content of the tuning sequence corresponding to the different types of memories is determined according to a specific protocol when a data reading operation is performed.

S74, according to the corresponding reading result of each data reading operation, recording the identification of the delay code used by each data reading operation.

Specifically, the execution result of each data read operation (for example, the successful execution of the data read operation or the failure of the data read operation) may be determined according to the read result corresponding to each data read operation, and thus the identification of the delay code used by each data read operation may be determined.

For example, when it is determined that the data read operation is successfully executed according to the corresponding read result of each data read operation, the identifier of the delay code used in the data read operation may be recorded as the zeroth identifier "0"; or when the data read operation is determined to fail to be executed according to the verification information corresponding to each data read operation, the identification of the delay code used by the data read operation can be recorded as a first identification '1'.

The clock signal corresponding to the transmission mode type is subjected to one-time delay processing by using one delay time length corresponding to one delay code for one-time data reading operation, and the delay time lengths corresponding to the delay codes are different, so that the actual environment of the data reading operation can be simulated more truly, the accuracy of the obtained reading results corresponding to the data reading operations is improved, and the accuracy of the identification of the delay code used by each data reading operation is further improved.

In some implementations, the type of transfer mode in which each data read operation is performed may be determined based on the type of memory in which the data read operation is performed.

As an example, the data read operation may include reading data stored by the first memory.

In this application scenario, the type of transmission mode in which the data read operation is performed may be determined according to the data transmission rate at which the data stored in the first memory is read.

As an example, when the data transmission rate of reading the data stored in the first memory is the same as the set rate, the transmission mode type is determined to be the first transmission mode.

For example, if the first memory is an embedded multimedia controller eMMC, when it is determined that the data transmission rate when the data read operation is performed is 400MB/s, it may be determined that the transmission mode type is the first transmission mode HS400; upon determining that the data transfer rate at which the data read operation is performed is not 400MB/s, the transfer mode type may be determined to be the second transfer mode, e.g., HS200.

In some examples, when a particular type of transmission mode is determined, a clock signal to delay processing may be determined, and delay processing operations may be performed.

As an example, when the transmission mode type is determined to be the first transmission mode, a signal corresponding to the first transmission mode is determined to be a synchronizing clock signal, wherein the synchronizing clock signal may be from a party providing the read data.

For example, if the first transmission mode is HS400, the synchronizing clock signal may be a Data latch signal (DS) from the embedded multimedia controller eMMC.

Accordingly, performing the delay processing may include: and carrying out time delay processing on the synchronous clock signals for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

In some examples, one data read operation uses a delay time corresponding to one delay code to perform one delay processing on the synchronous clock signal, that is, the number of times the data read operation is performed is the same as the number of times the synchronous clock signal is performed.

In some examples, the delay times corresponding to the respective delay codes may be different to delay the synchronous clock signals used for the respective data read operations for different durations.

As an example, when the transmission mode type is determined to be the second transmission mode, a signal corresponding to the second transmission mode is determined to be an initial clock signal, where the initial clock signal may be the acquired original clock signal.

For example, if the second transmission mode is HS200, the initial clock signal may be an original clock signal obtained when performing a write operation on the embedded multimedia controller eMMC.

Accordingly, performing the delay processing may include: and carrying out multiple time delay processing on the initial clock signal according to the time delay time lengths corresponding to the time delay codes.

In some examples, one data read operation uses a delay time corresponding to one delay code to perform one delay processing on the initial clock signal, i.e., the number of times the data read operation is performed is the same as the number of times the initial clock signal is performed.

In some examples, the delay times corresponding to the respective delay codes may be different to delay the initial clock signal used for each data read operation for different durations.

In some embodiments, a data read operation may be performed after performing a delay process on a clock signal corresponding to a transmission mode type.

In some examples, during execution of a data read operation, different sampling instructions may be employed to obtain a corresponding read result of the data read operation.

As an example, referring to a flowchart for obtaining a read result corresponding to a data read operation in the example of the present disclosure shown in fig. 10, in some examples, as shown in fig. 10, the following steps may be performed:

S81, for any data reading operation, judging whether the transmission of a preset first sampling instruction is supported when the data stored in the first memory is read, if so, executing the step S82; otherwise, S83 is performed.

Specifically, in different transmission modes, different reading modes may be used to read the data stored in the first memory. Therefore, when any data reading operation is executed, whether the data stored in the first memory can be read through a preset first sampling instruction or not in the first transmission mode or the second transmission mode can be judged.

S82, executing data reading operation under the delay processing of the clock signal corresponding to the transmission mode type according to a preset first sampling instruction so as to obtain a reading result of the data reading operation related to the first sampling instruction;

Specifically, when the first transmission mode is determined, the data stored in the first memory can be read according to the preset first sampling instruction, the preset first sampling instruction can be sent to the first memory, and further after the synchronous clock signal is delayed, the data stored in the first memory can be read according to the preset first sampling instruction, so that a reading result of the data reading operation related to the first sampling instruction is obtained.

When the first transmission mode is determined to be in the second transmission mode, the data stored in the first memory can be read according to the preset first sampling instruction, the preset first sampling instruction can be sent to the first memory, and further after the initial clock signal is delayed, the data stored in the first memory can be read according to the preset first sampling instruction, so that a reading result of the data reading operation related to the first sampling instruction is obtained.

S83, according to a preset second sampling instruction, executing data reading operation under the delay processing of the clock signal corresponding to the transmission mode type so as to acquire the reading result of the data reading operation related to the second sampling instruction.

Specifically, when it is determined that the data stored in the first memory cannot be read according to the preset first sampling instruction in the first transmission mode, a preset second sampling instruction can be sent to the first memory, and further after the synchronization clock signal is delayed, the data stored in the first memory can be read according to the preset second sampling instruction, so that a reading result of the data reading operation related to the second sampling instruction is obtained.

When the first transmission mode is determined to be in the second transmission mode, the data stored in the first memory cannot be read according to the preset first sampling instruction, the preset second sampling instruction can be sent to the first memory, and further after the initial clock signal is delayed, the data stored in the first memory can be read according to the preset second sampling instruction, so that a reading result of the data reading operation related to the second sampling instruction is obtained.

In some examples, the types of the first sampling instruction and the second sampling instruction may be determined according to the type of memory.

For example, if the memory includes the embedded multimedia controller eMMC, the first sampling command may refer to CMD21, and the second sampling command may be another general-purpose reading command, such as CMD8.

By adopting the judging process, when any data reading operation is in the first transmission mode or the second transmission mode, different sampling instructions (such as the first sampling instruction and the second sampling instruction) are adopted to acquire the reading result of the data reading operation related to the sampling instructions, so that different transmission scenes can be suitable, and the universality of the data reading operation is improved.

In some examples, when the transmission mode type is determined, and the read result of the data read operation related to the first sampling instruction or the read result of the data read operation related to the second sampling instruction is obtained according to a preset first sampling instruction or a preset second sampling instruction, the read result may be compared with the preset read result, so that the specific identifier of the delay code used by each time of the data read operation may be determined.

In some examples, the identification of the delay code used by each data read operation may be determined and recorded according to a relative relationship between the corresponding read result and a preset read result.

For example, for any one data read operation, when it is determined that the read result corresponding to the data read operation is the same as the preset read result, the identification of the delay code used for the data read operation is recorded as the zeroth identification "0".

For another example, for any one data read operation, when it is determined that the read result corresponding to the data read operation is different from the preset read result, the identification of the delay code used for the data read operation is recorded as the first identification "1".

In some examples, the read results may be determined according to a communication protocol for each type of memory.

For example, when the memory is an eMMC of the embedded multimedia controller, the preset reading result may be a tuning sequence when the data stored in the eMMC is read by using the first sampling command.

When the read result corresponding to the data read operation is the tuning sequence after the analysis processing, the identification of the delay code used for executing the data read operation can be recorded as a zeroth identification '0'; otherwise, the identification of the delay code used to perform the data write operation is recorded as a first identification "1".

For example, when the memory is an eMMC of the embedded multimedia controller, the preset reading result may be a value stored in a register of the eMMC of the multimedia controller when the second sampling instruction is used to read the data stored in the eMMC.

When the read result corresponding to the data read operation is determined to be the value stored in the register after the analysis processing, the identifier of the delay code used for executing the data read operation can be recorded as a zeroth identifier "0"; otherwise, the identification of the delay code used to perform the data write operation is recorded as a first identification "1".

In some examples, when recording the identity of the delay code used by each data read operation, the available identity may be selected as the target delay code for performing the data read operation.

As an example, the following steps may be performed to determine the target delay code for performing a data read operation.

B1 According to the sequence of each data reading operation, a reading identification sequence table with zeroth identification and first identification which are arranged in sequence is obtained.

B2 Determining that at least a region of consecutive zeroth identifications exists in the read identification sequence list.

B3 Selecting the zeroth mark from the determined area, and sequentially recording the zeroth mark to obtain a corresponding selection window.

B4 The delay code corresponding to the zeroth mark at the preset position of the selection window is used as the target delay code when each time of data read operation is executed.

In some examples, when step B3) is performed, resulting in a plurality of selection windows, B4) may include:

B41 Selecting the most selected window with the zeroth mark from the plurality of selected windows as a target window.

B42 Taking the delay code corresponding to the zeroth mark positioned at the preset position of the target window as the target delay code.

In some optional examples, before performing step B2), determining whether the total number of zeroth identifiers and first identifiers included in the read identifier sequence table is the same as the number of times the data read operation is performed, and performing step B2) when it is determined that the total number of zeroth identifiers and first identifiers included in the read identifier sequence table is the same as the number of times the data read operation is performed; otherwise, continuing to record the identification of the delay code used by the subsequent data reading operation.

By adopting the mode, the target delay code corresponding to the data reading operation can be obtained, and further the data reading operation can be executed according to the delay time length corresponding to the target delay code.

In order to facilitate an understanding and implementation of the scheme for determining the target delay code to be used for performing a data read operation on the first memory, an example is described below with reference to the accompanying drawings.

Referring to the flowchart of determining the target delay code for a data write operation in an application scenario in the disclosed example shown in fig. 11, the following steps may be performed as shown in fig. 11:

s91, judging whether the data transmission rate and the set rate are the same when the data reading operation is executed; if yes, go to step S92; if not, go to step S94.

S92, determining the transmission mode type as a first transmission mode.

In some examples, the first transmission mode may refer to HS400.

S93, carrying out time delay processing on the synchronous clock signals for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

S94, determining the transmission mode type as a second transmission mode.

In some examples, the second transmission mode may refer to HS200, or a compatible MMC mode, a high SDR (SINGLE DATA RATE ) mode, and a high-speed DDR (Double Data Rate) mode.

S95, carrying out time delay processing on the initial clock signal for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

S96, for any data reading operation, judging whether to support sending a preset first sampling instruction when the data stored in the first memory is read, if so, executing a step 97; if not, go to step S98.

As an example, in the first transmission mode, the data stored in the first memory may be read to determine whether transmission of a preset first sampling instruction is supported when the data read operation is performed.

As an example, the data stored in the first memory may be read in the second transmission mode to determine whether transmission of a preset first sampling instruction is supported when performing a data read operation.

S97, a first sampling instruction is sent, data reading operation is executed under delay processing, and a reading result related to the first sampling instruction is obtained.

As an example, in the first transmission mode, the first sampling instruction may be sent to the first memory, and further, when the data reading operation is performed after the delay processing is performed on the synchronous clock signal, the reading result related to the first sampling instruction may be obtained.

As an example, in the second transmission mode, the first sampling instruction may be sent to the first memory, and further, when the data reading operation is performed after the delay processing is performed on the synchronous clock signal, the reading result related to the first sampling instruction may be obtained.

S98, sending a second sampling instruction, and executing data reading operation under delay processing to obtain a reading result related to the second sampling instruction.

As an example, in the first transmission mode, the second sampling instruction may be sent to the first memory, and further, when the data reading operation is performed after the delay processing is performed on the synchronous clock signal, the reading result related to the second sampling instruction may be obtained.

As an example, in the second transmission mode, the second sampling instruction may be sent to the first memory, and further, when the data reading operation is performed after the delay processing is performed on the synchronous clock signal, the reading result related to the second sampling instruction may be obtained.

S99, for any data reading operation, whether the reading result is the same as the preset reading result or not, if so, executing the step S100; if not, step S101 is performed.

As an example, in the first transmission mode, it may be determined whether the obtained read result related to the first sampling instruction is the same as the preset read result when the data read operation is performed; or in the first transmission mode, judging whether the acquired reading result related to the second sampling instruction is the same as the preset reading result or not when the data reading operation is executed.

As an example, in the second transmission mode, it may be determined whether the obtained read result related to the first sampling instruction is the same as the preset read result when the data read operation is performed; or in the second transmission mode, judging whether the acquired reading result related to the second sampling instruction is the same as the preset reading result or not when the data reading operation is executed.

S100, recording the zero-th mark which is used by the data reading operation and is used as the mark of the delay code.

As an example, an available zeroth identification corresponding to a delay code used to perform a data read operation in a first transmission mode may be recorded.

As an example, an available zeroth identification corresponding to a delay code used to perform a data read operation in the second transmission mode may be recorded.

S101, recording the identification of a delay code used by a data reading operation as a first unavailable identification.

As an example, a first identification corresponding to a delay code used to perform a data read operation in a first transmission mode may be recorded as unusable.

As an example, a corresponding unavailable first identification of a delay code used to perform a data read operation in a second transmission mode may be recorded.

S102, according to the sequence of executing each time of data reading operation, sorting the recorded zeroth mark and the first mark to obtain a reading mark sequence table.

As an example, a read identity sequence table corresponding to performing a data read operation in the first transmission mode may be recorded.

As an example, a read identity sequence table corresponding to performing a data read operation in the second transmission mode may be recorded.

S103, reading whether the total number of the identifiers in the identifier sequence table is the same as the number of times of executing data reading operation, if so, executing the step S104; if not, the step S97 is continued, or the step S98 is continued.

As an example, if the read identifier sequence table is acquired according to the first sampling instruction, step S97 is performed when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed.

As an example, if the read identifier sequence table is acquired according to the second sampling instruction, step S98 is performed when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed.

S104, determining the area with continuous zeroth marks in the reading mark sequence table.

S105, selecting the zeroth mark from the determined area, and sequentially recording the selected zeroth mark to obtain a corresponding selection window.

S106, selecting the most selected window containing the zeroth mark as a target window.

S107, taking the delay code corresponding to the zeroth mark positioned in the middle of the target window as the target delay code.

S108, delaying the clock signal according to the delay time corresponding to the target delay code so as to execute the subsequent data reading operation.

The specific implementation of steps S91 to S108 may be referred to the foregoing examples.

With the above-described scheme in the example, when the target delay code for performing the subsequent data read operation can be selected, data can be stably read from the memory having the memory function, for example, data can be read from the first memory.

As another example, the data read operation may include an operation to read data stored in the second memory.

The second memory and the first memory are memories of different types, and the second memory and the first memory perform data writing and reading processes according to different communication protocols.

In this application scenario, when it is determined to perform an operation of reading the data stored in the second memory, it may be determined that the transmission mode type is the third transmission mode.

In some examples, when a particular type of transmission mode is determined, a particular clock signal to delay processing may be determined, and delay processing may be performed.

As an example, when the transmission mode type is determined to be the third transmission mode, determining the clock signal corresponding to the third transmission mode as the initial clock signal, where the initial clock signal is the acquired original clock signal.

For example, if the third transmission mode is SDR104, the initial clock signal may be the original clock signal obtained when performing a write operation to secure digital card SD.

As an example, referring to another flowchart for obtaining a read result corresponding to a data read operation in the examples of the present disclosure shown in fig. 12, in some examples, as shown in fig. 12, the following steps may be performed:

S111, for any data reading operation, judging whether the transmission of a preset third sampling instruction is supported when the data stored in the second memory is read in a third transmission mode, if so, executing step S112; otherwise, S113 is performed.

Specifically, in different transmission modes, different reading modes may be used to read the data stored in the second memory. Therefore, when any data reading operation is executed, whether the data stored in the second memory can be read through a preset third sampling instruction in the third transmission mode can be judged.

S112, executing data reading operation under the delay processing of the initial clock signal according to the preset third sampling instruction, and executing the data reading operation to acquire the reading result of the data reading operation related to the third sampling instruction;

Specifically, when the data stored in the second memory is determined to be in the third transmission mode and the data stored in the second memory can be read according to a preset third sampling instruction, the preset third sampling instruction can be sent to the second memory, and further after the initial clock signal is delayed, the data stored in the second memory can be read according to the preset third sampling instruction, so that a reading result of the data reading operation related to the third sampling instruction is obtained.

S113, according to a preset fourth sampling instruction, performing data reading operation under the delay processing of an initial clock signal to obtain a reading result of the data reading operation related to the fourth sampling instruction.

Specifically, when it is determined that the data stored in the second memory cannot be read according to the preset third sampling instruction in the third transmission mode, a preset fourth sampling instruction may be sent to the second memory, and further after the initial clock signal is delayed, the data stored in the fourth memory may be read according to the preset fourth sampling instruction, so that a reading result of the data reading operation related to the fourth sampling instruction is obtained.

In some examples, the types of the third sampling instruction and the fourth sampling instruction may be determined according to the type of memory.

For example, if the memory includes a secure digital card SD, the third sample instruction may be CMD19 and the fourth sample instruction may be other general purpose read data instructions, such as CMD8.

By adopting the judging process, when any data reading operation is in the third transmission mode, different sampling instructions (such as a third sampling instruction and a fourth sampling instruction) are adopted to acquire the reading result of the data reading operation related to the sampling instruction, so that different transmission scenes can be suitable, and the universality of the data reading operation is improved.

In some examples, when the transmission mode type is determined, and the read result of the data read operation related to the third sampling instruction or the read result of the data read operation related to the fourth sampling instruction is obtained according to a preset third sampling instruction or fourth sampling instruction, the read result may be compared with the preset read result, so that the specific identifier of the delay code used by each time of the data read operation may be determined.

For example, when the memory is the secure digital card SD, the preset reading result may be a tuning sequence when the data stored in the secure digital card SD is read using the third sampling instruction.

After the analysis processing, when the reading result corresponding to the data reading operation is the tuning sequence, the identification of the delay code used for executing the data reading operation can be recorded as a zeroth identification '0'; otherwise, the identification of the delay code used to perform the data read operation is recorded as a first identification "1".

For another example, when the data stored in the secure digital card SD is read using the fourth sampling instruction, the preset read result may be a value stored in a memory (for example, a register CID) in the secure digital card SD.

After analysis processing, when the reading result corresponding to the data reading operation is a value stored in the memory, the identifier of the delay code used for executing the data reading operation can be recorded as a zeroth identifier '0'; otherwise, the identification of the delay code used to perform the data read operation is recorded as a first identification "1".

In some alternative examples, reference may be made to the foregoing description of selecting the target delay code when performing a data read operation on the first memory, and the description will not be repeated here.

In order to facilitate an understanding and implementation of the scheme for determining the target delay code to be used for performing a data read operation on the second memory, an example is described below with reference to the accompanying drawings.

Referring to a flowchart of determining a target delay code for a data read operation in another application scenario in the example of the present disclosure shown in fig. 13, as shown in fig. 13, the following steps may be performed:

s121, determining the transmission mode type as a third transmission mode.

In some examples, the third transmission mode may be SDR104, SDR50, and so on.

S122, carrying out time delay processing on the initial clock signal for a plurality of times according to the time delay time lengths corresponding to the time delay codes.

S123, for any data reading operation, judging whether the data stored in the second memory is supported to be sent or not when the data is read, if so, executing the step S124; if not, go to step S125.

S124, sending a third sampling instruction, and executing data reading operation under delay processing to obtain a reading result related to the third sampling instruction.

As an example, in the third transmission mode, the first sampling instruction may be sent to the second memory to obtain a read result related to the third sampling instruction when the data read operation is performed after the delay processing is performed on the initial clock signal.

And S125, sending a fourth sampling instruction, and executing data reading operation under delay processing to obtain a reading result related to the fourth sampling instruction.

As an example, in the third transmission mode, a fourth sampling instruction may be sent to the second memory to obtain a read result related to the fourth sampling instruction when the data read operation is performed after the delay processing is performed on the initial clock signal.

S126, for any data reading operation, whether the reading result is the same as the preset reading result or not, if so, executing step S127; if not, go to step S128.

As an example, in the third transmission mode, it is determined whether the obtained read result related to the third sampling instruction is the same as the preset read result when the data read operation is performed; or in the third transmission mode, judging whether the obtained reading result related to the fourth sampling instruction is the same as the preset reading result or not when the data reading operation is executed.

S127, recording the zero-th mark which is used by the data reading operation and is used as the mark of the delay code.

S128, recording the identification of the delay code used by the data reading operation as the unavailable first identification.

S129, according to the sequence of executing each time of data reading operation, sorting the recorded zeroth mark and the first mark to obtain a reading mark sequence table.

S130, reading whether the total number of the identifiers in the identifier sequence table is the same as the number of times of executing data reading operation, if so, executing step S131; if not, the step S124 is continued, or the step S125 is continued.

As an example, if the read identifier sequence table is acquired according to the third sampling instruction, step S124 is performed when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed.

As an example, if the read identifier sequence table is acquired according to the fourth sampling instruction, step S125 is performed when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed.

S131, determining the area with continuous zeroth identification in the identification sequence table.

S132, selecting a zeroth mark from the determined area, and sequentially recording the selected zeroth mark to obtain a corresponding selection window.

S133, selecting the most selected window containing the zeroth mark as a target window.

S134, taking the delay code corresponding to the zeroth mark positioned in the middle of the target window as the target delay code.

S135, delaying the clock signal according to the delay time corresponding to the target delay code so as to execute the subsequent data reading operation.

The specific implementation of steps S121 to S135 may be referred to the foregoing examples.

With the arrangement in the above example, when the target delay code for performing the subsequent data read operation can be selected, it is possible to stably read data from the memory having the storage function, for example, from the second memory.

It should be noted that, in the above examples, the first memory and the second memory are taken as examples to illustrate that the scheme of performing the data read operation is merely illustrative, and is used to illustrate that the target delay code for performing the data read operation may be acquired in different manners according to the type of the memory, which is not to be construed as limiting the present invention. In some examples, more types of memory may also be included.

By adopting the scheme in the example, the multiple time delay processing is executed, and the target time delay code for executing the data writing operation or the data reading operation can be selected from a plurality of continuous zeroth identifiers, so that the stability of data transmission in the data writing operation or the data reading operation can be improved.

In specific implementation, in a u-boot environment, after application test is performed by adopting the data transmission method in the disclosed example, data can be stably written and read in a temperature range of-40 ℃ to 125 ℃.

The disclosed examples also provide a data transmission device corresponding to the data transmission method, and the description is given below by way of example with reference to the accompanying drawings.

Referring to a schematic structural diagram of a data transmission apparatus in the example of the present disclosure shown in fig. 14, in some examples, as shown in fig. 14, the data transmission apparatus 100 may include: a first processing unit 110 and a second processing unit 120, wherein:

The first processing unit 110 is configured to perform a plurality of data processing operations, and record, based on the execution result of each data processing operation, an identification of a delay code used by each data processing operation; the identification comprises a zeroth identification which is used for identifying the delay code used by the data processing operation as available when the data processing operation is successfully executed, and a first identification which is used for identifying the delay code used by the data processing operation as unavailable when the data processing operation is failed to execute; according to the identification selection signal, taking the delay code corresponding to the selected zeroth identification as a target delay code, and executing the data processing operation;

The second processing unit 120 is configured to select, when it is determined that there are a plurality of consecutive zeroth identifiers among the recorded identifiers, a zeroth identifier from the plurality of consecutive zeroth identifiers, and generate a corresponding identifier selection signal including a delay code corresponding to the selected zeroth identifier.

With the data transmission apparatus 100 in the above example, based on the execution result of each data processing operation, the first processing unit 110 can record the zeroth identifier that is available for identifying the delay code used when the data processing operation is successfully executed, and when the data processing operation is failed to be executed, the delay code used for identifying the first identifier is unavailable, and further the second processing unit 120 can select the zeroth identifier from among the recorded identifiers when determining that there are a plurality of consecutive zeroth identifiers, and take the delay code corresponding to the selected zeroth identifier as the target delay code, and generate the corresponding identifier selection signal, and since the identifier selection signal can include the delay code corresponding to the selected zeroth identifier, the delay code corresponding to the selected zeroth identifier can be taken as the target delay code, so as to execute the data processing operation.

With the above-described data transmission apparatus 100, since the target delay code is determined from a plurality of consecutive and usable zeroth identifiers, that is, from delay codes used for a plurality of data processing operations that are successively executed successfully, the zeroth identifier is used to identify and usable the delay code used when the data processing operations are executed successfully, and even if the target delay code is changed due to the influence of environmental factors, the target delay code is usable, so that the stability in the data processing process can be improved.

In some examples of the present disclosure, data processing operations may be divided into data writing operations and data reading operations based on the direction of data transfer, and different execution logic may be employed in performing the respective data processing operations.

In some examples, the data processing operation may include a data write operation.

In this application scenario, referring to a specific structural schematic diagram of a first processing unit in the example of the disclosure shown in fig. 15, as shown in fig. 15, the first processing unit 110 may include: a first delay module 111 and a first processing module 112, wherein:

The first delay module 111 is configured to perform delay processing on the clock signal for multiple times according to delay time lengths corresponding to the delay codes, where one delay time length corresponding to one delay code is used for performing delay processing on the clock signal for one time in one data writing operation, and delay time lengths corresponding to the delay codes are different;

The first processing module 112 is configured to obtain verification information corresponding to each data writing operation after executing the data writing operation under each time delay processing of the clock signal, where the verification information is used to determine whether the data writing operation can be successfully executed; and recording the identification of the delay code used by each data writing operation according to the verification information corresponding to each data writing operation.

Specifically, the first delay module 111 may perform delay processing according to a delay duration corresponding to the delay code, so that data writing operation may be performed, and for any data writing operation, a check signal corresponding to the data writing operation may be obtained.

In some examples, the first processing module 112 may record the identification of the delay code used by the data write operation as a zeroth identification "0" when it is determined that the verification information corresponding to the data write operation is the same as the preset verification information.

In some examples, the first processing module 112 may record the identification of the delay code used by the data write operation as the first identification "1" when it is determined that the verification information corresponding to the data write operation is different from the preset verification information.

In some alternative examples, delay modules having different structures may be employed to implement delay processing of clock signals.

As an example, with continued reference to fig. 15, the first delay module 111 may include a plurality of first delays (e.g., first delays Dl0, dl1, …, dln illustrated in fig. 15, where n is an integer greater than 1), a first logic operator Lg1, and a first selector SC1, where:

The first delays are sequentially connected, for example, the first delays Dl0, dl1, …, dln may be connected in series, where:

The first end of a first one Dl0 of the first delays may be input with a clock signal dl_in, the output end of a last one Dln of the first delays may be connected with the first end of the first logic operator Lg1, and the second end of each first delay of the first delays is connected with the second end of the first selector SC 1.

As an example, the second end of the first delayer Dl0 may be connected to the second end of the first selector SC1, the second end of the first delayer Dl1 may be connected to the second end of the first selector SC1, …, and the second end of the first delayer Dln may be connected to the second end of the first selector SC 1.

Referring next to fig. 15, a first terminal of the first selector SC1 may input a first control signal dl_sel, and generate a corresponding first selection signal for controlling the number of first delays for selecting a start-up delay function when performing a data write operation according to the first control signal dl_sel.

Specifically, the clock signal may be transmitted to the first processing module 112 through each first delay device, where each first delay device only plays a role in data transmission. In response to the first control signal, the first selector SC1 may select to turn on a delay function of at least one of the first delays Dl0 to Dln, so that a delay time period of the clock signal dl_in may be changed.

For example, in response to the first control signal dl_sel, the first selector SC1 may generate the first selection signal del0, so that a delay function of the first delay Dl0 may be turned on; in response to the first control signal dl_sel, the first selector SC1 may generate the first selection signal deln so that the delay function of all the first delays Dl0 may be turned on.

In some alternative examples, the first control signal dl_sel may be obtained from the first processing module, or may be obtained from other devices having logic processing capabilities, for example, from a central processor. The disclosed examples do not impose any limitation on the source of the first control signal.

The second end of the first logic operator Lg1 may input a second control signal dl_update, and the output end thereof is adapted to output the clock signal after delay processing to the first processing module 112, where the second control signal dl_update may be used to control the output timing of the clock signal after delay processing.

For example, after determining to perform the delay processing once, the second control signal outputs a corresponding clock signal to the first processing module.

That is, by setting the state of the second control signal (for example, the level corresponding to the second control signal is a low level), the output channel of the first logic operator is closed in the process of performing the delay processing on the clock signal; after the delay processing of the clock signal is determined, the output channel of the first logic operator is opened by setting the state of the second control signal (for example, the level corresponding to the second control signal is high level), so that the clock signal after the delay processing is transmitted to the first processing module, and normal data writing operation is realized.

In some examples, the first logic operator may include an and logic gate. In some examples, the second control signal may be obtained from the first processing module, or from other devices having logic processing capabilities, e.g., from a central processor. The disclosed examples do not impose any limitation on the source of the second control signal.

In some alternative examples, for some application scenarios with lower transmission rates, the frequency of the clock signal is smaller and less affected by environmental factors, and the data writing operation may be performed directly according to the clock signal.

Based on this, with continued reference to fig. 15, the first processing unit 110 may further include a mode selection module 113, wherein the mode selection module 113 may be coupled with the first delay module 111 (e.g., the mode selection module 113 may be connected with the first delay dl 0) and configured to control an operation state of the first delay module 111 in response to the mode selection signal pass_en.

More specifically, by the mode selection signal pass_en, whether or not the first delay block 111 is used to delay the clock signal dl_in can be controlled.

For example, when the mode selection signal pass_en is high level "1", delay processing of the clock signal dl_in is unnecessary; for another example, when the mode selection signal pass_en is at a low level "0", the number of the first delays for turning on the delay function can be selected by the first control signal dl_sel to perform delay processing on the clock signal dl_in for different durations.

It should be noted that, when the first processing unit further includes a mode selection module, the mode selection module plays a role in delay, but the delay time corresponding to the mode selection module is far less than the delay time of each first delayer, so in some examples, the delay time of the mode selection module may be ignored.

In some optional examples, the delay time duration corresponding to each of the first delays is the same. Namely, when different numbers of first delayers with delay functions are connected to the delay path, the corresponding delay time length can be sequentially increased.

In some other optional examples, the delay time duration corresponding to each of the first delays may be the same.

In some examples, after delaying the clock signal, a data write operation may be performed, and the target delay code may be obtained, where the manner in which the target delay code for performing the data write operation is obtained may be referred to in the foregoing examples, which are not described herein.

In some examples, the data processing operation may include a data read operation.

In some embodiments, when the data processing operation comprises a data read operation, different operations may be performed on different types or different communication protocols of memories in determining the corresponding target delay code during the performance of the data read operation.

In this application scenario, the first processing unit may include:

Specifically, the second processing module may determine a type of transmission mode for performing the data read operation multiple times, and different types of transmission modes, where types of clock signals corresponding to the types of transmission modes are different, so that the second delay module may perform delay processing on signals corresponding to the types of transmission modes according to delay durations corresponding to the delay codes, and may further perform the data read operation. And for any data reading operation, the corresponding reading result can be obtained, and because the reading result can be used for judging whether the data reading operation is successfully executed when the current transmission mode type is adopted, the second processing module can record the identification of the delay code used by each data reading operation according to the reading result corresponding to each data reading operation.

In some examples, the second processing module may record the identifier of the delay code used by the data read operation as a zeroth identifier "0" when it is determined that the read result corresponding to the data read operation is the same as the preset read result.

In some examples, the second processing module may record the identification of the delay code used by the data read operation as the first identification "1" when the read result corresponding to the data read operation is different from the preset read result.

As an example, the second delay module may include a plurality of second delays, a second logic operator, and a first selector, wherein:

The plurality of second time delays are sequentially connected, for example, a series connection manner may be adopted between the plurality of second time delays, wherein:

the first end of a first second delayer of the second delayers is suitable for inputting a clock signal corresponding to the transmission mode type, the output end of the last second delayer of the second delayers is connected with the first end of the second logic operator, and the second end of each second delayer of the second delayers is connected with the second end of the second selector.

As an example, the connection relationship between each second delay device and the second selector may be referred to the description of the first delay module, which is not described herein.

In some examples, the first end of the second selector inputs a third control signal, and generates a corresponding second selection signal according to the third control signal, where the second selection signal is used to control the number of second delays that are used to turn on the delay function when performing the data read operation.

Specifically, the clock signal corresponding to the transmission mode type may be transmitted to the second processing module through each second delay device, where each second delay device only plays a role of data transmission. In response to the second control signal, the second selector may select to turn on a delay function of at least one of the plurality of second delays, so that a delay period of the clock signal corresponding to the transmission mode type may be changed.

For example, in response to the third control signal, the second selector may generate a second selection signal to turn on the delay function of the first second delay; or in response to the third control signal, the second selector may generate a second selection signal to turn on the delay functions of all the second delays.

In some alternative examples, the third control signal may be obtained from the second processing module, or from another device having logic processing capabilities, e.g., from a central processor. The disclosed examples do not impose any limitation on the source of the third control signal.

The second end of the second logic operator may input a fourth control signal, and the output end of the second logic operator may output the clock signal corresponding to the transmission mode type after delay processing to the second processing module, where the fourth control signal may be used to control the output timing of the clock signal corresponding to the transmission mode type after delay processing.

For example, by the fourth control signal, after determining to perform the delay processing once, the clock signal corresponding to the transmission mode type after the delay processing is output to the second processing module.

Specifically, by setting the state of the fourth control signal, the output channel of the second logic operator is closed in the process of performing delay processing on the clock signal corresponding to the transmission mode type; after the delay processing of the clock signal corresponding to the transmission mode type is determined, the output channel of the second logic operator is started by setting the state of the fourth control signal so as to transmit the clock signal corresponding to the transmission mode type after the delay processing to the second processing module, so that normal reading operation is realized.

In some examples, the second logic operator may include an and logic gate. In some examples, the fourth control signal may be obtained from the second processing module, or from other devices having logic processing capabilities, e.g., from a central processor. The disclosed examples do not impose any limitation on the source of the fourth control signal.

In some alternative examples, for some application scenarios with lower transmission rates, the frequency of the clock signal is smaller and less affected by environmental factors, and the data read operation may be performed directly from the clock signal.

Based thereon, the second processing unit may further comprise a mode selection module, wherein the mode selection module may be coupled to the second delay module (e.g., the mode selection module may be connected to the first second delay) and configured to control an operating state of the second delay module in response to the mode selection signal.

More specifically, by the mode selection signal, it is possible to control whether or not the clock signal corresponding to the transmission mode type is delayed by the second delay module.

For example, when the level corresponding to the mode selection signal is high level "1", it is unnecessary to perform delay processing on the clock signal corresponding to the transmission mode type; for another example, when the level corresponding to the mode selection signal is "0" with a low level, the number of second delayers for turning on the delay function may be selected by the third control signal, so as to perform delay processing with different durations on the clock signal corresponding to the transmission mode type.

In some optional examples, the delay time duration corresponding to each of the second delays is the same. Namely, when different numbers of second delayers with delay functions are connected to the delay paths, the corresponding delay time length can be sequentially increased.

In some other optional examples, the delay time duration corresponding to each of the second delays may be the same.

In some examples, after delaying the clock signal corresponding to the transmission mode type, a data read operation may be performed, and then a target delay code may be obtained, where a manner of obtaining the target delay code for performing the data read operation may be referred to the foregoing examples, which are not described herein.

The present disclosure also provides a host that may include at least one processor and at least one memory, the memory and the processor being communicable via a communication bus; the memory stores computer instructions capable of running on the processor, and when the processor invokes the one or more computer executable instructions, the data transmission method described in any of the above embodiments may be executed, and details thereof may be referred to above and will not be described herein.

In particular implementations, the processor may include a Central Processing Unit (CPU), a Field Programmable Gate Array (FPGA), or the like.

The Memory may include random access Memory (Random Access Memory, RAM), read-Only Memory (ROM), non-Volatile Memory (NVM), and the like. In particular implementations, the computer instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

The present invention also provides a storage medium storing one or more computer executable instructions, where the one or more computer executable instructions may implement the data transmission method described in any of the foregoing embodiments, and specific reference may be made to the foregoing related content, which is not repeated herein.

Wherein the computer-readable storage medium may include any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium, and/or storage unit. Such as memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, compact Disk Read Only Memory (CDROM), compact disk recordable (CD-R), compact disk Rewriteable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disks (DVDs), a tape, a cassette, or the like.

Moreover, computer instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, and the like, implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

Although the examples of the present disclosure are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A data transmission method, comprising:

And executing the data processing operation by using the target delay code.

2. The data transmission method according to claim 1, further comprising:

determining a region with continuous zeroth marks in the mark sequence table;

3. The data transmission method according to claim 2, wherein the selection window is a plurality of;

4. A data transmission method according to claim 2 or 3, characterized in that before performing the step of determining that there is a region of consecutive zeroth identity in the identity sequence list, further comprising:

Judging whether the total number of the zeroth mark and the first mark contained in the mark sequence table is the same as the number of times of executing data processing operation, and executing the step of determining that a continuous zeroth mark area exists in the mark sequence table when the total number of the zeroth mark and the first mark is the same as the number of times of executing data processing operation; otherwise, continuing to record the identification of the delay code used by the subsequent data processing operation.

5. A data transmission method according to claim 2 or 3, wherein the data processing operation comprises a data writing operation;

6. A data transmission method according to claim 2 or 3, wherein the data processing operation comprises a data read operation;

7. The data transmission method of claim 5, wherein the data processing operation comprises a data write operation;

8. The data transmission method according to claim 7, wherein recording the identification of the delay code used by each data write operation according to the verification information corresponding to each data write operation includes:

9. The data transmission method according to claim 7 or 8, wherein the performing the data processing operation using the target delay code comprises:

10. The data transmission method of claim 6, wherein the data processing operation comprises a data read operation;

11. The data transfer method of claim 10, wherein the data read operation comprises reading data stored in the first memory;

12. The data transmission method according to claim 11, wherein the determining a transmission mode type for performing a data read operation according to a data transmission rate for reading the data stored in the first memory includes:

13. The data transmission method according to claim 12, wherein when determining that the transmission mode type is the first transmission mode, determining that a clock signal corresponding to the first transmission mode is a synchronous clock signal from a party providing read data;

14. The data transmission method according to claim 12, wherein when determining that the transmission mode type is the second transmission mode, determining that a clock signal corresponding to the second transmission mode is an initial clock signal, the initial clock signal being the acquired original clock signal;

15. The data transmission method according to any one of claims 12 to 14, wherein after performing data read operations under each time delay processing of a clock signal corresponding to the transmission mode type, obtaining read results corresponding to each time of the data read operations, includes:

Judging whether a preset first sampling instruction is supported to be sent when the data stored in the first memory is read for any data reading operation;

16. The data transfer method of claim 10, wherein the data read operation comprises reading data stored in the second memory;

17. The data transmission method according to claim 16, wherein when determining that the transmission mode type is a third transmission mode, determining that a clock signal corresponding to the third transmission mode is an initial clock signal, the initial clock signal being the acquired original clock signal;

18. The data transmission method according to claim 16 or 17, wherein after performing the data read operation under each time delay processing of the clock signal corresponding to the transmission mode type, obtaining the read result corresponding to each time of the data read operation comprises:

for any data reading operation, judging whether a preset third sampling instruction is supported to be sent when the data stored in the second memory is read in a third transmission mode;

19. The data transmission method according to claim 10, wherein recording the identification of the delay code used by each data read operation according to the corresponding read result of each data read operation comprises:

20. The data transmission method of claim 10, wherein the performing the data processing operation using the target delay code comprises:

21. A data transmission apparatus, comprising:

22. The data transmission apparatus of claim 21, wherein the data processing operation comprises a data write operation;

The first processing unit includes:

23. The data transmission apparatus of claim 22, wherein the first delay module comprises: a plurality of first delays, a first logic operator, and a first selector, wherein:

24. The data transmission device of claim 23, wherein the delay time lengths corresponding to the first delays are the same.

25. The data transmission apparatus of claim 22, wherein the first processing unit further comprises: and the mode selection module is coupled with the first delay module and is configured to respond to the mode selection signal to control the working state of the first delay module.

26. The data transmission apparatus of claim 21, wherein the data processing operation comprises a data read operation;

The first processing unit includes:

27. The data transmission apparatus of claim 26, wherein the second delay module comprises a plurality of second delays, a second logic operator, and a second selector, wherein:

28. A host, comprising: at least one processor and at least one memory storing one or more computer-executable instructions that are invoked by the processor to perform the data transmission method of any one of claims 1 to 20.

29. A storage medium storing one or more computer-executable instructions which, when executed, implement the data transmission method of any one of claims 1 to 20.