CN118069294A

CN118069294A - Inter-core interrupt injection method and device, electronic equipment and storage medium

Info

Publication number: CN118069294A
Application number: CN202410315987.XA
Authority: CN
Inventors: 孙锋
Original assignee: Beijing Qingyun Science And Technology Co ltd
Current assignee: Beijing Qingyun Science And Technology Co ltd
Priority date: 2024-03-19
Filing date: 2024-03-19
Publication date: 2024-05-24

Abstract

The invention discloses an inter-core interrupt injection method, an inter-core interrupt injection device, electronic equipment and a storage medium. The method is applied to an inter-core interrupt injection system, the system comprises an interrupt injection module positioned in a host machine virtualization system, and a fault processor and a target processor positioned in a virtual machine, and the method comprises the following steps: when the virtual machine is in a dead state due to interrupt response loss, an interrupt injection module sends an inter-core interrupt instruction to a target processor according to a preset inter-core interrupt injection interface; the target processor responds to the inter-core interrupt instruction and feeds back an interrupt response execution result to the fault processor; and the fault processor determines the repairing result of the virtual machine according to the interrupt response executing result. According to the embodiment of the invention, when the virtual machine is in the dead state due to the loss of interrupt response, the dead and stuck faults of the virtual machine are repaired through the IPI injection thought, the normal operation can be recovered without restarting the virtual machine, and the service stability is effectively improved.

Description

Inter-core interrupt injection method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of virtualization technologies, and in particular, to an inter-core interrupt injection method, an inter-core interrupt injection device, an electronic device, and a storage medium.

Background

Inter-core interrupts (IPIs) are a method of communicating between processor cores, and conventional operating systems may send IPI instructions to a designated target processor by invoking specific instructions during operation, and then the target processor responds to the interrupt and executes an interrupt program, where the processor sending the IPI instruction needs to wait for the corresponding target processor to process to complete before proceeding.

In a virtualization scenario, the IPI instruction response process of the virtual machine is simulated by the virtualization layer. In extreme scenarios, there may be a loss of IPI response, resulting in a phenomenon in which the processor sending the IPI instruction in the virtual machine dies due to long-term waiting. When the phenomenon occurs in the prior art, normal operation can be restored only by restarting the virtual machine, and service stability is seriously affected.

Disclosure of Invention

The invention provides an inter-core interrupt injection method, an inter-core interrupt injection device, electronic equipment and a storage medium, which repair the dead-lock fault of a virtual machine caused by interrupt response loss through the IPI injection thought, and can restore normal operation without restarting the virtual machine, thereby effectively improving service stability.

According to an aspect of the present invention, there is provided an inter-core interrupt injection method applied to an inter-core interrupt injection system including an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, the method comprising:

when the virtual machine is in a dead state due to interrupt response loss, an interrupt injection module sends an inter-core interrupt instruction to a target processor according to a preset inter-core interrupt injection interface;

The target processor responds to the inter-core interrupt instruction and feeds back an interrupt response execution result to the fault processor;

and the fault processor determines the repairing result of the virtual machine according to the interrupt response executing result.

According to another aspect of the present invention, there is provided an inter-core interrupt injection apparatus applied to an inter-core interrupt injection system including an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, the apparatus comprising:

The interrupt injection module is used for sending an inter-core interrupt instruction to the target processor according to a preset inter-core interrupt injection interface when the virtual machine is in a dead state due to interrupt response loss;

The interrupt response module is used for responding to the inter-core interrupt instruction by the target processor and feeding back an interrupt response execution result to the fault processor;

And the repair result determining module is used for determining the repair result of the virtual machine according to the interrupt response execution result by the fault processor.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the inter-core interrupt injection method of any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the method for injecting an inter-core interrupt according to any of the embodiments of the present invention when executed.

According to the technical scheme, when the virtual machine is in the dead state due to the loss of interrupt response, the interrupt injection module sends an inter-core interrupt instruction to the target processor according to the preset inter-core interrupt injection interface, the target processor responds to the inter-core interrupt instruction and feeds back an interrupt response execution result to the fault processor, and the fault processor further determines a repair result of the virtual machine according to the interrupt response execution result. According to the embodiment of the invention, when the virtual machine is in the dead state due to the loss of interrupt response, the dead and stuck faults of the virtual machine are repaired through the IPI injection thought, the normal operation can be recovered without restarting the virtual machine, and the service stability is effectively improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of an inter-core interrupt injection method according to a first embodiment of the present invention;

FIG. 2 is a flow chart of an inter-core interrupt injection method according to a second embodiment of the present invention;

FIG. 3 is a flow chart of an inter-core interrupt injection method according to a third embodiment of the present invention;

Fig. 4 is a schematic structural diagram of an inter-core interrupt injection device according to a fourth embodiment of the present invention;

Fig. 5 is a schematic structural diagram of an electronic device implementing an inter-core interrupt injection method according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Under the existing virtualization scene, the IPI instruction response process of the virtual machine is simulated by a virtualization layer, and under some extreme cases, the inter-core interrupt response loss condition possibly occurs, so that a processor of the virtual machine for sending IPI waits for a long time, and the phenomenon of dead halt and blocking of the virtual machine is caused. When the phenomenon occurs, the normal operation can be recovered only by restarting the virtual machine.

Example 1

Fig. 1 is a flowchart of an inter-core interrupt injection method according to an embodiment of the present invention, where the method may be performed by an inter-core interrupt injection device, and the inter-core interrupt injection device may be implemented in hardware and/or software, and the inter-core interrupt injection device may be configured in an electronic device, and the electronic device may be a computer or a server, for example, when it is determined that the virtual machine is in a dead state due to loss of an interrupt response. As shown in fig. 1, an inter-core interrupt injection method provided in the first embodiment is applied to an inter-core interrupt injection system, where the system includes an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, and specifically includes the following steps:

S110, when the virtual machine is in a dead state due to interrupt response loss, the interrupt injection module sends an inter-core interrupt instruction to the target processor according to a preset inter-core interrupt injection interface.

The host machine virtualization system may refer to a virtualization layer implemented on a host machine through virtualization software such as KVM (Kernel-based Virtual Machine ), xen (Xen hypervisor), and the like. The interrupt injection module may be a functional module for implementing an inter-core interrupt (IPI) injection operation, and an interface for injecting IPI instructions into the virtual machine may be preconfigured in the interrupt injection module, that is, an inter-core interrupt injection interface may be preset, where the inter-core interrupt injection interface may at least include: sysfs file interface and procfs file interface.

The target processor may refer to a virtualized central processing unit (Virtualised Central Processing Unit, vCPU) located within the virtual machine for responding to IPI instructions. The fault handler may refer to a corresponding CPU (vCPU) that sends an IPI instruction but does not receive an interrupt response execution result for a long time before the virtual machine is in a dead state, i.e., a CPU that causes the virtual machine to be in a dead state.

The inter-core interrupt instruction may refer to an instruction for delivering an IPI event, where the IPI instruction may include: interrupt vector number, target CPU identification for receiving IPI instructions, etc.

In the embodiment of the invention, when the inter-core interrupt injection system determines that the virtual machine is in a dead state due to interrupt response loss, the interrupt injection module located in the host machine virtualization system can call a preset inter-core interrupt injection interface configured in advance to send an IPI instruction to the target CPU, namely, the target CPU responds to the corresponding IPI by simulating the execution behavior of the normal IPI instruction, wherein the target CPU can comprise a certain designated CPU, certain designated CPUs or all CPUs except for a fault CPU located in the virtual machine.

S120, the target processor responds to the inter-core interrupt instruction and feeds back an interrupt response execution result to the fault processor.

The interrupt response execution result may be an execution result obtained after the target CPU responds to the IPI instruction.

In the embodiment of the invention, after receiving the IPI instruction, the target CPU can respond to the IPI instruction and execute a corresponding interrupt program, and then the executed interrupt response execution result is fed back to the fault CPU. In a specific embodiment, after receiving the IPI instruction, the target CPU may find, in a preset interrupt Vector table according to an interrupt Vector number (Vector) in the IPI instruction, a jump address (i.e. an entry address) of an associated interrupt program, and then the target CPU switches the current program execution flow to the jump address corresponding to the interrupt program, and returns an interrupt response execution result after the interrupt program is executed to the faulty CPU.

S130, the fault processor determines the repairing result of the virtual machine according to the interrupt response executing result.

In the embodiment of the invention, the fault CPU can determine the corresponding repair result of the virtual machine according to the corresponding receiving condition of the interrupt response execution result fed back by the target CPU, specifically, if the fault CPU receives the interrupt response execution result, the fault CPU resumes normal operation, namely, the repair result of the virtual machine is determined to be successful in repair; if the fault CPU does not receive the interrupt response execution result, the fault CPU is still in a non-response state such as dead halt and the like, namely, the repair result of the virtual machine is determined to be repair failure.

Further, when the repair result of the virtual machine is determined to be repair failure, the interrupt injection module can continuously call the preset inter-core interrupt injection interface to send an IPI instruction to the target processor until the fault CPU resumes normal operation, namely the virtual machine is successfully repaired. The dead-end blocking fault of the virtual machine caused by interrupt response loss is repaired through the IPI injection idea, normal operation can be recovered without restarting the virtual machine, and service stability is effectively improved.

It can be understood that, because the target CPU may reappear the interrupt response loss due to the response to the interrupt response execution result fed back by the IPI instruction, the present embodiment may sequentially inject a preset number (e.g. not limited to 10, 20, etc.) of IPI instructions into the target CPU through the preset inter-core interrupt injection interface in a cyclic injection manner, so as to improve the probability that the fault CPU receives the interrupt response execution result, thereby improving the repair success rate of the virtual machine.

Example two

Fig. 2 is a flowchart of an inter-core interrupt injection method according to a second embodiment of the present invention, which is further optimized and expanded based on the foregoing embodiments, and may be combined with each of the optional technical solutions in the foregoing embodiments. As shown in fig. 2, the method for injecting the inter-core interrupt provided in the second embodiment specifically includes the following steps:

S210, when the virtual machine is in a dead state due to interrupt response loss, an interrupt injection module sets an inter-core interrupt instruction corresponding to a preset interrupt command register by calling a preset inter-core interrupt injection interface and a preset interrupt injection function; wherein the inter-core interrupt instruction at least includes: the interrupt vector number and the target local advanced interrupt controller identification.

The preset interrupt injection function may be a function for implementing IPI injection simulation, and the preset interrupt injection function may at least include: the kvm_set_ msr function, through which the IPI injection can be achieved by calling the function to set an interrupt command register (Interrupt Command Register, ICR). The preset Interrupt Command Register (ICR) may refer to an ICR corresponding to the failed CPU. The interrupt vector number (Interrupt Vector Number, IVN) may refer to a unique number used in a computer system to identify an interrupt program. The target local advanced interrupt controller identifier (Local Advanced Programmable Interrupt Controller Identification, LAPIC ID) may refer to unique identifier information corresponding to the target LAPIC, and it should be understood that each CPU corresponds to one LAPIC, so that the LAPIC ID may also be used to identify the CPU, and the LAPIC is responsible for transmitting the received IPI instruction to the corresponding CPU.

In the embodiment of the present invention, when it is determined that a virtual machine is in a dead state due to loss of interrupt response, an interrupt injection module located in a host machine virtualization system may simulate normal execution behavior of an IPI instruction by calling a preset inter-core interrupt injection interface and a preset interrupt injection function, that is, simulate writing the IPI instruction by setting a pin of a preset ICR, where the IPI instruction at least includes: information such as IVN and target LAPIC ID, and the preset inter-core interrupt injection interface at least comprises: sysfs file interface and procfs file interface.

Further, on the basis of the above embodiment of the present invention, the method for injecting an inter-core interrupt provided in this embodiment further includes, before S210:

receiving a trigger operation of a target caller to determine that the virtual machine is in a dead state due to interrupt response loss; wherein, the target calling party at least comprises: target users and target health management systems.

The target caller may be understood as a system caller for monitoring an operation state of the virtual machine, and when detecting that the virtual machine is in a dead state due to loss of interrupt response, invoking an inter-core interrupt injection system to repair the virtual machine by triggering an operation, where the target caller may at least include: target users (e.g., system administrators, operation and maintenance personnel, etc.) and target health management systems (e.g., various virtual machine health management systems, etc.).

In the embodiment of the invention, the target caller can monitor the running state of the virtual machine in real time, when detecting that the virtual machine is in a dead state due to the loss of interrupt response, the target caller can send a virtual machine repairing request to the inter-core interrupt injection system through trigger operations such as related trigger button trigger, command line input and the like which are not limited to the host machine virtualization system, and further after the inter-core interrupt injection system receives the virtual machine repairing request corresponding to the trigger operation, the target caller determines that the virtual machine is in the dead state due to the loss of interrupt response, so that an interrupt injection module positioned in the host machine virtualization system is invoked to carry out dead fault repairing.

It should be understood that the manner in which the target caller detects that the virtual machine is in a dead state due to the interrupt response loss may be: when target calling parties such as a target user and a target health management system detect that an alarm log appears in the kernel of the virtual machine and a preset target function exists in the alarm log, determining that the virtual machine is in a dead state due to interrupt loss; the preset objective function at least comprises the following steps: a smp_call_function_many function and a smp_call_function_single function.

S220, sending the inter-core interrupt instruction to the corresponding target local advanced interrupt controller according to the target local advanced interrupt controller identification, and sending the inter-core interrupt instruction to the target processor by the target local advanced interrupt controller.

In the embodiment of the invention, after the IPI instruction is written by the preset ICR, the IPI instruction can be sent to the target LAPIC corresponding to the target LAPIC ID through the system bus, and then the target LAPIC transmits the IPI instruction to the affiliated target CPU.

S230, the target processor searches a jump address of a corresponding associated target interrupt program in a preset interrupt vector table according to the interrupt vector number of the inter-core interrupt instruction.

The preset interrupt vector table may refer to a pre-configured data structure storing an association relationship between an interrupt vector number and a corresponding interrupt program jump address. The target interrupt program may refer to an interrupt service routine corresponding to an IPI instruction. The jump address may refer to an entry address or a head address corresponding to the target interrupt program.

In the embodiment of the invention, the target CPU can respond to the IPI instruction transmitted by the target LAPIC, search the jump address of the corresponding associated target interrupt program in the preset interrupt vector table according to the IVN in the IPI instruction and by adopting the data query modes such as keyword matching, fuzzy matching and the like, and prepare to start executing the interrupt program.

S240, the target processor executes the target interrupt program corresponding to the jump address, and returns the interrupt response execution result corresponding to the target interrupt program to the fault processor.

In the embodiment of the invention, the target CPU can Interrupt and save the main program currently being executed, then jump and execute the target Interrupt program corresponding to the jump address, after the execution of the target Interrupt program is completed, the target LAPIC corresponding to the target CPU can send an EOI message to all LAPICs in the virtual machine through writing an Interrupt End register (EOI) to inform that the IPI instruction is processed, namely, the Interrupt response execution result corresponding to the target Interrupt program is returned to the fault CPU.

S250, when the fault processor receives the interrupt response execution result, determining that the repair result of the virtual machine is successful.

In the embodiment of the invention, if the fault CPU can normally receive the fed-back interrupt response execution result, the fault CPU can resume normal operation, namely, the restoration result of the virtual machine is determined to be restoration success.

And S260, when the fault processor does not receive the interrupt response execution result, determining that the repair result of the virtual machine is repair failure.

In the embodiment of the invention, if the fault CPU does not receive the fed-back interrupt response execution result, the fault CPU is still in an unresponsive state such as a dead halt and the like, namely, the repair result of the virtual machine is determined to be repair failure.

Further, on the basis of the above embodiment of the present invention, the method for injecting an inter-core interrupt provided in this embodiment further includes:

and when the repair result of the virtual machine is that the repair fails, the interrupt injection module sends an inter-core interrupt instruction to the target processor again according to the preset inter-core interrupt injection interface until the repair result of the virtual machine is determined to be that the repair is successful.

In the embodiment of the invention, due to the interrupt response execution result fed back by the target CPU, the situation of interrupt response loss may occur again, so that the virtual machine repair fails, and at this time, the interrupt injection module can call the preset inter-core interrupt injection interface to send the IPI instruction to the previous target processor again until the fault CPU resumes normal operation, that is, the virtual machine repair is successful. The dead-halt and dead-lock faults of the virtual machine caused by interrupt response loss are repaired through the IPI injection thought, the problem that service operation can only be recovered by restarting the virtual machine in the prior art is avoided, and service stability is effectively improved.

According to the technical scheme, when the virtual machine is in a dead state due to interrupt response loss, an interrupt injection module sets an inter-core interrupt instruction corresponding to a preset interrupt command register by calling a preset inter-core interrupt injection interface and a preset interrupt injection function; according to the identification of the target specimen high-level interrupt controller, sending an inter-core interrupt instruction to a corresponding target specimen high-level interrupt controller, and sending the inter-core interrupt instruction to a target processor by the target specimen high-level interrupt controller; the target processor searches a jump address of a corresponding associated target interrupt program in a preset interrupt vector table according to the interrupt vector number of the inter-core interrupt instruction; the target processor executes the target interrupt program corresponding to the jump address, and returns an interrupt response execution result corresponding to the target interrupt program to the fault processor; when the fault processor receives an interrupt response execution result, determining that the repairing result of the virtual machine is successful repairing; and when the fault processor does not receive the interrupt response execution result, determining that the repair result of the virtual machine is repair failure. When the embodiment of the invention determines that the virtual machine is in a dead state due to loss of interrupt response, the interrupt injection module is used for calling the preset inter-core interrupt injection interface and the preset interrupt injection function, namely, the target CPU responds to the IPI instruction to restore the normal operation of the fault CPU by simulating the execution behavior of the normal IPI instruction, so that the dead fault restoration of the virtual machine is realized, the problem that the service operation can be restored only by restarting the virtual machine in the prior art is avoided, and the service stability is effectively improved.

Example III

Fig. 3 is a flowchart of an inter-core interrupt injection method according to a third embodiment of the present invention, where on the basis of the foregoing embodiments, an implementation manner of the inter-core interrupt injection method is provided, so that a dead-lock failure caused by loss of interrupt response of a virtual machine can be repaired by using an IPI injection concept, and service stability is effectively improved. As shown in fig. 3, a method for injecting an inter-core interrupt according to a third embodiment of the present invention specifically includes the following steps:

S310, receiving a trigger operation of a target calling party, calling a preset inter-core interrupt injection interface and a preset interrupt injection function according to the trigger operation, and circularly injecting a preset number of inter-core interrupt instructions into a target CPU.

In the embodiment of the invention, the triggering operation of target calling parties such as a target user, a target health management system and the like can be received, the virtual machine is determined to be in a dead state due to the loss of interrupt response, then an interrupt injection module of an inter-core interrupt injection system is called, and a preset number (for example 10) of IPI instructions are circularly injected into a target CPU by simulating the execution behavior of normal IPI instructions, so that the target CPU responds to the corresponding IPI to restore the normal operation of a fault CPU, and the virtual machine is restored to the normal state.

It should be understood that, according to the execution logic of the IPI interrupt handler in the operating system, the multi-injection mode does not affect the functions of the system, and the execution logic is consistent whether multiple or single, so that the checking time of a small amount of IPIs is increased. Therefore, a loop injection mode can be adopted to sequentially inject a preset number of IPI instructions into all CPUs except the fault CPU in the virtual machine through a preset inter-core interrupt injection interface, so that the probability that the fault CPU receives an interrupt response execution result is improved, and the success rate of repairing the virtual machine is further improved.

S320, determining whether the fault processor receives an interrupt response execution result corresponding to the inter-core interrupt instruction.

And S330, if yes, determining that the repairing result of the virtual machine is successful repairing.

S340, if not, determining that the repairing result of the virtual machine is repairing failure, calling a preset inter-core interrupt injection interface and a preset interrupt injection function to inject an inter-core interrupt instruction into the target CPU again until the virtual machine is repaired successfully.

According to the technical scheme, a triggering operation of a target calling party is received, a preset inter-core interrupt injection interface and a preset interrupt injection function are called according to the triggering operation, and a preset number of inter-core interrupt instructions are circularly injected into a target CPU; determining whether the fault processor receives an interrupt response execution result corresponding to the inter-core interrupt instruction; if yes, determining that the repairing result of the virtual machine is successful repairing; if not, determining that the repairing result of the virtual machine is repairing failure, calling a preset inter-core interrupt injection interface and a preset interrupt injection function to inject an inter-core interrupt instruction into the target CPU again until the virtual machine is repaired successfully. When the embodiment of the invention determines that the virtual machine is in a dead state due to the loss of interrupt response, the dead and stuck faults of the virtual machine are repaired through the IPI injection thought, the normal operation can be recovered without restarting the virtual machine, and the service stability is effectively improved; meanwhile, by adopting an IPI multi-injection mode, the probability of receiving an interrupt response execution result by a fault CPU can be improved, and the repairing success rate of the virtual machine is further improved.

Example IV

Fig. 4 is a schematic structural diagram of an inter-core interrupt injection device according to a fourth embodiment of the present invention. As shown in fig. 4, the inter-core interrupt injection apparatus is applied to an inter-core interrupt injection system including an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, the apparatus comprising:

The interrupt injection module 41 is configured to send an inter-core interrupt instruction to the target processor according to a preset inter-core interrupt injection interface when it is determined that the virtual machine is in a dead state due to loss of interrupt response;

an interrupt response module 42, configured to respond to the inter-core interrupt instruction by the target processor, and feed back an interrupt response execution result to the fault processor;

and the repair result determining module 43 is configured to determine a repair result of the virtual machine according to the interrupt response execution result by using the fault processor.

Further, on the basis of the above embodiment of the present invention, the interrupt injection module 41 includes:

The module calling unit is used for setting inter-core interrupt instructions corresponding to the preset interrupt command register by calling a preset inter-core interrupt injection interface and a preset interrupt injection function when the virtual machine is in a dead state due to interrupt response loss; wherein the inter-core interrupt instruction at least includes: an interrupt vector number and a target local advanced interrupt controller identification;

And the instruction sending unit is used for sending the inter-core interrupt instruction to the corresponding target specimen advanced interrupt controller according to the target specimen advanced interrupt controller identification and sending the inter-core interrupt instruction to the target processor by the target specimen advanced interrupt controller.

Further, on the basis of the above embodiment of the invention, the interrupt response module 42 includes:

the address searching unit is used for searching the jump address of the corresponding associated target interrupt program in the preset interrupt vector table according to the interrupt vector number of the inter-core interrupt instruction by the target processor;

And the result return unit is used for executing the target interrupt program corresponding to the jump address by the target processor and returning the interrupt response execution result corresponding to the target interrupt program to the fault processor.

Further, on the basis of the above embodiment of the invention, the repair result determining module 43 includes:

The first repair result determining unit is used for determining that the repair result of the virtual machine is successful in repair when the fault processor receives the interrupt response execution result;

And the second repair result determining unit is used for determining that the repair result of the virtual machine is repair failure when the fault processor does not receive the interrupt response execution result.

Further, on the basis of the above embodiment of the present invention, the inter-core interrupt injection device further includes:

The triggering operation receiving module is used for receiving triggering operation of a target calling party so as to determine that the virtual machine is in a dead state due to interrupt response loss; wherein, the target calling party at least comprises: target users and target health management systems.

And the restoration module is used for sending the inter-core interrupt instruction to the target processor again according to the preset inter-core interrupt injection interface when the restoration result of the virtual machine is restoration failure, until the restoration result of the virtual machine is determined to be restoration success.

Further, on the basis of the above embodiment of the present invention, the preset inter-core interrupt injection interface at least includes: sysfs file interface and procfs file interface.

The inter-core interrupt injection device provided by the embodiment of the invention can execute the inter-core interrupt injection method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example five

Fig. 5 shows a schematic diagram of an electronic device 50 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 50 includes at least one processor 51, and a memory, such as a Read Only Memory (ROM) 52, a Random Access Memory (RAM) 53, etc., communicatively connected to the at least one processor 51, in which the memory stores a computer program executable by the at least one processor, and the processor 51 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 52 or the computer program loaded from the storage unit 58 into the Random Access Memory (RAM) 53. In the RAM 53, various programs and data required for the operation of the electronic device 50 can also be stored. The processor 51, the ROM 52 and the RAM 53 are connected to each other via a bus 54. An input/output (I/O) interface 55 is also connected to bus 54.

Various components in the electronic device 50 are connected to the I/O interface 55, including: an input unit 56 such as a keyboard, a mouse, etc.; an output unit 57 such as various types of displays, speakers, and the like; a storage unit 58 such as a magnetic disk, an optical disk, or the like; and a communication unit 59 such as a network card, modem, wireless communication transceiver, etc. The communication unit 59 allows the electronic device 50 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

The processor 51 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 51 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 51 performs the various methods and processes described above, such as the inter-core interrupt injection method.

In some embodiments, the inter-core interrupt injection method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 58. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 50 via the ROM 52 and/or the communication unit 59. When the computer program is loaded into RAM 53 and executed by processor 51, one or more steps of the inter-core interrupt injection method described above may be performed. Alternatively, in other embodiments, processor 51 may be configured to perform the inter-core interrupt injection method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. An inter-core interrupt injection method, applied to an inter-core interrupt injection system, the system comprising an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, the method comprising:

When the virtual machine is in a dead state due to interrupt response loss, the interrupt injection module sends an inter-core interrupt instruction to the target processor according to a preset inter-core interrupt injection interface;

and the fault processor determines the repair result of the virtual machine according to the interrupt response execution result.

2. The method as recited in claim 1, further comprising:

Receiving a trigger operation of a target caller to determine that the virtual machine is in a dead state due to interrupt response loss; wherein the target caller comprises at least: target users and target health management systems.

3. The method according to claim 1, wherein the interrupt injection module sends an inter-core interrupt instruction to the target processor according to a preset inter-core interrupt injection interface when it is determined that the virtual machine is in a dead state due to an interrupt response loss, comprising:

When the virtual machine is in a dead state due to interrupt response loss, the interrupt injection module sets the inter-core interrupt instruction corresponding to a preset interrupt command register by calling the preset inter-core interrupt injection interface and a preset interrupt injection function; wherein the inter-core interrupt instruction at least includes: an interrupt vector number and a target local advanced interrupt controller identification;

And sending the inter-core interrupt instruction to a corresponding target local advanced interrupt controller according to the target local advanced interrupt controller identifier, and sending the inter-core interrupt instruction to the target processor by the target local advanced interrupt controller.

4. The method of claim 1, wherein the target processor responding to the inter-core interrupt instruction and feeding back an interrupt response execution result to the fault processor comprises:

The target processor searches a jump address of a corresponding associated target interrupt program in a preset interrupt vector table according to the interrupt vector number of the inter-core interrupt instruction;

And the target processor executes the target interrupt program corresponding to the jump address, and returns the interrupt response execution result corresponding to the target interrupt program to the fault processor.

5. The method of claim 1, wherein the fault handler determining a repair result of the virtual machine based on the interrupt response execution result comprises:

when the fault processor receives the interrupt response execution result, determining that the repairing result of the virtual machine is successful repairing;

And when the fault processor does not receive the interrupt response execution result, determining that the repair result of the virtual machine is repair failure.

6. The method as recited in claim 1, further comprising:

And when the repair result of the virtual machine is that the repair is failed, the interrupt injection module sends the inter-core interrupt instruction to the target processor again according to the preset inter-core interrupt injection interface until the repair result of the virtual machine is determined to be that the repair is successful.

7. The method of claim 1, wherein the default inter-core interrupt injection interface comprises at least: sysfs file interface and procfs file interface.

8. An inter-core interrupt injection apparatus for use in an inter-core interrupt injection system, the system comprising an interrupt injection module located in a host machine virtualization system, and a fault processor and a target processor located in a virtual machine, the apparatus comprising:

9. An electronic device, the electronic device comprising:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the inter-core interrupt injection method of any of claims 1-7.

10. A computer readable storage medium storing computer instructions for causing a processor to implement the inter-core interrupt injection method of any of claims 1-7 when executed.