CN118060856B - Phased array radar module manufacturing method - Google Patents
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Abstract
The application relates to the field of transmission module manufacturing processes, in particular to a phased array radar module manufacturing method, which comprises the following steps: step 1, software design is carried out, a twin model of a phased array radar module is created, and the phased array radar module is designed through the twin model; step 2, module manufacturing, and modular production is carried out through a production module; step 3, hardware assembly, namely assembling and assembling all the modules through an assembling module to obtain a phased array radar module; and 4, detecting the finished product, namely detecting the finished product through a detection module. The twin model is constructed by a digital twin technology, so that the actual manufacturing operation entity and the twin model are mapped one by one, the operation state of the physical entity of the manufacturing line can be known in real time through the twin model, and the production process problem can be fed back in time, thereby being convenient for management personnel to master the production conditions of different products, different components and different working procedures in time.
Description
Technical Field
The application relates to the field of transmission module manufacturing processes, in particular to a phased array radar module manufacturing method.
Background
Phased array radar uses a set of fixed antenna elements to electronically control the phase of signals to change the direction of the beam, and such systems are widely used in both military and civilian applications. The main advantage of phased array radars is that they can be quickly and flexibly pointed in different directions without moving the antenna itself, which is critical for fast tracking of multiple targets, high speed searching and fire control systems.
The core of a phased array radar system is its T/R (transmit/receive) component module. These modules contain internal microwave integrated circuits and other electronic components responsible for the transmission and reception of signals, which are often micro-packaged in order to enable high performance in a compact space, thus increasing the density of components and the overall complexity of the system.
At present, the phased array radar module has the technical requirements of airtight and salt fog prevention and the like of the module, the implementation process of the module is complex, the module needs to be applied to various micro-packaging mixing processes, and different manufacturing processes have different temperature gradients in the manufacturing process, such as a connector sintering process, a chip sintering process, a 3-layer antenna board sintering process, a PCB (printed circuit board) reflow soldering process, a PCBA (printed circuit board) soldering process, a radio frequency chip bonding process, a gold wire bonding process, a laser seal soldering process, an antenna three-proofing process and the like.
Therefore, the radar module manufacturing method in the prior art not only faces challenges such as thermal management challenges, packaging complexity, and manufacturing precision requirements; the process flow fine control means is lacking, and the whole process flow data cannot be recorded, traced back, analyzed and interacted in real time; there are difficulties in management and optimization of materials and manufacturing equipment, and effective improvements in the manufacturing methods of radar modules are needed.
Disclosure of Invention
The application aims to provide a phased array radar module manufacturing method which is used for carrying out fine pipe control on the radar module manufacturing process through a digital twin technology, simultaneously carrying out control transformation on the temperature gradient of the manufacturing process through an integrated parameter model, and further being used for high-precision assembly process control of the radar module.
The application is realized by the following technical scheme:
A method of manufacturing a phased array radar module, comprising the steps of: step 1, software design, namely creating a twin model of a phased array radar module based on a digital twin technology, and designing the phased array radar module through the twin model, wherein the phased array radar module comprises an array antenna, a connector, a heat pipe, a phase shifter and a T/R unit; step 2, module manufacturing, namely after the step 1 is completed, simulating a manufacturing process by using a twin model, predicting and optimizing a manufacturing flow, and carrying out modularized production by using a production module; step 3, hardware assembly, namely simulating an assembly process by using a twin model after the step 2 is completed, and assembling all modules through an assembly module to obtain the phased array radar module; step 4, detecting finished products, namely detecting the finished products of the phased array radar module obtained in the step 3 through a detection module;
the twin model comprises a physical layer, a twin layer and an interaction layer, wherein the physical layer corresponds to actual data information of the phased array radar module, the twin layer carries out real-time digital mapping through the actual data information acquired by the physical layer, and the physical layer and the twin layer carry out interconnection mapping and updating calculation in the interaction layer; in the assembling process of the step 3, the temperature gradient control process under different assembling procedures is carried out through the central control module, wherein the control process is as follows: and taking the temperature information acquired by the physical layer as iteration data of the twin model, generating a temperature estimation signal by a temperature controller in the central control module based on the iteration data, and carrying out feedback adjustment according to the temperature of the temperature estimation signal.
Further, the design structure of the phase shifter in step 1 includes the following signal connections: the input balun, the quadrature signal generator, the signal synthesizer, the output balun and the compensation amplifier, wherein a buffer is added to the output of the signal synthesizer for insertion loss compensation and impedance transformation, the signal synthesizer is also connected with a DAC (digital-to-analog converter) conversion circuit in a signal connection mode, and the DAC conversion circuit is connected with a bias circuit, a logic encoder and a switch circuit in a signal connection mode.
Further, in step 3, the twin model is integrated with a parametric model, the parametric model is used for describing metadata samples of the phased array radar module in the twin layer, and parameterizing steps of the parametric model on the metadata samples are as follows: setting model precision, determining the space variation range of assembly parameters, and generating a plurality of initial parameter samples containing space vertexes by using Latin hypercube sampling; acquiring a scattering parameter curve at the parameter sample; establishing a transfer function coefficient matrix corresponding to the assembly parameters through a scattering parameter curve based on a vector fitting algorithm; modeling the transfer function coefficient matrix by utilizing an extreme learning machine algorithm, and constructing to obtain a parameter model; and carrying out convergence judgment, searching error points in the parameter samples in the sample set, updating the sample points if the error points do not meet the model precision, and carrying out assembly if the error meets the model precision.
Further, the phased array radar module further comprises a radar cavity, a chip, a carrier plate and a substrate, and in the step 3, the assembly procedure of the phased array radar module is as follows: the method comprises the steps of sleeve alignment, cleaning, connector sintering, bottom layer array antenna and radar cavity sintering, array antenna feed spot welding, top layer array antenna and middle layer array antenna sintering, middle layer array antenna and bottom layer array antenna sintering, chip and carrier plate eutectic, carrier plate and radar cavity sintering, substrate bonding, chip bonding, PCBA mounting, gold wire bonding, phased array radar module testing, laser seal welding, array antenna three-proofing and phased array radar module retesting, and the phased array radar module finishes warehousing after retesting inspection.
Further, in the assembling process of step 3, the sintering temperature of the connector is 351 ℃ to 371 ℃; the temperature interval between the bottom layer array antenna and the sintering of the radar cavity is 230-250 ℃; the temperature interval of the feed spot welding of the array antenna is 207 ℃ to 227 ℃; the sintering temperature interval of the top layer array antenna and the middle layer array antenna is 230-250 ℃; the sintering temperature interval of the middle layer array antenna and the bottom layer array antenna is 173-193 ℃; the temperature interval of eutectic of the chip and the carrier plate is 270-290 ℃; the sintering temperature interval of the carrier plate and the radar cavity is 139-159 ℃; the temperature range of gold wire bonding is 110 ℃ to 130 ℃; the temperature range for die bonding is 120 ℃ to 140 ℃.
Further, in the sintering process of the connector, the connector is installed in the welding groove, and then the welding clamp is used for synchronously limiting the connector, so that the welding process is completed.
Further, the substrate manufacturing process includes: casting, blanking and cutting, punching, filling through holes, printing a conductive medium, laminating and hot-pressing, hot cutting, discharging glue and sintering.
Further, the carrier plate is preprocessed before eutectic of the chip and the carrier plate, and the preprocessing process is as follows: selecting a carrier substrate, performing surface treatment, and sputtering a seed layer on the front side and the back side of the carrier substrate by magnetron sputtering; performing first thick photoresist lithography on the seed layer to expose a plurality of first-stage step areas; then the carrier substrate subjected to the first thick photoresist photoetching is put into electroplating solution for electroplating treatment; carrying out second thick photoresist photoetching on the carrier plate base material after the electroplating treatment to expose a plurality of secondary steps; and electroplating the carrier plate base material subjected to the second thick photoresist photoetching to form a step structure and a concave cavity which can be matched with the chip size, and finally taking the carrier plate subjected to the preprocessing as a positioning fixture of the chip.
Further, after the preprocessing is finished, carrying out fine processing treatment on the carrier plate, wherein the fine processing treatment process is as follows: carrying out double-sided thinning leveling treatment on the prefabricated carrier plate, and polishing after the leveling treatment is finished, so that the surface roughness of the carrier plate is lower than 0.82 mu m; after the carrier plate is cleaned, carrying out surface electroplating treatment, and carrying out graphic photoetching treatment on the surface of the carrier plate after electroplating; etching the carrier plate subjected to graphic photoetching treatment to etch out a positioning graphic; and immersing the corroded carrier plate in photoresist removing liquid, and finishing fine processing of the carrier plate by a scribing technology.
Compared with the prior art, the application has the following advantages and beneficial effects:
1. According to the application, a twin model is constructed by a digital twin technology, so that an actual manufacturing operation entity and the twin model are mapped one by one, the operation state of a physical entity of a manufacturing line can be known in real time through the twin model, and the production process problem can be fed back in time, thereby being convenient for a manager to master the production conditions of different products, different components and different working procedures in time, and realizing real-time analysis of the process parameters of equipment in a key working procedure, real-time master of the production progress and the material use condition of different projects and real-time monitoring of the state of different equipment through a flow data visualization technology, thereby providing an all-around analysis tool for the manager;
2. According to the application, by setting the model precision and determining the variation range of the assembly parameter space, an accurate parameter model can be created, which is helpful for predicting and controlling errors possibly occurring in the assembly process, and an Latin hypercube sampling method is adopted to generate an initial parameter sample, so that the whole parameter space can be effectively covered, and the method is more efficient and uniform than the traditional grid sampling method, and is helpful for better understanding the influence of parameter variation on the assembly errors; the sample points which do not meet the model precision can be dynamically identified and corrected by judging the convergence and searching the error points of the parameter samples in the sample set, and the iterative learning and updating process is beneficial to continuously improving the model accuracy and reducing the assembly error;
3. The hierarchical structure design of the carrier plate is beneficial to forming complex concave cavities and step structures, and provides accurate reference for chip positioning; the two electroplating treatments enable the carrier substrate to form step structures and cavities that can be matched with the chip size, and these structures are critical to achieving accurate eutectic of the chip and the carrier.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:
FIG. 1 is a schematic flow chart of a manufacturing method of the present application;
FIG. 2 is a block diagram of a manufacturing system of the present application;
FIG. 3 is a logical block diagram of a manufacturing method of the present application;
FIG. 4 is a schematic diagram of a design structure of a phase shifter according to the present application;
Fig. 5 is a schematic partial structure of the carrier of the present application.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present application, the present application will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present application and the descriptions thereof are for illustrating the present application only and are not to be construed as limiting the present application. It should be noted that the present application is already in a practical development and use stage.
In order to make the technical solution of the present application clearer, a phased array radar module manufacturing system is described herein, specifically, the phased array radar module manufacturing method is based on the phased array radar module manufacturing system, as shown in fig. 2, the system includes a server group, and further includes a production module, a twin module, an assembly module, a detection module and a central control module which are connected with the server group through signals, the twin module is connected with the production module and the assembly module through signals, a digital twin model is carried in the twin module and is used for simulation analysis of each module of the phased array radar,
It should be noted that the production module may be an automated production line which is mature in the prior art, including but not limited to a Printed Circuit Board (PCB) manufacturing apparatus, a chip mounter, a reflow oven, a wave soldering apparatus, an electroplating apparatus, a thin film deposition apparatus, a photolithography apparatus, an etching apparatus, a packaging apparatus, a diffusion furnace, etc.; the assembly module can be an automatic assembly line which is mature in the prior art, such as a multi-axis assembly robot and the like; the detection module can comprise a code scanning gun, a printer, a high-speed camera, antenna test equipment, a signal generator, a spectrum analyzer, a network analyzer and the like; the central control module comprises a large-screen display and a central control unit which are connected through signals, and a temperature controller is arranged in the central control unit, wherein the temperature controller is preferably a PID fuzzy controller with a Smith estimated controller.
In order to make the technical solution of the present application more clear, the terms of the present application are described herein, specifically:
In the present application, the term "digital twin technique" refers to a simulation technique that simulates the behavior and performance of a physical object by creating a virtual copy of it, which copy can be used to predict the behavior of the actual object in the real world and can be used to optimize design and production flow;
In the present application, the term "phased array radar module" refers to a highly flexible radar system capable of electronically controlling the direction of a radar beam, rather than physically moving an antenna, by which is meant that the radar system is composed of a plurality of independent modules including array antennas, connectors, heat pipes, phase shifters, T/R units, and the like;
In the present application, the term "actual data information" includes, but is not limited to: precise component size and geometry; material properties such as dielectric constant, magnetic permeability, electrical conductivity, thermal conductivity, etc.; the weight and density of the assembly; processing parameters such as temperature, pressure, processing speed, time, etc.; working environment temperature, humidity, air pressure, etc.;
In the present application, the term "interconnection map" refers to the bi-directional flow and synchronization of data and information between the physical layer (i.e., the actual phased array radar module) and the twinning layer (i.e., the twinning of the radar module);
In the present application, the term "update computation" refers to the use of real-time data collected from the physical layer to refresh and optimize information and parameters in the twin layer to ensure that the digital model accurately reflects the current state and behavior of the physical entity.
Example 1:
As shown in fig. 1, a method for manufacturing a phased array radar module includes the following steps:
Step 1, software design, namely creating a twin model of a phased array radar module based on a digital twin technology, and designing the phased array radar module through the twin model, wherein the phased array radar module comprises an array antenna, a connector, a heat pipe, a phase shifter and a T/R unit; in this step, a twin model of the phased array radar module is constructed by digital twin technology, the twin model also comprises a virtual model of the manufacturing system, and a designer can perform radar model test and optimal design in a virtual environment.
Step 2, module manufacturing, namely after the step 1 is completed, simulating a manufacturing process by using a twin model, predicting and optimizing a manufacturing flow, and carrying out modularized production by using a production module; using the twin model in step 1 to simulate the entire manufacturing process can help predict potential problems and optimize the process prior to actual production.
Step 3, hardware assembly, namely simulating an assembly process by using a twin model after the step 2 is completed, and assembling all modules through an assembly module to obtain the phased array radar module; this step includes actually assembling the hardware parts of the radar module, using a twin model to simulate the assembly process and ensure that all steps are optimized prior to actual operation.
Step 4, detecting finished products, namely detecting the finished products of the phased array radar module obtained in the step 3 through a detection module; and finally, detecting the performance and quality of the finished product through a detection module, and ensuring that all specifications and performance indexes meet the requirements.
The twin model comprises a physical layer, a twin layer and an interaction layer, wherein the physical layer corresponds to actual data information of the phased array radar module, the twin layer carries out real-time digital mapping through the actual data information acquired by the physical layer, and the physical layer and the twin layer carry out interconnection mapping and updating calculation in the interaction layer; in the assembling process of the step 3, the temperature gradient control process under different assembling procedures is carried out through the central control module, wherein the control process is as follows: and taking the temperature information acquired by the physical layer as iteration data of the twin model, generating a temperature estimation signal by a temperature controller in the central control module based on the iteration data, and carrying out feedback adjustment according to the temperature of the temperature estimation signal.
It should be noted that, the method for manufacturing the radar module in the prior art not only faces challenges such as thermal management challenges, packaging complexity, and manufacturing precision requirements; the process flow fine control means is lacking, and the whole process flow data cannot be recorded, traced back, analyzed and interacted in real time; there are difficulties in the management and optimization of materials and manufacturing equipment. Based on the above problems, the applicant proposes a method for manufacturing a phased array radar module, and a complex intelligent manufacturing method based on a combination of technologies and devices such as a three-dimensional modeling technology, a network communication technology, a digital twin technology, etc., the overall manufacturing logic of which is shown in fig. 3, in the manufacturing process of the phased array radar module, a detailed manufacturing procedure is first set, which includes an operation guideline, required materials, components and devices for each step, and how to configure the whole manufacturing system to most efficiently produce a high quality product, after the manufacturing system is configured, the system operates according to a predetermined procedure, and each step operation in the manufacturing process generates manufacturing signals, which include critical information about the production state, the efficiency of the device, and the quality of the product; on the basis, the Li Sheng model is connected with a manufacturing system, and the manufacturing process is analyzed and optimized, so that the stable operation of the system is ensured; meanwhile, the interface association mapping of the manufacturing signals and the digital twin model signals plays an important role, and the mapping process ensures that actual data of a production site can be fed back into the digital twin model in real time; these real-time data then drive the virtual operation of a digital twin model that can simulate the actual production process, predict product quality, identify potential failures or bottlenecks, and provide advice to improve the manufacturing process. This data-based virtual simulation enables the production system to be adjusted and optimized before real world problems occur, thereby improving the production efficiency and product quality of the entire phased array radar module.
It should be further noted that, the twin model is constructed by digital twin technology, so that the actual manufacturing operation entity and the twin model are mapped one by one, and then the operation state of the physical entity of the manufacturing line can be known in real time through the twin model, for example, by implementing the real-time traceability module of the manufacturing process, operators can report various production process data in real time through the module, and can feed back the production process problems in time, so that the manager can conveniently master the production conditions of different products, different components and different procedures in time. Through a process data visualization technology, real-time analysis of process parameters of key process equipment, real-time mastering of production progress and material service conditions of different items and real-time monitoring of different equipment states are realized, so that an all-around analysis tool is provided for management staff.
It should be further noted that, for the temperature gradient control process of the temperature controller in the central control module, it is not practical that the model is always perfectly matched with the actual data object, and only the absolute real data object effort can be made to approach the orientation infinitely, and the temperature controller also has deviations in control structure and parameter design estimation due to the complexity or dynamic change property of the parameters, which is particularly prominent in the temperature gradient control process in the assembly and the assembly of the phased array radar module, and not only has continuous change of time sequence, but also has dynamic deviation in environmental temperature factors. Based on the above situation, the first-order inertia law of the temperature controller is deduced by converting the collected temperature signal into a digital signal and based on the temperature set by the server group, and the first-order inertia law satisfies the closed-loop response of the control process of the temperature controller, and for the first-order inertia law, the first-order system based on the lyapunov design theory is adopted. Specifically, taking a Smith predictive controller as an example, in order to divide a transfer function of the predictive controller into an abnormal part and a normal part, then take out an output signal of the abnormal part as a feedback signal during adaptive control, and compensate the feedback signal to the normal part, in short, the continuous change of a time sequence and the influence of dynamic deviation on environmental temperature factors on a temperature gradient are eliminated through a compensation process of the Smith predictive controller.
It should be noted that, the design structure of the phase shifter in step 1 includes the following signal connections: the input balun, the quadrature signal generator, the signal synthesizer, the output balun and the compensation amplifier, wherein a buffer is added to the output of the signal synthesizer for insertion loss compensation and impedance transformation, the signal synthesizer is also connected with a DAC (digital-to-analog converter) conversion circuit in a signal connection mode, and the DAC conversion circuit is connected with a bias circuit, a logic encoder and a switch circuit in a signal connection mode.
It should be noted that, besides being able to perform phase modulation, the phase shifter can also obtain a certain variation of the amplitude of the signal and can provide a phase shift in the range of 0 ° to 360 °, but the phase shifter in the prior art also has some problems, such as errors generated by each module unit, and asymmetry of the circuit in different phase states, which cannot be eliminated, and the influence can only be reduced by continuous optimization, and referring to fig. 4, the quadrature signal generator in the figure can generate four-way two-by-two quadrature differential signals. Also in the present embodiment, the signal synthesizer is preferably a vector synthesizer or a gilbert cell circuit, taking the gilbert cell circuit as an example, which can perform polarity selection while performing the gain method; the logic encoder finishes encoding the digital control signal input externally, the output of the logic encoder is used for controlling the DAC conversion circuit, and the DAC conversion circuit converts the control signal generated by the logic encoder into an analog signal input by the circuit and sends the analog signal to the input end of the signal synthesis unit, so that the phase modulation of the signal is finished.
The above design can not only realize accurate phase modulation but also adjust signal amplitude by integrating the quadrature signal generator, the signal synthesizer (preferably a vector synthesizer or a gilbert cell circuit), the DAC conversion circuit and the compensation amplifier. Secondly, a buffer is added to the output of the signal synthesizer, which is helpful for insertion loss compensation and impedance matching, so that the signal quality and transmission efficiency are improved, and the overall distortion of the system is reduced; in addition, through the cooperation of the logic encoder and the DAC conversion circuit, the digital control signal can be more accurately converted into an analog signal, and high-precision phase modulation is realized. Even if the problems of module unit errors, circuit asymmetry under the phase state and the like exist, the influence of the errors can be effectively reduced through the optimization of the design, and the overall performance and reliability of the system are further improved. For an input balun, an input signal is converted into a differential form, and then two orthogonal signals of four paths are generated through an orthogonal signal generator; for the orthogonal signal generator, two-stage polyphase filters based on RC network may be used to form the orthogonal signal generator in this embodiment, specifically, the first stage converts the input differential signal into four-way signals that are input to the second stage network in two-two orthogonal manner, and then outputs the four-way signals through the second stage network. To minimize the loss of the circuit, two differential inductive loads are connected at the terminals of the circuit to resonate with the capacitance at the circuit terminals. Preferably, for the logic encoder, the logic encoder in this embodiment is designed to generate 64 kinds of logic control units by using six-bit digital signals to select 64 kinds of bit shift circuits, which are sequentially from 000000 to 111111.
In the step 3, the twin model is integrated with a parameter model, the parameter model is used for describing metadata samples of the phased array radar module in the twin layer, and the parameterization step of the parameter model on the metadata samples is as follows: setting model precision, determining the space variation range of assembly parameters, and generating a plurality of initial parameter samples containing space vertexes by using Latin hypercube sampling; acquiring a scattering parameter curve at the parameter sample; establishing a transfer function coefficient matrix corresponding to the assembly parameters through a scattering parameter curve based on a vector fitting algorithm; modeling the transfer function coefficient matrix by utilizing an extreme learning machine algorithm, and constructing to obtain a parameter model; and carrying out convergence judgment, searching error points in the parameter samples in the sample set, updating the sample points if the error points do not meet the model precision, and carrying out assembly if the error meets the model precision.
It should be further noted that, when the phased array radar module in the prior art is assembled and assembled, the mechanical processing precision of the structure is dependent, and then various structural deviations of the components inevitably occur in the processing and manufacturing process, and the structural deviations are further amplified when the assembly and the assembly are performed, so that the transmission performance of the radar module is affected, and therefore, the structural assembly deviation needs to be reduced in the assembly process of the radar module. Specifically, due to lamination, hole filling or sintering and other factors, plate inter-stage alignment deviation is easy to occur, so that structure dislocation occurs, the structure dislocation influences signal transmission, and insertion loss among transmission structures is increased; the joint connection process in the assembly process also affects the transmission performance of the radar module, and because the joint connection process is limited by uncertain factors such as the actual size and the installation position of the radio frequency devices on the substrate, gaps can appear when different circuit substrates are connected, and the size of the gap changes the impedance matching of the transmission line, so that the transmission performance of the high-density T/R unit is affected.
Based on the above-mentioned problems, the applicant has proposed a parametric model suitable for the assembly and manufacture of radar modules, and integrated in a twinning model, in particular, which satisfies:
；
Wherein, Response to the parametric model;
、、、、 Respectively representing the size coefficient, the interconnection dislocation coefficient, the feeder width coefficient, the gap error coefficient and the array antenna spacing coefficient of the substrate;
、、、、 representing a state equation matrix corresponding to the size coefficient of the substrate, the interconnection dislocation coefficient, the feeder width coefficient, the gap error coefficient and the array antenna spacing coefficient respectively;
representing complex frequencies for expressing the frequency response of the radar module and satisfying ; Wherein j is the upper and lower limit ranges of the frequency interval; represents angular frequency; f represents a cycle frequency; in this embodiment, the behavior of the parametric model can be extended into the complex frequency domain based on the frequency response;
i is the initial parameter of the parameter model;
n is the endpoint parameter of the parametric model.
For the above parameter model, it should be noted that, the parameter model reflects the transmission performance of the radar module under different geometric parameter variables (including but not limited to the size coefficient of the substrate, the interconnection dislocation coefficient, the feeder width coefficient, the slot error coefficient, the array antenna spacing coefficient, and the like, and the geometric parameter variable can be continuously introduced into the model) and complex frequency parameters, the parameter model uses a vector fitting method to establish a rational macro model related to complex frequency, further obtains a corresponding state equation matrix under the metadata sample, and further realizes parameters by means of an extreme learning algorithmResponse toThe parameterized modeling process of (2) and the vector fitting process are as follows: the vector fitting process is completed by presetting a group of pole random vectors, introducing data to be fitted, and repeating the iterative process until the stable vectors are obtained after convergence.
The parameter model can be used for accurately describing a group of metadata samples in the assembly process, wherein the metadata samples can be assembly deviations among certain modules and can be expressed as. And establishing a parameter model related to frequency by using a vector fitting method, further obtaining a corresponding transfer function coefficient matrix under the assembly data, and further realizing a parametric modeling process from parameters to responses by using an extreme learning machine algorithm. By setting the model precision and determining the variation range of the assembly parameter space, an accurate parameter model can be created, which is helpful for predicting and controlling errors possibly occurring in the assembly process, and an Latin hypercube sampling method is adopted to generate an initial parameter sample, so that the whole parameter space can be effectively covered, and the method is more efficient and uniform than the traditional grid sampling method, and is helpful for better understanding the influence of parameter variation on the assembly errors; the sample points which do not meet the model precision can be dynamically identified and corrected by judging the convergence and searching the error points of the parameter samples in the sample set, and the iterative learning and updating process is helpful for continuously improving the model accuracy and reducing the assembly error.
It should be noted that, the phased array radar module further includes a radar cavity, a chip, a carrier plate and a substrate, and in step 3, the assembly procedure of the phased array radar module is as follows: the method comprises the steps of sleeve alignment, cleaning, connector sintering, bottom layer array antenna and radar cavity sintering, array antenna feed spot welding, top layer array antenna and middle layer array antenna sintering, middle layer array antenna and bottom layer array antenna sintering, chip and carrier plate eutectic, carrier plate and radar cavity sintering, substrate bonding, chip bonding, PCBA mounting, gold wire bonding, phased array radar module testing, laser seal welding, array antenna three-proofing and phased array radar module retesting, and the phased array radar module finishes warehousing after retesting inspection.
In the assembling procedure of the step 3, the sintering temperature of the connector is 351 ℃ to 371 ℃; the temperature interval between the bottom layer array antenna and the sintering of the radar cavity is 230-250 ℃; the temperature interval of the feed spot welding of the array antenna is 207 ℃ to 227 ℃; the sintering temperature interval of the top layer array antenna and the middle layer array antenna is 230-250 ℃; the sintering temperature interval of the middle layer array antenna and the bottom layer array antenna is 173-193 ℃; the temperature interval of eutectic of the chip and the carrier plate is 270-290 ℃; the sintering temperature interval of the carrier plate and the radar cavity is 139-159 ℃; the temperature range of gold wire bonding is 110 ℃ to 130 ℃; the temperature range for die bonding is 120 ℃ to 140 ℃.
It should also be noted that, for alignment sleeves, it involves preparing and inspecting all necessary components, ensuring complete and fitting assembly requirements, including but not limited to radar cavities, chips, carrier plates, substrates, etc.; for cleaning, before assembly, all parts need to be thoroughly cleaned to remove surface contaminants, oil and dust to ensure high quality of the sintering and welding process; sintering the connector; the method comprises the steps of forming solid connection between a connector and a radar cavity, for example, forming a welding ring by using Au88Ge12 (361 ℃), installing the welding ring in a welding groove, and welding after limiting the connector by using a fixture; sintering the bottom layer array antenna, selecting Sn90Sb10 (240 ℃) custom-made forming soldering lug, mounting on a welding surface, limiting by using pins, and fixing the array antenna by using a fixture clamp; sintering the top layer array antenna, namely sintering the top layer antenna and the middle layer antenna together by using a Sn90Sb10 (240 ℃) custom-made forming soldering lug on a tool piece; sintering the middle layer array antenna, and sintering the independently sintered upper layer antenna and bottom layer antenna by adopting a Sn63Pb37 (183 ℃) forming soldering lug; for eutectic sintering of the power amplifier chip, au80Sn20 (280 ℃) molding soldering lug is selected for sintering; for PCB reflow soldering, the reflow soldering temperature is selected to be Sn96.5Ag3Cu0.5 (217 ℃) soldering; for feed point welding, all connector pin interconnection electrical welding adopts Sn96.5Ag3Cu0.5 (217 ℃) solder; for chip bonding, the radio frequency chip is bonded on the cavity by using a double-component conductive adhesive, and the curing temperature is 130 ℃; for gold wire bonding, the temperature of the gold wire bonding process is 120 ℃; for laser seal welding, the outer cover plate is subjected to seal welding in a sealed nitrogen environment, and the cover plate is bonded and fixed by using a tooling fixture in the seal welding process; for the three-proofing of the array antenna, a layer of high-frequency three-proofing paint is sprayed on the side wall and the top surface around the antenna in a spraying mode.
It should be noted that the above-mentioned assembly process is only a preferred example, and is not limited thereto, and in some embodiments, the assembly temperature gradient of the present application may be: the sintering temperature of the connector is 361 ℃; the temperature interval between the bottom layer array antenna and the sintering of the radar cavity is 240 ℃; the temperature interval of the feed spot welding of the array antenna is 217 ℃; the sintering temperature interval of the top layer array antenna and the middle layer array antenna is 240 ℃; the sintering temperature interval of the middle layer array antenna and the bottom layer array antenna is 183 ℃; the temperature interval of the eutectic of the chip and the carrier plate is 280 ℃; the sintering temperature interval of the carrier plate and the radar cavity is 149 ℃; the temperature interval of gold wire bonding is 120 ℃; the temperature interval for die bonding was 130 ℃. The procedures embody comprehensive consideration of high-precision assembly, structural integrity, electrical connection reliability, production efficiency and strict quality control, so that the phased array radar module has remarkable improvement in performance, reliability and durability compared with the prior art, and is particularly suitable for military and civil fields with strict requirements on high performance and high reliability.
In this embodiment, it is preferable that the connector is mounted in the welding groove during sintering of the connector, and the welding process is completed after the connector is synchronously limited by using the welding jig. For welding jig, after first anchor clamps, second anchor clamps and cavity pass through pin, screw location installation, send into logical inslot respectively with the connector, and through pushing away a section of thick bamboo downwards to promote the connector, the connector is when receiving annular array's stopper spacing whereabouts, the central axis of connector and the central axis coincidence of logical groove can be corrected to the stopper, continue to promote the connector whereabouts, make the connector fall into the holding tank and wear to establish and weld the ring and get into the spacing inslot, take out and push away a section of thick bamboo, the pressure that the stopper received disappears, the spring resets, the stopper rotates to logical groove, and contradict at the top of connector through the arcwall face of bottom, carry out axial spacing to the connector, guarantee that the connector has higher position accuracy and be difficult for taking place axial float when the heat welding.
The manufacturing process of the substrate includes: casting, blanking and cutting, punching, filling through holes, printing a conductive medium, laminating and hot-pressing, hot cutting, discharging glue and sintering. It should be further noted that, for casting, the ceramic glass powder and the organic binder with proper proportion are uniformly mixed, and the above materials are only one preferred choice in the embodiment, and are not limited by the materials, and are pulped to form slurry, and then cast on a plane carrier moving at a uniform speed to form a green ceramic tape with compactness, uniform thickness and certain strength and toughness; for blanking and cutting, spreading the raw porcelain tape rolled on a reel, flatly fixing the raw porcelain tape on a clean workbench through a positioning hole, baking the raw porcelain tape at 120 ℃, cutting the raw porcelain tape according to the required size and shape, and cutting the raw porcelain tape by using a cutter or laser; the punching comprises a heat conduction hole, a micro-channel groove body and a positioning hole; for filling the through holes, the through holes to be filled only have heat conducting holes, and silver paste added with glass powder is filled in the through holes, so that the sintering is more compact in the later co-firing process; for printing of a conductive medium, wiring design is carried out by utilizing a twin model, and the positions and the sizes of the through holes are taken into consideration during design; stacking the green ceramic sheets filled with the through holes and printed with the electrodes together in sequence for lamination and hot pressing, wherein the alignment holes on the green ceramic sheets are correspondingly consistent with the alignment posts on the stacking base; for hot cutting, cutting before sintering, and cutting out a frame irrelevant to a module; and for glue discharging and sintering, sintering according to a designed sintering curve in the sintering process.
It should be noted that, the pretreatment is performed on the carrier before eutectic of the chip and the carrier, and the pretreatment process is as follows: selecting a carrier substrate, performing surface treatment, and sputtering a seed layer on the front side and the back side of the carrier substrate by magnetron sputtering; performing first thick photoresist lithography on the seed layer to expose a plurality of first-stage step areas; then the carrier substrate subjected to the first thick photoresist photoetching is put into electroplating solution for electroplating treatment; carrying out second thick photoresist photoetching on the carrier plate base material after the electroplating treatment to expose a plurality of secondary steps; and electroplating the carrier plate base material subjected to the second thick photoresist photoetching to form a step structure and a concave cavity which can be matched with the chip size, and finally taking the carrier plate subjected to the preprocessing as a positioning fixture of the chip.
It should be noted that, after the preprocessing is completed, the carrier plate is subjected to fine processing, and the fine processing process is as follows: carrying out double-sided thinning leveling treatment on the prefabricated carrier plate, and polishing after the leveling treatment is finished, so that the surface roughness of the carrier plate is lower than 0.82 mu m; after the carrier plate is cleaned, carrying out surface electroplating treatment, and carrying out graphic photoetching treatment on the surface of the carrier plate after electroplating; etching the carrier plate subjected to graphic photoetching treatment to etch out a positioning graphic; and immersing the corroded carrier plate in photoresist removing liquid, and finishing fine processing of the carrier plate by a scribing technology.
It should also be noted that in the radar module manufacturing process, in order to meet the requirements of high heat dissipation and grounding (low ohmic contact) of the chips, reliable interconnection of multiple chips with the radar cavity is required, and in this process, nondestructive pick-up, transfer and placement of bare chips, high efficiency of multi-chip soldering and high solder penetration of the soldering surfaces are required. Based on this, the applicant proposes to use a carrier plate as a positioning fixture of a chip, and to specifically manufacture the carrier plate according to the clamping and positioning function of the carrier plate, where the chip includes, but is not limited to, a power amplifier bare chip, a drive amplifier bare chip, a phase shifter bare chip, an amplifier bare chip, a limiter bare chip, and the like. Specifically, the partial structure schematic diagram of the carrier plate is shown in fig. 5, wherein the first-stage step area is smaller than the second-stage step area, and the surface treatment performed after the carrier plate base material is selected can remove impurities such as an oxide layer, greasy dirt and the like, so that the cleanliness and the adhesive force of the surface of the carrier plate are improved, and a good foundation is created for the subsequent deposition of the seed layer; and sputtering a seed layer on the front side and the back side of the carrier substrate to provide a conductive base for electroplating and ensure the uniformity and the adhesive force of an electroplated layer. This step is critical to forming a good electroplated structure; the primary step area and the secondary step area are exposed through twice thick photoresist photoetching, and the hierarchical structure design is beneficial to forming complex concave cavities and step structures, so that accurate reference is provided for chip positioning; the two electroplating treatments enable the carrier substrate to form step structures and cavities that can be matched with the chip size, and these structures are critical to achieving accurate eutectic of the chip and the carrier. In addition, the graphic lithography process is: and coating photoresist on the surface of the carrier plate, performing exposure and lithography, exposing the positioning pattern, and then attaching protective adhesive on the back surface.
Example 2:
In order to make the technical scheme of the application clearer, a process of constructing a twin model by aiming at a digital twin technology is described in the embodiment, specifically, firstly, the twin model is constructed, when modeling entity equipment of a manufacturing system, a link node is formed by extracting a functional component, a moving component, a fixed component and an inheritance component on the basis of the functional component and the moving component, each link node has a respective characteristic root and is used for responding to the organization structure of the link node, the link node is divided into a father node, a son node and a brother node in terms of the hierarchy of the link node, the son node is a node under the father node, and the link component is the inheritance component of the link component of the father node; a parent node is a node above a child node; the brother node is a node before or after another node belonging to the same father node, the link parts of the two brother nodes are inheritance parts of the link parts of the same father node, and the manufacturing system in the application is a moving chain formed by linking a series of father nodes and child nodes together.
More specifically, taking a multi-axis automated assembly line as an example, extracting features from a multi-axis automated assembly line center model, including Y-axis moving parts, to form a link node Y; extracting an X-axis moving part on the basis of a Y-axis moving structure, wherein a link node Y and a link node X are in a father-son inheritance relationship, namely, the X-axis moving link node is under the Y-axis moving link node, the Y-axis moving link node drives the X-axis to move together, and the same is true, and the Z-axis moving part is extracted while synchronously extracting moving link nodes comprising a main shaft, a guide rail and other structures to jointly form a link node network; then, attributes are created for each link node according to the structural characteristics, including the motion type, the motion range, the physical type, the material quality, the material density, the inertia and the like.
Secondly, from the aspect of behavior, behavior characteristics such as interfaces, signals, containers, paths, controllers, kinematic models, sensors and the like are added. Depending on the operational nature of the multi-axis automation line, the behavioral characteristics that need to be added to the multi-axis automation line model include servo controllers, signals, containers, bi-directional paths, interfaces, path sensors, actuators, process sensors, temperature sensors, and the like. Finally, from the aspect of logic, the logic program can add hidden attributes to the multi-axis automatic assembly line, so that the behavior can complete tasks only under specific conditions, such as automatic assembly operation after the temperature gradient meets the process requirements. It should be further noted that, the construction process of the remaining component models is similar to that of the multi-axis automation assembly line, and will not be repeated here, and the above models are introduced into the Visual Components environment, and the feature structure of the complete manufacturing system is maintained through the software introduction setting during the introduction.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the application, and is not meant to limit the scope of the application, but to limit the application to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the application are intended to be included within the scope of the application.
Claims (9)
1. A method of manufacturing a phased array radar module, comprising: the method comprises the following steps:
Step 1, software design, namely creating a twin model of a phased array radar module based on a digital twin technology, and designing the phased array radar module through the twin model, wherein the phased array radar module comprises an array antenna, a connector, a heat pipe, a phase shifter and a T/R unit;
Step 2, module manufacturing, namely after the step 1 is completed, simulating a manufacturing process by using a twin model, predicting and optimizing a manufacturing flow, and carrying out modularized production by using a production module;
step 3, hardware assembly, namely simulating an assembly process by using a twin model after the step 2 is completed, and assembling all modules through an assembly module to obtain the phased array radar module;
Step 4, detecting finished products, namely detecting the finished products of the phased array radar module obtained in the step 3 through a detection module;
The twin model comprises a physical layer, a twin layer and an interaction layer, wherein the physical layer corresponds to actual data information of the phased array radar module, the twin layer carries out real-time digital mapping through the actual data information acquired by the physical layer, and the physical layer and the twin layer carry out interconnection mapping and updating calculation in the interaction layer;
in the assembling process of the step 3, the temperature gradient control process under different assembling procedures is carried out through the central control module, wherein the control process is as follows: and taking the temperature information acquired by the physical layer as iteration data of the twin model, generating a temperature estimation signal by a temperature controller in the central control module based on the iteration data, and carrying out feedback adjustment according to the temperature of the temperature estimation signal.
2. A method of manufacturing a phased array radar module as claimed in claim 1, wherein: the design structure of the phase shifter in the step 1 comprises the following steps of signal connection in sequence: the input balun, the quadrature signal generator, the signal synthesizer, the output balun and the compensation amplifier, wherein a buffer is added to the output of the signal synthesizer for insertion loss compensation and impedance transformation, the signal synthesizer is also connected with a DAC (digital-to-analog converter) conversion circuit in a signal connection mode, and the DAC conversion circuit is connected with a bias circuit, a logic encoder and a switch circuit in a signal connection mode.
3. A method of manufacturing a phased array radar module as claimed in claim 1, wherein: in the step 3, the twin model is integrated with a parameter model, the parameter model is used for describing metadata samples of the phased array radar module in the twin layer, and the parameterization step of the parameter model on the metadata samples is as follows: setting model precision, determining the space variation range of assembly parameters, and generating a plurality of initial parameter samples containing space vertexes by using Latin hypercube sampling; acquiring a scattering parameter curve at the parameter sample; establishing a transfer function coefficient matrix corresponding to the assembly parameters through a scattering parameter curve based on a vector fitting algorithm; modeling the transfer function coefficient matrix by utilizing an extreme learning machine algorithm, and constructing to obtain a parameter model; and carrying out convergence judgment, searching error points in the parameter samples in the sample set, updating the sample points if the error points do not meet the model precision, and carrying out assembly if the error meets the model precision.
4. A method of manufacturing a phased array radar module as claimed in claim 1, wherein: the phased array radar module further comprises a radar cavity, a chip, a carrier plate and a base plate, and in the step 3, the assembly procedure of the phased array radar module is as follows: the method comprises the steps of sleeve alignment, cleaning, connector sintering, bottom layer array antenna and radar cavity sintering, array antenna feed spot welding, top layer array antenna and middle layer array antenna sintering, middle layer array antenna and bottom layer array antenna sintering, chip and carrier plate eutectic, carrier plate and radar cavity sintering, substrate bonding, chip bonding, PCBA mounting, gold wire bonding, phased array radar module testing, laser seal welding, array antenna three-proofing and phased array radar module retesting, and the phased array radar module finishes warehousing after retesting inspection.
5. A method of manufacturing a phased array radar module as claimed in claim 4, wherein: in the assembling procedure of the step 3, the sintering temperature of the connector is 351 ℃ to 371 ℃; the temperature interval between the bottom layer array antenna and the sintering of the radar cavity is 230-250 ℃; the temperature interval of the feed spot welding of the array antenna is 207 ℃ to 227 ℃; the sintering temperature interval of the top layer array antenna and the middle layer array antenna is 230-250 ℃; the sintering temperature interval of the middle layer array antenna and the bottom layer array antenna is 173-193 ℃; the temperature interval of eutectic of the chip and the carrier plate is 270-290 ℃; the sintering temperature interval of the carrier plate and the radar cavity is 139-159 ℃; the temperature range of gold wire bonding is 110 ℃ to 130 ℃; the temperature range for die bonding is 120 ℃ to 140 ℃.
6. A method of manufacturing a phased array radar module as claimed in claim 4, wherein: in the sintering process of the connector, the connector is installed in a welding groove, and then the welding clamp is used for synchronously limiting the connector to finish the welding process.
7. A method of manufacturing a phased array radar module as claimed in claim 4, wherein: the manufacturing process of the substrate comprises the following steps: casting, blanking and cutting, punching, filling through holes, printing a conductive medium, laminating and hot-pressing, hot cutting, discharging glue and sintering.
8. A method of manufacturing a phased array radar module as claimed in claim 4, wherein: the chip and the carrier plate are preprocessed before eutectic, and the preprocessing process is as follows: selecting a carrier substrate, performing surface treatment, and sputtering a seed layer on the front side and the back side of the carrier substrate by magnetron sputtering; performing first thick photoresist lithography on the seed layer to expose a plurality of first-stage step areas; then the carrier substrate subjected to the first thick photoresist photoetching is put into electroplating solution for electroplating treatment; carrying out second thick photoresist photoetching on the carrier plate base material after the electroplating treatment to expose a plurality of secondary steps; and electroplating the carrier plate base material subjected to the second thick photoresist photoetching to form a step structure and a concave cavity which can be matched with the chip size, and finally taking the carrier plate subjected to the preprocessing as a positioning fixture of the chip.
9. A method of manufacturing a phased array radar module as claimed in claim 8, wherein: after the preprocessing is finished, carrying out fine processing treatment on the carrier plate, wherein the fine processing treatment process is as follows: carrying out double-sided thinning leveling treatment on the prefabricated carrier plate, and polishing after the leveling treatment is finished, so that the surface roughness of the carrier plate is lower than 0.82 mu m; after the carrier plate is cleaned, carrying out surface electroplating treatment, and carrying out graphic photoetching treatment on the surface of the carrier plate after electroplating; etching the carrier plate subjected to graphic photoetching treatment to etch out a positioning graphic; and immersing the corroded carrier plate in photoresist removing liquid, and finishing fine processing of the carrier plate by a scribing technology.
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