CN118057578A - Method for manufacturing epitaxial wafer - Google Patents

Method for manufacturing epitaxial wafer Download PDF

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Publication number
CN118057578A
CN118057578A CN202311020809.6A CN202311020809A CN118057578A CN 118057578 A CN118057578 A CN 118057578A CN 202311020809 A CN202311020809 A CN 202311020809A CN 118057578 A CN118057578 A CN 118057578A
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China
Prior art keywords
wafer
process chamber
height
source gas
susceptor
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CN202311020809.6A
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Chinese (zh)
Inventor
金镇权
朴在旭
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SK Siltron Co Ltd
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LG Siltron Inc
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Publication of CN118057578A publication Critical patent/CN118057578A/en
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/14—Feed and outlet means for the gases; Modifying the flow of the reactive gases
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating
    • C30B25/165—Controlling or regulating the flow of the reactive gases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A method of manufacturing an epitaxial wafer is disclosed, the method comprising disposing a wafer on a susceptor in a process chamber, disposing the susceptor at a source gas supply height within the process chamber, supplying a source gas to grow a single crystal film on a surface of the wafer, moving the susceptor downward in the process chamber, and lowering a temperature in the process chamber to cool the wafer.

Description

Method for manufacturing epitaxial wafer
Cross Reference to Related Applications
The present application claims priority from korean patent application No. 10-2022-015607 filed on publication No. 2022, 11-21 at 2022, 35u.s.c. ≡119, which is incorporated herein by reference in its entirety as if fully set forth herein.
Technical Field
Embodiments of the present invention relate to a method of manufacturing an epitaxial wafer, and more particularly, to a method of manufacturing an epitaxial wafer, which can effectively discharge residual gas out of a process chamber when an epitaxial layer is grown on a wafer in the process chamber.
Background
Wafers widely used as semiconductor device fabrication materials may be made from a variety of materials, such as single crystal substrates including single crystal silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), and glass substrates. The wafer is produced by the following process: a slicing step of slicing a single crystal silicon ingot into thin wafers; a polishing step of polishing the wafer to a desired thickness while improving the flatness of the wafer; an etching step of removing the damaged layer of the wafer; a polishing step of polishing the surface of the wafer and improving the flatness thereof; and a cleaning process for removing contaminants from the wafer surface.
The wafer manufactured by the above process is called a polished wafer. A wafer having an epitaxial layer grown on a polished wafer is called an epitaxial wafer. Epitaxial wafers are characterized in that they have fewer surface defects than polished wafers and the concentration or type of dopants is controllable. In addition, the epitaxial wafer has advantages in that the purity of the epitaxial layer is high and the crystal characteristics of the epitaxial layer are excellent, which is advantageous in improving the yield and device characteristics of highly integrated semiconductor devices.
The epitaxial layer may be deposited using a Chemical Vapor Deposition (CVD) method. Chemical vapor deposition is a method of growing a thin material layer on a target object, such as a semiconductor wafer. Layers having different conductivities are applied to the semiconductor wafer by chemical vapor deposition to provide the semiconductor wafer with desired electrical characteristics.
A general chemical vapor deposition apparatus includes a process chamber for depositing a single crystal film, a susceptor (susceptor) installed in the process chamber, a heating lamp provided in the process chamber, and a source gas injection device configured to inject a source gas into a wafer. The source gas injected from the source gas injection device forms a single crystal film on the wafer supported on the susceptor.
However, the conventional method of depositing an epitaxial layer on a wafer has the following problems.
The source gas introduced into the process chamber of the chemical vapor deposition apparatus may remain in the process chamber even after deposition of the epitaxial layer, and may be coupled to the epitaxial layer (the surface of which is unstable at high temperature) to form fine particles. These fine particles are called Localized Light Scatterers (LLS). The wafer with fewer LLS numbers may be a wafer with fewer surface defects.
Disclosure of Invention
Embodiments of the present invention provide a method of manufacturing an epitaxial wafer with reduced surface defects, particularly improved LLS.
In one embodiment, a method of fabricating an epitaxial wafer includes: the wafer is placed on a susceptor in a process chamber, the susceptor is placed in the process chamber at a source gas supply height, the source gas is supplied to grow a single crystal film on the wafer surface, the susceptor is moved downward in the process chamber, and the temperature in the process chamber is lowered to cool the wafer.
The source gas inlet may be disposed at a first height of one sidewall of the process chamber, the purge gas inlet may be disposed at a second height of one sidewall of the process chamber, and the first height may be higher than the second height.
The gas outlet may be provided at a third height of the other sidewall of the processing chamber facing the one sidewall, and the third height may be higher than the second height.
In the cooling step, a height from the second height to the base is 32% or less of a distance from the first height to the second height.
In the cooling step, the temperature within the processing chamber may be 750 to 1000 ℃.
The cooling step may be performed for 20 seconds or more.
In the cooling step, the source gas and the purge gas may be supplied through the source gas inlet, and the purge gas may be supplied through the purge gas inlet.
The purge gas inlet may be provided in the one sidewall of the process chamber to be inclined upward with respect to the horizontal direction.
Drawings
Arrangements and embodiments may be described in detail with reference to the following drawings, wherein like reference numerals refer to like elements, and wherein:
fig. 1 is a view schematically showing a chemical vapor deposition apparatus for manufacturing an epitaxial wafer according to one embodiment;
fig. 2 is a view showing the inside of the process chamber cooled after depositing the epitaxial layer in fig. 1;
fig. 3 is a detailed view showing a positional relationship between the components in fig. 2;
Fig. 4 is a view showing the inside of a chamber in which deposition of an epitaxial layer is performed;
FIG. 5 is a diagram showing LLS on the surface of an epitaxial wafer according to the positional variation of the susceptor in FIG. 3;
FIG. 6 is a graph showing the change in LLS number according to the temperature in the process chamber at the time of cooling in FIG. 3;
FIG. 7 is a graph showing the change in LLS number according to the cooling time in the process chamber of FIG. 3; and
Fig. 8 and 9 are diagrams showing LLS of a wafer manufactured according to a manufacturing method of an epitaxial wafer.
Description of the embodiments
For a specific explanation of the present disclosure, embodiments will be described and described in detail with reference to the accompanying drawings to aid in understanding of the present disclosure.
However, the embodiments of the present disclosure may be modified in various different forms, and the scope of the present disclosure is not limited to the following embodiments. Embodiments of the present disclosure are provided solely for the purpose of more fully explaining the present disclosure to a person having a general knowledge in the technical field to which the present disclosure relates.
Furthermore, relational terms such as "first," "second," "upper," and "lower" may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements.
In a method of manufacturing an epitaxial wafer according to one embodiment, a wafer is disposed on a susceptor in a process chamber, the susceptor is disposed at a source gas supply height in the process chamber, the source gas is supplied to grow a single crystal film on a wafer surface, and a temperature of the process chamber is lowered to perform a cooling step. At this time, the susceptor in the processing chamber is moved downward.
Fig. 1 is a view schematically showing a chemical vapor deposition apparatus for manufacturing an epitaxial wafer according to one embodiment.
The chemical vapor deposition apparatus 1000 according to the present embodiment includes a transfer chamber 200, load lock chambers (load lock chamber) 300 and 400, and a process chamber 100.
A bracket 211 is formed in the transfer chamber 200, and a transfer arm 222 is installed in the bracket 211. The transfer arm 222 transfers the wafer W among the transfer chamber 200, the load lock chambers 300 and 400, and the process chamber 100.
The load lock chambers 300 and 400 may be disposed at one side of the transfer chamber 200. In general, the load lock chambers 300 and 400 may be waiting areas of the wafer W before and after the wafer is transferred to the process chamber 100 (deposition of a single crystal film is performed in the process chamber 100).
The wafer W on which the single crystal film is not deposited may be stored in the load lock chamber 300, and the wafer W on which the single crystal film is deposited may be stored in the load lock chamber 400. The process chamber 100 and the load lock chambers 300 and 400 may be respectively connected to the transfer chamber 200 through the gates G1 to G3.
The wafer W stored in the load lock chamber 300 is transferred to the process chamber 100 by the transfer arm 222. In the process chamber 100, a deposition process of a single crystal film (i.e., an epitaxial layer) is performed on a wafer W on a susceptor by a source gas.
The processing chamber 100 is coupled to one side of the transfer chamber 200 and communicates with the transfer chamber 200 through a door G. The process chamber 100 has a reaction zone 120 defined therein, a wafer W is placed in the reaction zone 120 and deposition of a single crystal film is performed, and the reaction zone 120 is defined as a sealed space by the body 110.
The process chamber 100 may be provided with a gas outlet 150 through which the source gas remaining in the reaction zone 120 after the deposition process of the single crystal film is discharged to the outside.
Fig. 2 is a view showing the inside of the process chamber cooled after depositing the epitaxial layer in fig. 1, and fig. 3 is a detailed view showing the positional relationship between the components in fig. 2.
The source gas inlet 130 may be disposed in one sidewall of the process chamber 100, and the purge gas inlet 140 may be disposed at a lower elevation. The gas outlet 150 may be provided in the other side wall opposite to the one side wall. For example, the gas outlet 150 may be located below the source gas inlet 130 and above the purge gas inlet 140.
The source gas is supplied through the source gas inlet 130. For example, the source gas may be any of various source gases containing silicon (Si), such as silicon tetrachloride (SiCl 4), trichlorosilane (SiHCl 3, trichlorosilane, TCS), dichlorosilane (SiH 2Cl2, dichlorosilane), or silane (SiH 4). In addition, the source gas may include, in part, hydrogen (H 2), which is a purge gas, which will be described below.
In addition, the source gas may be moved into the reaction zone 120 by a purge gas (or carrier gas) (e.g., hydrogen gas) and may be exhausted from the process chamber 100 through the gas outlet 150. In addition to hydrogen, the purge gas may be other inert gases, such as nitrogen (N 2) or argon (Ar).
The deposition of the single crystal film may be performed at a high temperature of, for example, 1100 ℃ or more, and a cooling process may be performed in the reaction zone 120 before the single crystal film is transferred to the outside through the gate G1 and cooled.
The cooling process may be performed at a lower temperature than the deposition process, for example, at a temperature of 750 to 1000 ℃.
At this time, the source gas introduced into the reaction zone 120 during deposition of the single crystal film may remain, and when the source gas is coupled to the unstable single crystal film on the wafer surface in a relatively high temperature state, LLS may be formed. Accordingly, in order to prevent the generation of LLS, the susceptor may be moved downward while cooling the wafer in the reaction zone 120 of the process chamber 100 such that the height of the wafer W is equal to or about equal to the height of the purge gas inlet 140, whereby contact between the residual source gas and the wafer may be reduced.
That is, referring to fig. 4 (fig. 4 shows the inside of the chamber in which epitaxial layer deposition is performed), the source gas S1 may be supplied to the wafer at a similar height to the wafer, so that the deposition process of the single crystal film is smoothly performed, and the source gas S 2 may be exhausted from the process chamber 100 through the gas outlet 150 after the end of the deposition process of the single crystal film.
During the cooling process of fig. 2, the wafer W is moved to a lower height than the deposition process of fig. 4 due to the downward movement of the susceptor. Accordingly, the source gas S remaining in the reaction zone 120 may not directly move to the wafer W but be directed toward the gas outlet 150.
Purge gas C1 supplied through the purge gas inlet 140 is directed to the wafer, and purge gas C2 around the wafer is directed to the gas outlet 150. At this time, the source gas S may also move in the direction of the gas outlet 150. For this, the purge gas inlet 140 may be provided in one sidewall of the process chamber to be inclined upward with respect to the horizontal direction. At this time, the purge gas C1 may be supplied in an upward direction with respect to the horizontal direction.
Accordingly, the possibility of supplying source gas to the wafer during the cooling process can be reduced, thereby reducing the generation of LLS.
Referring to fig. 3, it may be assumed that the center portion of the source gas inlet 130 is positioned at P1, the center portion of the purge gas inlet 140 is positioned at P2, the center portion of the gas outlet 150 is positioned at P3, and the upper surface of the susceptor on which the wafer W is positioned at Ps.
During cooling in the reaction zone 120 after deposition of the single crystal film, the center portion position P2 of the purge gas inlet 140 may be the lowest, the position Ps of the upper surface of the susceptor where the wafer W is located may be equal to or higher than P2, the center portion position P3 of the gas outlet 150 may be higher than Ps, and the center portion position P1 of the source gas inlet 130 may be higher than P3.
FIG. 5 is a diagram showing LLS on the surface of an epitaxial wafer according to the positional variation of the susceptor in FIG. 3; in fig. 5 to 8, the vertical axis represents the number of LLSs.
In fig. 5, the height (%) of the susceptor in the cooling step refers to the ratio of h2 to h1 in fig. 3. When the height (%) of the susceptor is 100, the height of the upper surface of the susceptor is equal to the height of the source gas inlet 130. When the height (%) of the susceptor is 0, the height of the upper surface of the susceptor is equal to the height of the purge gas inlet 140.
In the method of manufacturing an epitaxial wafer according to the present embodiment, the epitaxial wafer is manufactured such that the number of LLS on the wafer surface is about 5.3 per square centimeter. Thus, the height (%) of the base may be 32 or less.
Fig. 6 is a graph showing the change in LLS number according to the temperature in the process chamber at the time of cooling in fig. 3.
As can be seen from fig. 6, the number of LLS is significantly reduced when the temperature in the process chamber is 750 ℃ or higher in the cooling step. However, in consideration of the fact that the temperature of the processing chamber is 1100 ℃ or higher when depositing the epitaxial wafer, the temperature of the processing chamber during cooling may be set to 1000 ℃ or lower.
Fig. 7 is a graph showing the change in LLS number according to the cooling time in the process chamber in fig. 3. In the method of manufacturing an epitaxial wafer according to the present embodiment, when a wafer having an epitaxial layer deposited thereon is cooled in a process chamber for about 20 seconds or more, the number of LLS is less than 0.5, whereby it can be seen that the number of LLS is steadily decreasing. In addition, when a wafer having an epitaxial layer deposited thereon is cooled in a process chamber for about 10 seconds or more, the number of LLS may be 1.33 or less. It is sufficient to provide a cooling time of about 60 seconds. Here, the number of LLSs is the number of LLSs per square centimeter, as previously described.
Fig. 8 and 9 are diagrams showing LLS of a wafer manufactured according to a method of manufacturing an epitaxial wafer.
Fig. 8 shows the LLS number of the epitaxial wafer manufactured according to the comparative example (reference) and the LLS number of the epitaxial wafer manufactured according to the example (improvement). It can be seen that the LLS average value of the epitaxial wafer produced according to the example was 0.93. Here, the size of the LLS in fig. 8 and 9 may be larger than that of the LLS in fig. 5 to 7.
In fig. 9, black represents the result of LLS of the epitaxial wafer manufactured according to the comparative example measured using a Scanning Tunneling Microscope (STM), and blue represents the result of LLS of the epitaxial wafer manufactured according to the embodiment measured using the STM. It can be seen that the number of LLS on the epitaxial wafer manufactured according to the embodiment is reduced, thereby improving the quality of the epitaxial wafer.
In the method of manufacturing an epitaxial wafer according to the embodiment of the present invention, a relatively low-temperature cooling process is performed in a process chamber after depositing an epitaxial layer. At this time, the susceptor has a lower height than when the epitaxial layer is deposited, so that the source gas in the process chamber does not directly contact the wafer. Further, a purge gas is supplied above the susceptor, whereby the purge gas facilitates the discharge of the source gas. Accordingly, an increase in the number of LLS on the surface of the wafer on which the epitaxial layer is deposited due to the formation of particles can be prevented, and thus the quality of the epitaxial wafer can be improved.
As apparent from the above description, the method of manufacturing an epitaxial wafer according to one embodiment has an effect in that a relatively low temperature cooling process is performed in a process chamber after depositing an epitaxial layer, a susceptor is at a lower height than when depositing an epitaxial layer, whereby a source gas in the process chamber does not directly contact a wafer, and a purge gas is supplied above the susceptor, whereby the purge gas facilitates the discharge of the source gas, and thus an increase in the number of LLS on the surface of the wafer on which the epitaxial layer is deposited due to the formation of particles can be prevented, and the quality of the epitaxial wafer can be improved.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and may be embodied in various different forms, and it will be understood by those skilled in the art that the present disclosure may be embodied in specific forms other than the forms described herein without departing from the technical spirit and essential characteristics of the present disclosure. The disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is therefore defined by the appended claims, and it is intended that all changes or modifications derived from the meaning and scope of the claims and their equivalents be included in the scope of the present disclosure.

Claims (8)

1. A method of fabricating an epitaxial wafer, the method comprising:
disposing the wafer on a susceptor in a process chamber;
Disposing a susceptor at a source gas supply height in a process chamber, and supplying a source gas to grow a single crystal film on a surface of a wafer; and
The susceptor is moved downward in the process chamber and the temperature in the process chamber is reduced to cool the wafer.
2. The method of claim 1, wherein
A source gas inlet is provided at a first elevation of one sidewall of the process chamber,
Providing a purge gas inlet at a second elevation of said one sidewall of the process chamber, and
The first height is higher than the second height.
3. The method of claim 2, wherein
Providing a gas outlet at a third level of the other side wall of the process chamber facing the one side wall, and
The third height is higher than the second height.
4. A method according to any one of claims 1 to 3, wherein, in the cooling step, the height from the second height to the base is 32% or less of the distance from the second height to the first height.
5.A method according to any one of claims 1 to 3, wherein, in the cooling step, the temperature in the process chamber is 750 to 1000 ℃.
6. A method according to any one of claims 1 to 3, wherein the cooling step is carried out for 20 seconds or more.
7. A method according to claim 2 or 3, wherein in the cooling step, the source gas and the purge gas are supplied through the source gas inlet and the purge gas is supplied through the purge gas inlet.
8. A method as claimed in claim 2 or 3, wherein the purge gas inlet is provided in the one side wall of the process chamber to be inclined upwardly with respect to the horizontal.
CN202311020809.6A 2022-11-21 2023-08-14 Method for manufacturing epitaxial wafer Pending CN118057578A (en)

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KR10-2022-0156507 2022-11-21

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CN118057578A true CN118057578A (en) 2024-05-21

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