CN118054875A - Method and device for generating timestamp in distributed high-frequency data acquisition of distribution network - Google Patents
Method and device for generating timestamp in distributed high-frequency data acquisition of distribution network Download PDFInfo
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Abstract
The invention discloses a method and a device for generating a timestamp in distributed high-frequency data acquisition of a distribution network, wherein the method comprises the following steps: acquiring high-frequency data of a target power distribution network; performing high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode, and recording the triggering time of DMA interruption based on a GPS; performing fault detection on the high-frequency data acquired by the low-speed recording through a fault detection algorithm, and stopping the high-speed recording and the low-speed recording if faults occur; adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption; the invention realizes high-precision generation of the time stamp in high-frequency sampling through GPS time service, DMA transmission and time stamp compensation.
Description
Technical Field
The invention relates to the technical field of synchronous sampling, in particular to a method and a device for generating a timestamp in distributed high-frequency data acquisition of a distribution network.
Background
The power distribution fault distance measurement terminal detects voltage traveling waves generated during faults through high-frequency sampling, calculation and wave recording, sampling data containing voltage abrupt changes are sent to the cloud server through a wireless communication method, and fault point positioning is carried out by a cloud program through the data of the plurality of measurement terminals. Accurate positioning of fault points requires accurate, high sampling rate, high precision, time-stamped, sampled data, and complete data information to be stored. In order to improve the accuracy of positioning, in addition to the sampling rate of synchronous sampling, the synchronous accuracy of sampling between terminals must be improved, that is, the synchronism of data sampling is ensured. In general, the terminal performs time service through the GPS or the Beidou second pulse, so that the second alignment of each terminal is ensured. The terminals can set a uniform sampling frequency, but due to the influence of temperature, aging of components and the like, the actual sampling rate is often different from the set sampling rate to different degrees. There is also a deviation in the sampling timing.
The traditional method adopts an ultra-high-precision temperature compensation crystal oscillator and a high-capacity FPGA to realize a high-precision time keeping circuit and a sampling control circuit, and has the defects of complex logic circuit and high cost.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a method and a device for generating a timestamp in distributed high-frequency data acquisition of a distribution network, which solve the technical problems that the cost and complexity are increased due to the fact that the traditional method relies on lifting hardware to improve the synchronous precision of distributed sampling.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
In a first aspect, the present invention provides a method for generating a timestamp in distributed high frequency data acquisition of a distribution network, including:
Acquiring high-frequency data of a target power distribution network;
performing high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode, and recording the triggering time of DMA interruption;
performing fault detection on the high-frequency data acquired by the low-speed recording through a fault detection algorithm, and stopping the high-speed recording and the low-speed recording if faults occur;
and adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption.
Optionally, the performing high-speed recording and low-speed recording on the high-frequency data by using a DMA method includes:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting the first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area.
Optionally, after the high-speed recording area and the low-speed recording area are full, the recording is restarted from the beginning.
Optionally, adding a timestamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interrupt includes:
Taking the triggering time of corresponding half full interruption as the time stamp of the last data point in the data copied and input from the upper half area for the data copied and input from the upper half area in the high-speed recording area each time;
Calculating the time stamp of all data points in the data copied and input from the upper half area according to the time stamp of the last data point in the data copied and input from the upper half area each time;
Taking the triggering time of the corresponding full interrupt as the time stamp of the last data point in the data copied and input from the lower half area for the data copied and input from the lower half area in the high-speed recording area each time;
the time stamp of all data points in the data copied and input from the lower half area is calculated according to the time stamp of the last data point in the data copied and input from the lower half area.
Optionally, the triggering time of the DMA interrupt based on the GPS record includes:
Initializing a counter TIM5, wherein the counting pulse of the counter TIM5 is taken from the working clock passing through the PLL; the counter TIM5 works in a capturing mode, and the captured signal is PPS second pulse from GPS/Beidou;
Triggering a TIM5 interrupt in response to capturing a rising edge of PPS second pulses; the TIM5 interrupt comprises clearing interrupt bits, reading a current count value count tim5 of the counter TIM5 and marking as f sys, and clearing a current count value count tim5;
When entering the DMA interrupt, the current count value count tim5 of the counter TIM5 is read and recorded as t s, and the trigger time of the DMA interrupt is determined according to t s and UTC time information corresponding to the rising edge of PPS second pulse.
In a second aspect, the present invention provides a device for generating a timestamp in distributed high-frequency data acquisition of a distribution network, where the device includes:
the data acquisition module is used for acquiring high-frequency data of the target power distribution network;
The wave recording module is used for carrying out high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode and recording the triggering time of DMA interruption;
the wave recording stopping module is used for carrying out fault detection on the high frequency data acquired by the low-speed wave recording through a fault detection algorithm, and stopping the high-speed wave recording and the low-speed wave recording if faults occur;
and the time stamp adding module is used for adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption.
Optionally, the performing high-speed recording and low-speed recording on the high-frequency data by using a DMA method includes:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting a first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area;
and after the high-speed recording area and the low-speed recording area are fully stored each time, the high-speed recording area and the low-speed recording area are stored again from the head.
In a third aspect, the present invention provides an electronic device, including a processor and a storage medium;
The storage medium is used for storing instructions;
The processor is operative according to the instructions to perform steps according to the method described above.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method.
In a fifth aspect, the invention provides a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the method described above.
Compared with the prior art, the invention has the beneficial effects that:
according to the method and the device for generating the time stamp in the distributed high-frequency data acquisition of the distribution network, the high-precision generation of the time stamp in the high-frequency sampling is realized through GPS time service, DMA transmission and time stamp compensation.
Drawings
Fig. 1 is a flow chart of a method for generating a timestamp in distributed high-frequency data acquisition of a distribution network according to an embodiment of the present invention;
Fig. 2 is a schematic flow chart of high-speed recording and low-speed recording for the high-frequency data according to the embodiment of the present invention;
fig. 3 is a schematic structural diagram of a distributed power distribution network fault location system according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of a terminal in the fault location system according to the embodiment of the present invention;
Fig. 5 is a schematic diagram of a format of a recording file according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Embodiment one:
As shown in fig. 1, the embodiment of the invention provides a method for generating a timestamp in distributed high-frequency data acquisition of a distribution network, which comprises the following steps:
and S1, acquiring high-frequency data of a target power distribution network.
S2, performing high-speed recording and low-speed recording on the high-frequency data by adopting a DMA mode, and recording the triggering time of DMA interruption;
as shown in fig. 2, the high-speed recording and the low-speed recording of the high-frequency data by using the DMA method include:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting the first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area.
And after the high-speed recording area and the low-speed recording area are fully stored each time, the high-speed recording area and the low-speed recording area are stored again from the head.
The triggering time of recording the DMA interrupt based on the GPS comprises the following steps:
Initializing a counter TIM5, wherein the counting pulse of the counter TIM5 is taken from the working clock passing through the PLL; the counter TIM5 works in a capturing mode, and the captured signal is PPS second pulse from GPS/Beidou;
Triggering a TIM5 interrupt in response to capturing a rising edge of PPS second pulses; the TIM5 interrupt comprises clearing interrupt bits, reading a current count value count tim5 of the counter TIM5 and marking as f sys, and clearing a current count value count tim5;
When entering the DMA interrupt, the current count value count tim5 of the counter TIM5 is read and recorded as t s, and the trigger time of the DMA interrupt is determined according to t s and UTC time information corresponding to the rising edge of PPS second pulse.
Step S3, performing fault detection on the high-frequency data acquired by the low-speed recording through a fault detection algorithm, and stopping the high-speed recording and the low-speed recording if faults occur;
S4, adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption; the method specifically comprises the following steps:
Taking the triggering time of corresponding half full interruption as the time stamp of the last data point in the data copied and input from the upper half area for the data copied and input from the upper half area in the high-speed recording area each time;
Calculating the time stamp of all data points in the data copied and input from the upper half area according to the time stamp of the last data point in the data copied and input from the upper half area each time;
Taking the triggering time of the corresponding full interrupt as the time stamp of the last data point in the data copied and input from the lower half area for the data copied and input from the lower half area in the high-speed recording area each time;
the time stamp of all data points in the data copied and input from the lower half area is calculated according to the time stamp of the last data point in the data copied and input from the lower half area.
As shown in fig. 3, the embodiment of the invention provides a structural schematic diagram of a distributed power distribution network fault location system; the termination in fig. 3 is a measurement device mounted at the beginning end of the line and at the bifurcation site, typically on a transformer stand, with the operating power taken from the low voltage side of the transformer. The hardware principle of the terminal is shown in fig. 4, and the terminal comprises a CPU, a 3-path CVT voltage transformer, a signal conditioning circuit, a GPS signal receiving module, a communication module and a crystal oscillator. The CVT voltage transformer is a transient capacitive voltage division type sensor adopting a last screen principle, is used for converting a high-voltage signal about 6kV to the ground into a small voltage signal of a few volts, has a bandwidth of more than 1MHz, and can be used for measuring the transient voltage of the line fault of the power distribution network. The signal conditioning circuit is used for filtering and isolating signals. The GPS signal receiving module is used for receiving a pulse per second signal (PPS) of GPS/Beidou and UTC time information. The communication module is used for uploading the wave recording file with the time stamp to the cloud server. The crystal oscillator provides the CPU with the clock frequency necessary for operation.
The CPU adopts a singlechip with the working frequency of 480MHz, the crystal oscillator is 25MHz, and the system clock with the frequency of 480MHz is obtained after internal PLL frequency multiplication.
The terminal needs to collect voltage waveforms of 3 channels, and the sampling frequency is set to be 1MHz. The singlechip is internally provided with 3 AD converters, and can collect data of 3 channels simultaneously. The singlechip directly carries the ADC result to a DMA buffer area in a DMA mode. The program opens up a DMA buffer zone with 2000 x 3 points, which can store 2ms sampling data, the buffer zone is divided into an upper zone and a lower zone, and each half zone can store 1ms data. In the program, 2 DMA interrupts are enabled, full interrupt and half full interrupt, respectively. When the data in the upper half area is full, a half full interrupt is triggered, in the half full interrupt, the program copies the data in the upper half area to the high-speed recording area in an M2M DMA mode, and at the moment, the data of the ADC can be continuously transported to the lower half area. When the data in the lower half area is full, the full interrupt is triggered, and in the full interrupt, the program copies the data in the lower half area to the high-speed recording area in an M2M DMA mode, and at the moment, the data of the ADC are transported to the upper half area.
When the data in the high-speed recording area is full, the data is stored again from the head. That is, the last 40ms of data is always reserved in the high-speed recording area. In this way, high-speed wave recording for high-speed data acquisition is realized. At the entry of the full interrupt and the half interrupt, the time at that time is recorded as the sampling time of the last data.
In addition, the high-speed recording and the low-speed recording are performed simultaneously. The sampling rate of the low-speed wave recording is 1ksps, the total wave recording length is 50ms, and the method is used for a fault starting algorithm of the CPU to judge whether a fault occurs at present. If the fault occurs, the DMA operation is stopped immediately, and the data of the ADC is not updated to the high-speed recording area, so that the high-speed recording data in the fault is reserved.
And determining the fault position by measuring the moment when the traveling wave reaches each monitoring terminal.
In order to calculate the position of the fault point, the cloud program calculates waveform data sent by each terminal, finds the accurate time of arrival of the traveling wave head, and the error is not more than 0.1us. In order to meet the above requirements, the present example takes the following three measures.
1. The terminal adopts a receiving module based on a GPS/Beidou time setting system, and the module can count PPS second pulse and UTC time. On the basis of a PPS place, the singlechip generates a time reference with the precision of 0.1us in a counting mode. The reference and the UTC time from GPS combine to form a time stamp that can be used to time stamp the sampled data.
2. And the constant-temperature crystal oscillator is adopted, so that sampling frequency deviation caused by frequency deviation of the crystal oscillator is reduced. In order to save the cost, the terminal adopts a constant-temperature crystal oscillator with lower precision, the normal-temperature frequency difference is 0.2ppm, the temperature frequency difference is 0.5ppm, and the precision can not meet the requirement of traveling wave ranging, so that the terminal also needs to adopt software measures to compensate.
3. And measuring the frequency of the system clock by using a counter TIM5, uploading the frequency value to the cloud together with the recording data, and compensating the sampling time of the recording data of each terminal at the cloud.
The process is as follows:
A counter TIM5 is initialized, the counting pulse is taken from the working clock after passing through the PLL, the standard value is 240MHz, and the frequency of the clock has certain deviation due to the influence of the initial precision and the temperature of the crystal oscillator. The counter TIM5 is configured to operate in a capture mode, the captured signal being PPS seconds pulses from GPS with an error of 10ns.
The role of the counter TIM5 is two: the first is to calculate the frequency of the system clock in the capture interrupt, and the second is that the count value can be used as a source of the 0.1us reference value.
During operation, when a PPS rising edge comes, the TIM5 interrupt is triggered. The interrupt bit is cleared first during an interrupt, the current count value count tim5 of TIM5 is read and noted as f sys, and the current count value is cleared immediately. The frequency of the system bus clock should be 240M, denoted as f sys0. Meanwhile, the value of count tim5/24 is the count pulse with resolution of 0.1us, and can be used as a time stamp of sampling.
The trigger period for both half full interrupt and full interrupt is 2ms. After the interrupt is entered, the value of the current count value count tim5 is first read and stored in the timestamp array, then the DMA in M2M mode is started, the data in the corresponding half area is carried to the cache area, and finally the first data point is required to be stored in the low-speed recording area.
In the running process of the program, the starting algorithm calculates the data of the low-speed wave recording area once every 2ms, and when a fault is detected, the DMA operation is immediately stopped, and at the moment, the waveform data of the traveling wave head is already stored in the high-speed wave recording area.
As shown in fig. 5, in the recording file, the file header includes basic information such as a file name, device information, geographical coordinates, etc., followed by a terminal clock frequency, a time stamp array, and high-speed recording data, and the total length of the recording area data is 40us, which is divided into 40 areas. Each region corresponds to one upper half or lower half of the DMA. The timestamp of the last data point of each partition is recorded in timestamp array t s.
Taking sample area 0 as an example, 1000 sampling points are marked as y 0-y 999, and the time of each sampling point is compensated according to the following formula, and the time of the ith data point of sample area 0The method comprises the following steps:
After the compensation is carried out according to the method, the precision of the time stamp of the sampling point can be controlled within 0.1us, thereby meeting the requirement of travelling wave ranging.
Embodiment two:
the embodiment of the invention provides a device for generating a timestamp in distributed high-frequency data acquisition of a distribution network, which comprises the following components:
the data acquisition module is used for acquiring high-frequency data of the target power distribution network;
The wave recording module is used for carrying out high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode and recording the triggering time of DMA interruption;
the wave recording stopping module is used for carrying out fault detection on the high frequency data acquired by the low-speed wave recording through a fault detection algorithm, and stopping the high-speed wave recording and the low-speed wave recording if faults occur;
and the time stamp adding module is used for adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption.
Specifically, the performing high-speed recording and low-speed recording on the high-frequency data by using the DMA method includes:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting a first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area;
and after the high-speed recording area and the low-speed recording area are fully stored each time, the high-speed recording area and the low-speed recording area are stored again from the head.
Embodiment III:
based on the first embodiment, the embodiment of the invention provides electronic equipment, which comprises a processor and a storage medium;
The storage medium is used for storing instructions;
The processor is operative according to the instructions to perform steps according to the method described above.
Embodiment four:
based on the first embodiment, the embodiment of the present invention provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the above method.
Fifth embodiment:
based on an embodiment one, an embodiment of the present invention provides a computer program product comprising a computer program/instruction which, when executed by a processor, implements the steps of the above method.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. The method for generating the timestamp in the distributed high-frequency data acquisition of the distribution network is characterized by comprising the following steps of:
Acquiring high-frequency data of a target power distribution network;
Performing high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode, and recording the triggering time of DMA interruption based on a GPS;
performing fault detection on the high-frequency data acquired by the low-speed recording through a fault detection algorithm, and stopping the high-speed recording and the low-speed recording if faults occur;
and adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption.
2. The method for generating the timestamp in the distributed high-frequency data acquisition of the distribution network according to claim 1, wherein the performing high-speed recording and low-speed recording on the high-frequency data in a DMA manner comprises:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting the first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area.
3. The method for generating a timestamp in distributed high frequency data collection of a distribution network as recited in claim 2, wherein the high speed recording area and the low speed recording area are stored again from the beginning after each full time.
4. The method for generating a timestamp in distributed high frequency data acquisition of a distribution network according to claim 2, wherein adding a timestamp to the high frequency data acquired by the high speed recorder according to the trigger time of the DMA interrupt comprises:
Taking the triggering time of corresponding half full interruption as the time stamp of the last data point in the data copied and input from the upper half area for the data copied and input from the upper half area in the high-speed recording area each time;
Calculating the time stamp of all data points in the data copied and input from the upper half area according to the time stamp of the last data point in the data copied and input from the upper half area each time;
Taking the triggering time of the corresponding full interrupt as the time stamp of the last data point in the data copied and input from the lower half area for the data copied and input from the lower half area in the high-speed recording area each time;
the time stamp of all data points in the data copied and input from the lower half area is calculated according to the time stamp of the last data point in the data copied and input from the lower half area.
5. The method for generating a timestamp in distributed high frequency data collection of a distribution network according to claim 1, wherein the triggering time based on the GPS record DMA interrupt comprises:
Initializing a counter TIM5, wherein the counting pulse of the counter TIM5 is taken from the working clock passing through the PLL; the counter TIM5 works in a capturing mode, and the captured signal is PPS second pulse from GPS/Beidou;
Triggering a TIM5 interrupt in response to capturing a rising edge of PPS second pulses; the TIM5 interrupt comprises clearing interrupt bits, reading a current count value count tim5 of the counter TIM5 and marking as f sys, and clearing a current count value count tim5;
When entering the DMA interrupt, the current count value count tim5 of the counter TIM5 is read and recorded as t s, and the trigger time of the DMA interrupt is determined according to t s and UTC time information corresponding to the rising edge of PPS second pulse.
6. A device for generating a timestamp in distributed high frequency data collection of a distribution network, the device comprising:
the data acquisition module is used for acquiring high-frequency data of the target power distribution network;
the wave recording module is used for carrying out high-speed wave recording and low-speed wave recording on the high-frequency data in a DMA mode and recording the triggering time of DMA interruption based on a GPS;
the wave recording stopping module is used for carrying out fault detection on the high frequency data acquired by the low-speed wave recording through a fault detection algorithm, and stopping the high-speed wave recording and the low-speed wave recording if faults occur;
and the time stamp adding module is used for adding a time stamp to the high-frequency data acquired by the high-speed recording according to the triggering time of the DMA interruption.
7. The apparatus for generating a timestamp in distributed high frequency data acquisition of a distribution network as claimed in claim 1, wherein said DMA mode for high speed recording and low speed recording of said high frequency data comprises:
Dividing the DMA buffer zone into an upper half zone and a lower half zone, wherein the DMA interrupt comprises a full interrupt and a half full interrupt, and the following steps are circularly executed:
Inputting the high frequency data into the upper half area, and triggering the half-full interrupt when the upper half area is full; the half full interrupt comprises copying and inputting a first data in the data stored in the upper half area into a low-speed recording area, and copying and inputting the data stored in the upper half area into a high-speed recording area;
Inputting the high-frequency data into the lower half area, and triggering the full interrupt when the lower half area is full; the full interrupt comprises copying and inputting a first data in the data stored in the lower half area into a low-speed recording area, and copying and inputting the data stored in the lower half area into a high-speed recording area;
and after the high-speed recording area and the low-speed recording area are fully stored each time, the high-speed recording area and the low-speed recording area are stored again from the head.
8. An electronic device, comprising a processor and a storage medium;
The storage medium is used for storing instructions;
The processor being operative according to the instructions to perform the steps of the method according to any one of claims 1-5.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the method according to any one of claims 1-5.
10. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of any of claims 1-5.
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