CN118051389A

CN118051389A - Communication processor testing method and device, electronic equipment and storage medium

Info

Publication number: CN118051389A
Application number: CN202410030531.9A
Authority: CN
Inventors: 么鹏; 沈郁博; 韩滔; 郭晗; 孔笑荷
Original assignee: CASIC Defense Technology Research and Test Center
Current assignee: CASIC Defense Technology Research and Test Center
Priority date: 2024-01-08
Filing date: 2024-01-08
Publication date: 2024-05-17

Abstract

The application provides a test method and device of a communication processor, electronic equipment and a storage medium: the test time sequence of the test item can be determined according to the test content; repeated testing can be avoided by determining the test time sequence, and further the test efficiency is improved. Determining a test stimulus corresponding to each test item; applying test excitation to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test excitation is applied; according to the test time sequence, the comprehensive and efficient performance test is realized by applying different stimuli to different test items. And judging the qualification of the test item according to the preset expected response and the test response, and obtaining a test result. And (3) obtaining a test result for evaluating the performance of the communication processor by analyzing the qualification of each test item, so as to realize automatic and efficient test of the communication processor.

Description

Communication processor testing method and device, electronic equipment and storage medium

Technical Field

The present application relates to the field of performance testing technologies, and in particular, to a method and apparatus for testing a communication processor, an electronic device, and a storage medium.

Background

Processors employing the PowerPC architecture have very wide applications in network communications applications, industrial control applications, home digitizing, network storage, military applications, power system control, and the like, due to their excellent performance and highly integrated and technically advanced features. However, since the PowerPC architecture processor is relatively expensive compared to the ARM architecture processor, the popularity of the PowerPC architecture processor is poor, and thus, a test method for a processor adopting the PowerPC architecture is lacking.

Disclosure of Invention

In view of the above, the present application provides a method, an apparatus, an electronic device and a storage medium for testing a communication processor, which are used for implementing efficient testing of a Power-PC architecture processor.

Based on the above object, a first aspect of the present application provides a method for testing a communication processor, including:

Acquiring test content, and determining a test time sequence of the test item according to the test content;

Determining test stimulus corresponding to each test item;

Applying the test stimulus to the communication processor according to the test time sequence, and capturing a test response of the communication processor after the test stimulus is applied;

And judging the qualification of the test item according to a preset expected response and the test response to obtain a test result.

A second aspect of the present application provides a test apparatus for a communication processor, comprising:

The time sequence determining module is respectively configured to: acquiring test content, and determining a test time sequence of the test item according to the test content;

The excitation determining module is configured to: determining test stimulus corresponding to each test item;

The response capturing module is respectively configured to: applying the test stimulus to the communication processor according to the test time sequence, and capturing a test response of the communication processor after the test stimulus is applied;

the result determining module is configured to: and judging the qualification of the test item according to a preset expected response and the test response to obtain a test result.

A third aspect of the application provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method as provided in the first aspect of the application when executing the program.

A fourth aspect of the application provides a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method provided by the first aspect of the application.

From the above, it can be seen that the test method, apparatus, electronic device and storage medium for a communication processor provided by the present application: the test time sequence of the test item can be determined according to the test content; repeated testing can be avoided by determining the test time sequence, and further the test efficiency is improved. Determining a test stimulus corresponding to each test item; applying test excitation to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test excitation is applied; according to the test time sequence, the comprehensive and efficient performance test is realized by applying different stimuli to different test items. And judging the qualification of the test item according to the preset expected response and the test response, and obtaining a test result. And (3) obtaining a test result for evaluating the performance of the communication processor by analyzing the qualification of each test item, so as to realize automatic and efficient test of the communication processor.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a hardware structure of a machine test system according to an embodiment of the present application;

FIG. 2 is a flow chart of a testing method of a communication processor according to an embodiment of the application;

FIG. 3 is a flow chart of determining test timing of test items according to an embodiment of the present application;

FIG. 4 is a flow chart of determining test stimulus according to an embodiment of the present application;

FIG. 5 is a flow chart of capturing test responses according to an embodiment of the present application;

FIG. 6 is a flowchart of a method for performing eligibility determination according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating different actions performed under different capture conditions according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a testing device of a communication processor according to an embodiment of the present application;

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the application.

Detailed Description

The present application will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

In this document, it should be understood that any number of elements in the drawings is for illustration and not limitation, and that any naming is used only for distinction and not for any limitation.

Based on the above description of the background art, there are also the following cases in the related art:

The PowerPC architecture processor has high integration degree compared with the ARM architecture processor, and has large chip selectable range, high performance and easy upgrading.

The positioning of the PowerPC architecture processor relative to the ARM architecture processor is different: the ARM architecture processor is oriented to a low-end consumer market, and has the advantages of low power consumption; the PowerPC architecture processor is oriented to the middle-high end market, and has the advantage of good performance. The application of the PowerPC architecture processor in the embedded field is in a middle-high end scene, so the PowerPC architecture processor is mainly used for application equipment such as switches, network processors, high-end game machines and the like, the performance requirements of the application equipment on the processor are very strong, the products are all power supplies of independent AC/DC, and a fan is generally arranged in a case. Power consumption should not be a problem.

ARM architecture processors are all consumer electronics oriented mobile terminals such as mobile phones, notebook computers and the like. The advantages of ARM in the consumer electronics field are very clear for three reasons: low price, complete matching IP and convenient integration and use.

The automated test equipment ATE (Automatic Test Equipment) tests the object under test by means of a computer-controlled test instrument. The manual test is replaced by computer programming, the instrument is controlled based on a test program, and input and output signal detection analysis is carried out on the to-be-tested product, so that whether the performance of the to-be-tested product meets the requirement is judged. The ATE test needs to design a test program according to a test target and a project, prepare a test instrument used for the test, such as an oscilloscope, a universal meter, a spectrum analyzer and the like, connect the test instrument with a to-be-tested product, control and test the test by ATE test equipment, and perform system analysis on a test result to generate a data report. Compared with manual testing, ATE testing has high efficiency, high reliability, high accuracy and high repeatability, is the most common testing mode in the electrical testing industry, and is widely applied to the fields of electronic manufacturing industry and electronic product research and development. However, ATE test equipment cannot be directly applied to automated and efficient testing of a PowerPC architecture processor due to problems such as interface and program suitability. However, the efficiency of manual testing is too low, so an automatic test method applied to the processor of the PowerPC architecture is needed.

The test method, the device, the electronic equipment and the storage medium of the communication processor can determine the test time sequence of the test item according to the test content; repeated testing can be avoided by determining the test time sequence, and further the test efficiency is improved. Determining a test stimulus corresponding to each test item; applying test excitation to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test excitation is applied; according to the test time sequence, the comprehensive and efficient performance test is realized by applying different stimuli to different test items. And judging the qualification of the test item according to the preset expected response and the test response, and obtaining a test result. And (3) obtaining a test result for evaluating the performance of the communication processor by analyzing the qualification of each test item, so as to realize automatic and efficient test of the communication processor.

A test method of a communication processor according to an exemplary embodiment of the present application is described below with reference to the accompanying drawings.

In some embodiments, the test method of the communication processor is applied to a machine test system, and the machine test system consists of hardware and software. As shown in fig. 1, the hardware part mainly includes a test socket 1, a test board 2, a test accompanying circuit in the test board, a test head 3 and a test server 4, a test program is stored in the test server 4, test data are interacted with the test head 3 through optical fibers, test resources in the test head 3 are scheduled, and the test of the processor is completed through the test board and the test socket 1. The machine test system is based on an ATE test machine for program development, a test program software part comprises a test program and a test vector set, the test program is stored in a test server 4 in a code form, the test server 4 realizes a test method of a communication processor by executing the test program code, realizes test resource scheduling, completes test behaviors, and the test vector defines expected responses of input signal test excitation and output signals.

Wherein the test board card 2 is used for realizing electrical connection between the test resources and the devices. On the one hand, the test board card 2 is connected with the test resources in the 93000 system through the Pogo Pin, and on the other hand, the test board card 2 is connected with the processor to be tested through the test socket 1. The test head 3 mounts necessary test boards 2, such as a power board, a clock board, a digital channel board, etc., according to the test requirements. Taking a to-be-tested processor as an XYP8377 type multipurpose communication processor as an example, the XYP8377 power pins are respectively connected into 8 power channels (used for connecting 8 MSDPS power supplies) of the test socket 1 according to a voltage domain, so as to provide 1.1V nuclear power for the to-be-tested processor; 2.5V DDR PLL power supply; DDR SDRAM I/O power supply at 1.8V; eTSEC1I/O power supply at 2.5V or 3.3V; serDes1 simulates a high power supply or SerDes2 simulates a high power supply; 1.1V PLL analog power supply; a SerDes1 digital power supply, a SerDes2 digital power supply, a SerDes1 IO power supply, or a SerDes2IO power supply; 3.3V IO signal power.

Since the XYP8377 processors have more power rails, the same voltage power rails are combined. The clock design adopts two connection modes, one is a digital channel connected to the machine test system, the machine test system provides clock signals, the other is an external crystal oscillator provides clock signals, the crystal oscillator is powered by an ASM1117 power supply conversion chip, and the two modes can be switched by the machine test system through a relay. The testing process mainly comprises the steps that a testing program schedules testing resources, test excitation is applied to input signals of the processor to be tested through the testing board card 2, responses of output signals are captured, and behaviors of the processor to be tested in processing responses are analyzed.

In addition, the connection between the processor to be tested and the test board 2 requires an additional custom-made special test socket 1 on the test board 2. The test socket 1 is not only adapted to the packaging form of the to-be-tested processor, but also more importantly, the signal connection between the to-be-tested processor and the test board card 2 can be conveniently realized, and in the selection of the test socket 1, the heat dissipation problem of the to-be-tested processor needs to be considered.

The software design mainly comprises test programming and debugging, and the XYP8377 test program mainly comprises a test vector set, a test code set, a test flow and the like. The test flow is composed of a plurality of test items, the sequence of the test items determines the chip test flow, and each test item is configured with a corresponding test vector, test code, test voltage and test time sequence according to test content, namely, each test item corresponds to at least one test vector, so that one or more electrical performance parameter test tasks in the test content are realized.

The test vector set consists of several test vectors, and the test vector generating process is based on the behavior model of the tested device, and the VCD waveform is simulated in testbench to describe the time of the input signal to apply excitation, the time of the output signal to output expected output response, and the test program completes the application of test excitation and the capture of test response via the machine test system based on the signal waveform defined by the test vector.

The software design mainly comprises the processes of test resource planning, test vector conversion, test subprogram code programming and debugging, test procedure programming and debugging, test item function debugging, test item parameter debugging, test program solidifying and the like, the test programs can completely cover the electrical performance parameter test requirements in the test detail gauge, the test programs are stored in the test server 4 in a code form, the test server 4 realizes the test method of the communication processor by executing the test program codes, realizes test resource scheduling, and completes test behaviors.

In some embodiments, as shown in fig. 2, a method for testing a communication processor includes:

step 201: and acquiring test contents, and determining the test time sequence of the test item according to the test contents.

In specific implementation, the test contents include test categories determined according to the needs of the user, and illustratively, the test contents can be divided into 8 test categories: connectivity test, function test, DC parameter test, power consumption test, I2C port AC parameter test, SPI port AC parameter test, JTAG port AC parameter test, RGMII port AC parameter test. The 8 test categories almost comprise each electrical performance parameter test task of the communication processor, and if a user needs additional test items, the corresponding test items can be actively added in the initiative of the test content. The test items are configured with corresponding test vectors, test codes, test voltages and test time sequences according to the test content, and are used for testing one or more electric performance parameter test tasks.

Therefore, the sequence of the test items determines the test flow of the chip, and the test time sequence of the test items can avoid repeated tests, for example, under different test scenes, the test items corresponding to the first time sequence in the test time sequence are all connectivity test items, and the test purpose of the connectivity test items is to determine the differential pressure of the ESD diode of the IO pin of the communication processor to be measured, so as to determine whether the contact between the communication processor to be measured and the test socket, and between the test socket and the test board card is good, and avoid abnormal test parameters caused by poor contact. If the test of the connectivity test item is not performed first, and if the test failure occurs in other subsequent test items, it cannot be determined whether the test failure occurs due to poor contact between different devices, so that the test of the corresponding test item needs to be performed again after the test item is determined to be qualified, and repeated test is caused, so that the test item before in the test sequence is generally associated with the other test item, and on the premise of meeting the test content, the test item with fewer associated test items is relatively more rearward.

Step 202: test stimulus corresponding to each test item is determined.

In specific implementation, the test vector set consists of a plurality of test vectors, the test vectors describe when and what kind of excitation is applied to the input signals, when and what kind of expected output response is output to the output signals, and the test program completes the application of test excitation and the capture of test response through the machine test system according to the signal waveforms defined by the test vectors. Therefore, as long as the test vector corresponding to the test item is determined, the corresponding test stimulus, and the application time of the test stimulus, can be determined.

Step 203: and applying test stimulus to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test stimulus is applied.

In specific implementation, the test of the test items is sequentially performed according to the test time sequence, and it is assumed that the test response of the test item 1 is captured at the current moment, the test of the test item 1 is ended, the test of the test item 2 is continued, at this time, the type of test excitation and the application time of the test excitation are determined according to the test vector 2 corresponding to the test item 2, and then, after the application time is reached, the corresponding type of test excitation is applied to the communication processor. After receiving the test excitation as an input signal, the communication processor to be tested outputs a test response as an output signal, and sends the test response to the machine test system until the machine test system captures the test response of the communication processor after the test excitation is applied, and sequentially continuing the test of the next test item according to the test time sequence, and stopping the test if the next test item is not available. According to the test time sequence, the comprehensive and efficient performance test is realized by applying different stimuli to different test items.

Step 204: and judging the qualification of the test item according to the preset expected response and the test response, and obtaining a test result.

In particular embodiments, the set of test vectors consists of a number of test vectors describing when and what stimulus is applied to the input signal and when and what desired output response is output by the output signal. Therefore, as long as the test vector corresponding to the test item is determined, the corresponding expected response can be determined. The expected response indicates an expected value range corresponding to the target parameter to be tested in the test item when the communication processor to be tested does not have a fault, namely if the test value of the target parameter in the test response is in the expected value range, the corresponding test item is determined to be qualified; if the test value of the target parameter in the test response is outside the expected value range, determining that the corresponding test item is not qualified.

If the lower boundary value of the expected value range is smaller than or equal to the test value of the target parameter and smaller than or equal to the upper boundary value of the expected value range, determining that the test value of the target parameter is within the expected value range, otherwise, determining that the test value of the target parameter is outside the expected value range.

In summary, the test method of the communication processor provided by the application can determine the test time sequence of the test item according to the test content; repeated testing can be avoided by determining the test time sequence, and further the test efficiency is improved. Determining a test stimulus corresponding to each test item; applying test excitation to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test excitation is applied; according to the test time sequence, the comprehensive, efficient and accurate electrical performance parameter test is realized by applying different excitations to different test items. And judging the qualification of the test item according to the preset expected response and the test response, and obtaining a test result. And by analyzing the qualification of each test item, a test result for evaluating the performance of the communication processor is obtained, so that the communication processor is automatically and efficiently tested.

In some embodiments, as shown in fig. 3, determining a test timing of a test item according to test content includes:

Step 301: and determining a class time sequence of the test class according to the test content.

In particular, the test content may be divided into 8 test categories, for example: connectivity test, function test, DC parameter test, power consumption test, I2C port AC parameter test, SPI port AC parameter test, JTAG port AC parameter test, RGMII port AC parameter test. The 8 test categories almost comprise each electrical performance parameter test task of the communication processor, and if a user needs additional test items, the corresponding test items can be actively added in the initiative of the test content. The class timing sequence of the test class and the test item corresponding to each test class are shown in table 1:

The test device comprises a test device, a test device and a test system, wherein the test device comprises a connectivity test, a function test, a direct current parameter test, a power consumption test, an I2C port alternating current parameter test, an SPI port alternating current parameter test, a JTAG port alternating current parameter test and an RGMII port alternating current parameter test from front to back in sequence. And corresponding test items can be added or reduced in each test category according to user requirements.

Step 302: and determining the arrangement sequence of at least one test item in each test category according to the test content.

In particular, the arrangement order of the test items in the test category can be obtained according to table 1, for example, in the dc parameter test, the arrangement order of the test items is the input high level voltage (V _IH), the input low level voltage (V _IL), the output high level voltage (V _OH), and the output low level voltage (V _OL).

Step 303: and determining the test time sequence of the test items according to the category time sequence and the arrangement order.

In specific implementation, the test categories are ordered according to the category time sequence, and then the test time sequence of all the test items is determined according to the arrangement sequence of the test items in each test category.

For example, the functional test is preferably performed before the dc parameter test, and the test items are arranged in the order of low-voltage condition test function_v _DDmin, normal-voltage condition test function_v _DDnom, and high-voltage condition test function_v _DDmax, and then the dc parameter test is performed, and the test items are arranged in the order of input high-level voltage V _IH, input low-level voltage V _IL, output high-level voltage V _OH, and output low-level voltage V _OL. The total test timing is low voltage condition test function_v _DDmin, normal voltage condition test function_v _DDnom, high voltage condition test function_v _DDmax, input high voltage V _IH, input low voltage V _IL, output high voltage V _OH, output low voltage V _OL.

In some embodiments, as shown in FIG. 4, determining the test stimulus corresponding to each test item includes:

Step 401: a set of test vectors corresponding to the test categories is determined.

In specific implementation, the test vector set is composed of a plurality of test vectors, the generation process of the test vectors is based on a behavior model of a device to be tested, and the VCD waveform generated in a simulation mode in testbench describes when an input signal is applied with any excitation, when an output signal outputs any expected output response, and the test program completes application of test excitation and capture of test response through a machine test system according to the signal waveform defined by the test vectors.

Step 402: and determining test vectors corresponding to the test items in the vector set according to the arrangement sequence.

In particular, the test vector corresponding to the input high-level voltage in the dc parameter test is illustratively Function. Indicating that the power supply is supplying power normally, the machine test system provides a 33MHz master clock.

Step 403: test stimulus corresponding to the test item is determined by reading the test vector.

In specific implementation, the running test vector enters a test state, and test excitation corresponding to the test item is determined by reading the test vector.

In some embodiments, as shown in fig. 5, applying test stimulus to the communication processor according to the test timing and capturing test response of the communication processor after applying the test stimulus includes:

Step 501: and determining a target test item according to the test time sequence, and determining a target test vector corresponding to the target test item.

In specific implementation, since the test time sequence is generally the connectivity test item arranged in the first time sequence, when the connectivity test item is the target test item, the test purpose is to measure the PN junction voltage of the ESD diode of the IO pin of the communication processor to be tested, and determine whether the communication processor to be tested is well contacted with the machine test system. Belongs to a guarantee test to ensure the proceeding of the subsequent test, so that the corresponding target test vector is empty.

Step 502: and determining target test excitation corresponding to the target test item according to the target test vector, and applying the target test excitation to the communication processor.

In particular, if the target test stimulus corresponding to the connectivity test item is-100 uA current, the test vector is sent to the communication processor when the test is performed, and when the communication processor runs the test vector, the test item test starts and-100 uA current is applied to the communication processor.

Step 503: a target test response of the communication processor for the target test stimulus is captured.

In specific implementation, after-100 uA current is applied to a communication processor to be tested, the PN junction voltage of the ESD protection diode is detected, and if the voltage value is between-1100 mV and-100 mV, the connectivity test is qualified.

In some embodiments, as shown in fig. 6, the test item qualification is determined according to a preset expected response and a test response, so as to obtain a test result, including:

Step 601: target parameters for evaluating the test response are determined.

In specific implementation, taking connectivity test as an example, the test item is a connectivity test item, and the target parameter for judging the test response is to measure the PN junction voltage of the ESD diode of the IO pin of the communication processor to be tested. Among them, the PN junction is a junction composed of an n-type semiconductor and a p-type semiconductor, in which electrons and holes are diffused each other until an equilibrium state is reached.

Step 602: and determining the expected value range of the target parameter according to the expected response.

In specific implementation, the expected value range can be-1100 mV to-100 mV.

Step 603: and determining the test value of the target parameter according to the test response.

In specific implementation, PN junction voltage of an ESD diode of an IO pin of a communication processor to be tested is measured to obtain test response, and then a test value of a target parameter is determined.

Step 604: and determining the qualification judgment result of the test item according to the expected value range and the test value.

In particular, step 604 includes:

step 6041: and determining that the qualification judgment result of the test item is qualified in response to the test value being in the expected value range.

In the specific implementation, if the test value is-1000 mV, -1100mV < -1000mV < -100mV, the test value is in the expected value range, and the qualification judgment result of the test item is determined to be qualified.

Step 6042: and determining that the qualification judgment result of the test item is unqualified in response to the test value being out of the expected value range.

In specific implementation, if the test value is-1200 mV, -1200mV < -1100mV, and the test value is outside the expected value range, determining that the qualification judgment result of the test item is unqualified.

Step 605: and integrating the qualification judgment results of all the test items to obtain a test result.

And in specific implementation, integrating the qualification judgment results of all the test items to obtain test results including whether all the tests are qualified or not, and judging the performance of the communication processor to be tested.

In some embodiments, as shown in fig. 7, the method for testing a communication processor further includes:

step 701: and responding to the condition that the target test response is not captured, and carrying out alarm prompt.

In the specific implementation, if the target test response is not captured after the test excitation is applied, the communication processor to be tested is indicated to have serious problems or test faults, and alarming prompt is carried out to prompt staff to overhaul.

Step 702: in response to capturing the target test response, testing of the next test item is performed according to the test timing after capturing the target test response.

In the specific implementation, if the target test response is successfully captured after the test stimulus is applied, the completion of the test of the target test item is indicated, and the test of the next test item is carried out according to the test time sequence.

In some embodiments, exemplary, the testing of test items in a test type is as follows

1. Connectivity test, including connectivity test items

Test purpose: and measuring the PN junction voltage of the ESD diode of the IO pin of the communication processor to be tested, and determining whether the communication processor to be tested is well contacted with the test machine.

Test conditions: the communication processor power pin is set to 0 and the IO pin applies-100 uA current.

Test vector: empty.

The test content is as follows: applying-100 uA current, and detecting the PN junction voltage of the ESD protection diode.

Test criteria: the expected value range is-1100 mV to-100 mV, the typical test value is-623.5 mV, and if the test value is within the expected value range, the test value is qualified.

2. Functional testing

Test purpose: and measuring whether the communication processor to be tested works correctly under the conditions of minimum, normal and maximum power supply voltages.

Test conditions: detecting whether a communication processor to be detected works normally or not in three power modes:

High voltage condition ovdd=3.4635V, avdd_p=2.625V, vdd=1.2V

Low voltage condition ovdd=3.135V, avdd_p=2.375v, vdd=1.05V

Normal voltage condition ovdd=3.3v, avdd_p=2.5v, vdd=1.1v

VDD represents an operating voltage within the communication processor, typically less than the input voltage.

AVDD represents an analog voltage that powers analog devices in the communication processor.

OVDD denotes a digital input/output power supply voltage.

Test vector: cpu_667.

The test content is as follows: the communication processor to be tested runs the test vector CPU_667 under different voltage conditions respectively, enters different states to be tested, collects output pin output responses at expected time, and compares the output pin output responses with expected results to judge whether the function of the communication processor to be tested is correct.

3.1, Direct current parameter test, including test item V _IH,V_IL.

Test purpose: the voltage value of the input pin V _IH,V_IL of the communication processor to be measured is measured.

Test conditions: the power supply supplies power normally, and the machine station provides a 33MHz main clock.

Test vector: functions

The test content is as follows: the communication processor to be tested respectively carries out test vectors Functio n under different voltage conditions, acquires output pin output responses at expected time, and compares the output pin output responses with expected results to judge whether the function of the communication processor to be tested is correct.

Test criteria: if V _IH is less than or equal to 2V, determining that the steel is qualified; vil is more than or equal to 0.8V, and is determined to be qualified.

3.2, The DC parameter test includes test item V _OH,V_OL.

Test purpose: and measuring the voltage value of an output pin V _OH,V_OL of the communication processor to be measured.

Test vector: functions

The test content is as follows: and after the communication processor is powered on, the GPIO generates a high-low level turning signal, the V _OH,V_OL card line is continuously changed by using SPECSE ARCH test functions, and the output level of the failure boundary point is detected.

Test criteria: determining qualification when V _OH is more than or equal to 233V; and when V _OL is less than or equal to 2V, determining that the steel is qualified.

4. The power consumption test comprises power dynamic power consumption and static power consumption tests, and comprises test items of 3.3V dynamic power supply current I _VDD33, 2.5V dynamic power supply current I _VDD25, 1.1V dynamic power supply current I _VDD11, IDDS 33-3V465,3.3V static power supply current I _{DDS33_3V3}, 2.5V static power supply current I _DDS25 and 1.1V static power supply current I _DDS11.

Test purpose: and measuring whether the dynamic and static power supply currents of the communication processor to be measured are qualified.

Test conditions: the normal power supply supplies power and applies corresponding test stimulus.

Test vector: the dynamic current uses the TEST vector gpio_test;

The test content is as follows: the communication processor to be tested runs the test vector first, and after entering the test state, the dynamic current and the static current of the power supply pins VDD, AVDD_P and OVDD are respectively measured.

Test criteria: the requirement of the qualification test value of the VDD dynamic current I _VDD33 is not more than 3A; the qualification test value of the VDD dynamic current I _VDD25 is required to be not more than 500mA; the requirement of the qualification test value of the VDD dynamic current I _VDD11 is not more than 8A; the qualification test value of the OVDD quiescent current I _{DDS33_3V465} is not more than 250mA; the qualification test value of the quiescent current I _{DDS33_3V3} of the OVD is required to be not more than 200mA; the qualification test value of the AVDD_P static current I _DDS25 is not more than 200mA; the VDD quiescent current I _DDS11 pass test value is required to be no greater than 250mA.

5. The I2C parameter test includes test items SCL clock frequency f _I2C, SCL clock low period T _I2CL, SCL clock high period T _I2CH, setup time T _I2SVKH for a complex START condition, START condition hold time T _I2SXKL, data setup time T _I2DVKH, data hold time T _I2SXKL, STOP condition setup time T _I2PVKH, bus free time T _I2KHDX between STOP condition and START condition.

Test purpose: and measuring the I2C port time parameter of the communication processor to be measured.

Test conditions: and the communication processor to be tested runs the test vector to enter a test state and performs time parameter measurement.

Test vector: I2C.

The test content is as follows: and (5) parameter scanning measurement. The communication processor to be tested firstly runs the test vector I2C, after the I2C port is configured, the device enters a test state, then the time parameter is converted into an input test excitation signal, and the measurement parameter is stepped from the maximum value to the minimum value or from the minimum value to the maximum value through the functional test.

Test criteria: SCL clock frequency f _I2C qualified test value is not less than 400KHz; the qualification test value of the low level period T _I2CL of the SCL clock is not less than 1.3us; the qualified test value of the high level period T _I2CH of the SCL clock is not less than 0.6us, and the qualified test value of the set-up time T _I2SVKH of the repeated START condition is not less than 0.6us; the START condition retention time T _I2SXKL is required to be not less than 0.6us; the data establishment time T _I2DVKH is not less than 100ns; the data retention time T _I2SXKL is not more than 0.9us; STOP condition setup time T _I2PVKH is required to be not less than 0.6us; the bus free time T _I2KHDX between STOP condition and START condition is required to be no less than 1.3us.

6. SPI parameter test, including test item: SPI data input setup time tsu (MI), SPI data input hold time th (MI), SPI data output valid time tv (MO), SPI data output hold time th (MO)

Test purpose: and measuring the SPI port time parameter of the communication processor to be measured.

Test vector: SPI.

The test content is as follows: and (5) parameter scanning measurement. The communication processor to be tested firstly runs the test vector SPI, after the SPI port is configured, the device enters a test state, then the time parameter is converted into an input test excitation signal, and the measurement parameter is stepped from the maximum value to the minimum value or from the minimum value to the maximum value through the functional test.

Test criteria: the SPI data input setup time tsu (MI) qualification test value is required to be not less than 6.5ns; the SPI data input holding time th (MI) qualification test value is not less than 2.5ns; the valid time tv (MO) qualification test value of SPI data output is not more than 2.5ns; the SPI data output holding time th (MO) qualification test value is required to be not less than 0ns.

7. JTAG parameter testing, including test item JTAG data setup time t _SU, JTAG data hold time t _HD.

Test purpose: and measuring the JTAG port time parameter of the communication processor to be measured.

Test vector: JTAG.

The test content is as follows: and (5) parameter scanning measurement. The communication processor to be tested firstly runs a test vector JTAG, after the JTAG port is configured, the device enters a test state, then, the time parameter is converted into an input test excitation signal, and the measurement parameter is stepped from a maximum value to a minimum value or from the minimum value to the maximum value through functional test.

Test criteria: JTAG data setup time t _SU qualified test value is not less than 4ns; JTAG data hold time t _HD is required to be no less than 10ns.

8. The RGMII port ac parameter test includes test items RGMII transmit clock period TX _CYC, RGMII data output delay TX _SKEW, RGMII data output delay RX _CYC, RGMII data input hold time RX _HOLD, RGMII data input setup time RX _SETUP.

Test purpose: and measuring the RGMII port time parameter of the communication processor to be measured.

Test vector: RGMII.

The test content is as follows: and (5) parameter scanning measurement. The communication processor to be tested firstly runs the test vector RGMII, after the RGMII port is configured, the device enters a test state, then the time parameter is converted into an input test excitation signal, and the measurement parameter is stepped from the maximum value to the minimum value or from the minimum value to the maximum value through the functional test.

Test criteria: the RGMII transmitting clock period TX _CYC qualified test value is required to be not less than 7.5ns and not more than 8.5ns; the RGMII data output delay TX _SKEW is required to be no less than 0ns and no more than 1ns; the RGMII receiving clock period RX _CYC qualified test value is required to be not less than 7.5ns and not more than 8.5ns; RGMII data input holding time RX _HOLD qualified test value is not less than 1ns; the RGM II data input setup time RX _SETUP is required to be no less than 1ns.

And when all the test items in the 8 test types are qualified, determining that the communication processor is qualified, otherwise prompting unqualified test items in the test result for a detector to analyze the fault reason.

It should be noted that, the method of the embodiment of the present application may be performed by a single device, for example, a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of an embodiment of the present application, the devices interacting with each other to accomplish the method.

It should be noted that the foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Based on the same inventive concept, the application also provides a testing device of the communication processor, which corresponds to the method of any embodiment.

Referring to fig. 8, the test device of the communication processor includes:

the timing determining module 10 is configured to: acquiring test content, and determining a test time sequence of the test item according to the test content;

the excitation determination module 20 is configured to: determining a test stimulus corresponding to each test item;

The response capture module 30 is configured to: applying test excitation to the communication processor according to the test time sequence, and capturing test response of the communication processor after the test excitation is applied;

the result determining module 40 is configured to: the qualification judgment of the test item is carried out according to the preset expected response and the test response, and obtaining a test result.

For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, the functions of each module may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.

The device of the foregoing embodiment is used to implement the testing method of the corresponding communication processor in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.

Based on the same inventive concept, the application also provides an electronic device corresponding to the method of any embodiment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the method for testing the communication processor of any embodiment when executing the program.

Fig. 9 shows a more specific hardware architecture of an electronic device according to this embodiment, where the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.

The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), a microprocessor, an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solutions provided in the embodiments of the present disclosure.

The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage, dynamic storage, etc. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.

The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.

Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).

Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).

It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.

The electronic device of the foregoing embodiment is configured to implement the testing method of the corresponding communication processor in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.

Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method for testing a communication processor according to any of the embodiments.

The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.

The storage medium of the foregoing embodiments stores computer instructions for causing the computer to execute the test method of the communication processor according to any one of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described herein.

It will be appreciated that before using the technical solutions of the various embodiments in the disclosure, the user may be informed of the type of personal information involved, the range of use, the use scenario, etc. in an appropriate manner, and obtain the authorization of the user.

For example, in response to receiving an active request from a user, a prompt is sent to the user to explicitly prompt the user that the operation it is requesting to perform will require personal information to be obtained and used with the user. Therefore, the user can select whether to provide personal information to the software or hardware such as the electronic equipment, the application program, the server or the storage medium for executing the operation of the technical scheme according to the prompt information.

As an alternative but non-limiting implementation, in response to receiving an active request from a user, the manner in which the prompt information is sent to the user may be, for example, a popup, in which the prompt information may be presented in a text manner. In addition, a selection control for the user to select to provide personal information to the electronic device in a 'consent' or 'disagreement' manner can be carried in the popup window.

It will be appreciated that the above-described notification and user authorization process is merely illustrative, and not limiting of the implementations of the present disclosure, and that other ways of satisfying relevant legal regulations may be applied to the implementations of the present disclosure.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the application as described above, which are not provided in detail for the sake of brevity.

Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.

While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, and the like, which are within the spirit and principles of the embodiments of the application, are intended to be included within the scope of the application.

Claims

1. A method for testing a communication processor, comprising:

Determining test stimulus corresponding to each test item;

2. The method of claim 1, wherein determining the test timing of the test item based on the test content comprises:

Determining a class time sequence of the test class according to the test content;

Determining the arrangement sequence of at least one test item in each test category according to the test content;

And determining the test time sequence of the test items according to the category time sequence and the arrangement sequence.

3. The method of claim 2, wherein said determining test stimulus corresponding to each of said test items comprises:

Determining a test vector set corresponding to the test category;

Determining test vectors corresponding to the test items in the vector set according to the arrangement sequence;

the test stimulus corresponding to the test item is determined by reading the test vector.

4. The method of claim 1, wherein the applying the test stimulus to the communication processor according to the test timing and capturing a test response of the communication processor after applying the test stimulus comprises:

determining a target test item according to the test time sequence, and determining a target test vector corresponding to the target test item;

Determining target test stimulus corresponding to the target test item according to the target test vector, and applying the target test stimulus to the communication processor;

A target test response of the communication processor for the target test stimulus is captured.

5. The method as recited in claim 4, further comprising:

responding to the failure to capture the target test response, and carrying out alarm prompt;

and responding to the target test response, and testing the next test item according to the test time sequence after the target test response is captured.

6. The method of claim 1, wherein the performing the eligibility judgment on the test item according to the preset expected response and the test response to obtain a test result includes:

determining target parameters for evaluating the test response;

Determining an expected value range of the target parameter according to the expected response;

Determining a test value of the target parameter according to the test response;

determining a qualification judgment result of the test item according to the expected value range and the test value;

And integrating the qualification judgment results of all the test items to obtain the test result.

7. The method of claim 1, wherein determining the eligibility determination of the test item based on the expected range of values and the test value comprises:

Determining that the qualification judgment result of the test item is qualified in response to the test value being in the expected value range;

And determining that the qualification judgment result of the test item is unqualified in response to the test value being out of the expected value range.

8. A test apparatus for a communication processor, comprising:

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 7 when the program is executed by the processor.

10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 7.