CN1180462C - Method for coating metal on the surface of integrated circuit structure - Google Patents
Method for coating metal on the surface of integrated circuit structure Download PDFInfo
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- CN1180462C CN1180462C CNB021087601A CN02108760A CN1180462C CN 1180462 C CN1180462 C CN 1180462C CN B021087601 A CNB021087601 A CN B021087601A CN 02108760 A CN02108760 A CN 02108760A CN 1180462 C CN1180462 C CN 1180462C
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- integrated circuit
- circuit structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a method for coating metal on the surface of an integrated circuit structure, which is carried out on an integrated circuit structure comprising a substrate and more than one chip arranged on the substrate, wherein the chip is coupled on the substrate in various modes, such as gold wire knotting or crystal coating, and sealing glue is at least coated on the chip and the substrate near the chip. A metal spraying layer coated on the surface of the part non-conducting region of the integrated circuit structure is formed in a metal spraying mode. A protecting film as protection is selectively added onto the surface before the metal layer is sprayed. The thickness of the metal spraying layer can be easily controlled and changed according to requirements. The metal spraying layer can reach the effects of good heat radiation and electromagnetic prevention, and can maintain the normal operation of the integrated circuit chip.
Description
Technical field
The present invention relates to a kind of method of integrated circuit structure surface metallization, particularly relate on an integrated circuit structure in the metal jet mode, part surface at this integrated circuit structure forms a surface metallization layer, and this metal layer thickness can be required according to practice, adjust the metal jet procedure parameter, reach required thickness and kenel.
Background technology
Along with electronics industry is constantly progressive, electronic system and Electronic Packaging are typically designed to and use minimum space as far as possible in practicalities.Therefore the space of bearer circuit is a valuable assets, should utilize as far as possible; For reaching this purpose, the downsizing circuit then be can yet be regarded as and is apt to use effective ways in space, and the circuit of downsizing also can increase the speed of service, the minimizing advantage that noise and other manifested.Yet heat dissipation problem also displays along with downsizing, and especially the increase of assembly causes the heat that produces, is also following along with increase transistorized number on single semiconductor subassembly to raise.
The form of one of semiconductor die package formation, comprising one or more chip is connected on the substrate, usually with its formation and be connected in a Printed Circuit Card (printed circuit card) or a printed circuit board (PCB) (printed circuit board), chip then can connect on the substrate in many ways.Generally the most common as beating gold thread mode (wire bonding), it is to electrically connect to superfine little gold thread of substrate tie point by the chip assembly place; Another kind then is to cover crystalline substance (flip chip) mode, and it is with entity contact and the electric connection of block tin (solder bump) as chip.For reaching the purpose of heat radiation, add the fin that a heat-conducting constitutes usually again, at last to keep the normal operation of chip.
See also Figure 1A to being the manufacturing process schematic diagram that known integrated circuit encapsulation of beating the gold thread mode constitutes.One integrated circuit structure 1, it is a packing forms, it consists predominantly of a substrate 11 and arrangement chip 13 thereon.These substrate 11 upper and lower sides are to be laid with the circuit layer (not shown), and can be the superimposed substrate form of single or multiple lift.And chip 13 is to utilize gold thread 14 to be coupled on the substrate 11 to beat the gold thread mode.Sealing 15 is to be overlying on chip 33 and near the substrate 11 thereof again, and main purpose is at integrated circuit structure 1 and chip 13.And this integrated circuit structure 1 is to be incorporated on the circuit board by a plurality of tin balls 12 at last.
Right fin 17 is usually earlier with a sheet metal, as heat radiation materials such as metallic coppers, with die-cut (punch), compacting (press) or module modes such as (molding) are made the fin 17 that meets for integrated circuit structure 1, its kenel must can be coincide fully with integrated circuit structure 1, shown in Figure 1B.And complete for fin 17 can be engaged with integrated circuit structure 1, be that an adhesion coating 16a, 16b are coated in the subregion on sealing 15 and substrate 11 earlier, at last again with integrated circuit structure 1 in fin 17 pressings, reach radiating effect.
Please consulting shown in Fig. 2 A to C, is the integrated circuit encapsulation formation process schematic diagram that covers crystal type again.As aforementioned, an integrated circuit structure 2, it mainly also includes a substrate 21 and arrangement chip 23 thereon, and different is that this chip 23 is to utilize block tin 24 (solder bump) to be coupled on the substrate 21 to cover crystal type, reaches the purpose that electrically conducts.And this integrated circuit structure 1 is to be incorporated on the circuit board by a plurality of tin balls 22 at last.
So fin 27 is same earlier with a sheet metal, as preferable materials of heat radiation such as metallic coppers, make with die-cut (punch), compacting (press) or module modes such as (molding) that to meet be the fin 27 of integrated circuit structure 2, its kenel must can be coincide fully with integrated circuit structure 2, shown in Fig. 2 B.And complete for fin 27 can be engaged with integrated circuit structure 2, be that an adhesion coating 26a, 26b are coated in the subregion on chip 23 and substrate 21 earlier, at last again with integrated circuit structure 2 in fin 27 pressings, reach radiating effect, shown in Fig. 2 C.
Yet above-mentioned all integrated circuit structures of commonly using still have following Lieque husband with surface metallization as fin:
(1) this fin needs earlier sheet metal made with die-cut (punch), compacting (press) or module numerous and diverse modes such as (molding) that to meet be the fin kenel of integrated circuit structure, and must can coincide fully with integrated circuit structure, the process complexity, and expend cost.
(2) manufacturing process needs a large amount of expensive boards, wastes unnecessary cost.
(3) the integrated circuit encapsulation that runs into complicated kenel constitutes, and its fin is made difficulty, and scope is seriously limited, and easily makes mistakes.
(4) the integrated circuit encapsulation constitutes and need carry out with complicated board in addition in the fin pressing, and needs adhesion coating auxiliary, also raises the cost.
(5) output is low, is difficult for volume production.
Therefore, the manufacturing process of the fin of integrated circuit structure still has the great space of improving.Industry is also prayed and can be issued to optimal operation usefulness in the trend of microminiaturization.
Summary of the invention
Main purpose of the present invention is to provide a kind of method of integrated circuit structure surface metallization, it forms a surface metallization layer in metal jet mode (metal spray) at the part surface of this integrated circuit structure on an integrated circuit structure, and this metal thickness can be required according to practice, adjust metal jet manufacturing process parameter, reach required thickness.
Secondary objective of the present invention is to provide a kind of manufacturing process of washing framework of integrated circuit structure, this washing framework can reach the effect of heat radiation and electromagnetic shielding, and the washing framework that forms can be made into arbitrary form and size, does not need complicated board, easily volume production.
The method that is to provide a kind of applied metal spray regime formation integrated circuit structure of another syllabus of the present invention, it directly is covered with a metal level at the crystal back side that comprises plurality of chips in the metal jet mode, make when encapsulating manufacturing process, the metal level that each chip back in the formed integrated circuit structure is covering is promptly as the usefulness of ready-made fin.
For reaching above-mentioned purpose, the present invention provides a kind of method of integrated circuit structure surface metallization, commonly uses the surface metal of making integrated circuit structure in modes such as die-cut, compacting or modules by casting out, and forms the washing layer and change in the metal jet mode.It is earlier to include a substrate and settle the integrated circuit encapsulation of chip thereon to constitute more than one one, and chip is to be coupled in and to finish encapsulation on the substrate to beat the gold thread mode or to cover crystal type.Include at the described method step of part that this encapsulation constitutes in the metal jet mode:
(a) provide an integrated circuit structure, this integrated circuit structure includes a substrate and at least one arrangement chip thereon;
(b) form a surface metallization layer in the metal jet mode at the part surface of this integrated circuit structure, this part surface comprises the part surface of this substrate.
That is to say that the present invention provides a kind of method of integrated circuit structure surface metallization, commonly use the surface metal of making integrated circuit structure in modes such as die-cut, compacting or modules, form the washing layer and change in the metal jet mode by casting out.It is earlier to include a substrate and settle the integrated circuit encapsulation of chip thereon to constitute more than one one, and chip is to be coupled in and to finish encapsulation on the substrate to beat the gold thread mode or to cover crystal type.On the surface, the non-conductive district of part that this encapsulation constitutes, spray the metal jet layer that formation one is coated in the surface in the metal jet mode, this metal jet layer is constituted by simple metal or alloy.Wherein, this metal jet mode can be the electric arc meltallizing, and the thickness of this metal jet layer can be complied with the required control break of doing easily, can reach the effect of better heat radiating effect and anti electromagnetic wave, keeps the normal operation of integrated circuit (IC) chip.
The present invention also provides a kind of applied metal spray regime to form the method for integrated circuit structure, and described method step comprises:
(a) provide a crystal, this crystal comprises some chips of having finished the semiconductor fabrication process;
(b) be covered with a metal level with metal arc meltallizing spray regime at the back side of this crystal, and the melt temperature of electric arc meltallizing head end point is between 4000 ℃-6000 ℃;
(c) cut this crystal, make its plurality of chips be divided into the individual chip of unit, this unit chip is respectively encapsulated, make more than one this chip placing on a substrate, become an integrated circuit structure.
But the present invention also the applied metal spray regime in the manufacturing process that forms integrated circuit structure, comprise some crystal back sides of having finished semiconductor fabrication process chip one, be covered with a metal level in the metal jet mode at the back side of this crystal, cutting apart this crystal again makes after the individual chip of its plurality of chips unit of being split up into, this unit chip is respectively encapsulated manufacturing process, make chip placing that the back side covering a metal level on substrate, become an integrated circuit structure.Because respectively this chip back has promptly covered a metal level, so the metal level that each chip back in the formed integrated circuit structure is covering makes chip keep normal effect when running promptly as the usefulness of ready-made fin.
Description of drawings
Figure 1A to C is the known manufacturing process schematic diagram of breaking gold thread packaged integrated circuits body structure surface metallizing;
Fig. 2 A to C is the manufacturing process schematic diagram of the integrated circuit structure surface metallization of known chip package;
Fig. 3 A to B is the first preferred embodiment manufacturing process schematic diagram of the method for integrated circuit structure surface metallization of the present invention;
Fig. 4 A to C is the second preferred embodiment manufacturing process schematic diagram of the method for integrated circuit structure surface metallization of the present invention;
Fig. 5 A to G is the 3rd preferred embodiment manufacturing process schematic diagram of the manufacturing process of the washing framework of integrated circuit structure of the present invention;
Fig. 6 A to D forms the 4th preferred embodiment manufacturing process schematic diagram of integrated circuit structure for applied metal spray regime of the present invention.
Embodiment
One of major technique feature of the present invention is to change in the metal jet mode to form the washing layer, is suitable for the integrated circuit structure of various sizes.
Seeing also Fig. 3 A to B is the first embodiment of the present invention.One integrated circuit structure 3 at first is provided, this integrated circuit structure 3 is the encapsulation aspect of general industry, it consists predominantly of a substrate 31 and arrangement chip 33 thereon, and industry is installed one more than the chip according to required usually, only represents with a chip 33 among the right figure.Described substrate 31 can be a ceramic substrate or plastic base, ceramic substrate be with ceramic material as insulating barrier, and this plastic base is as insulating barrier with plastic basis material.And its material be two butadiene dilute acid acid imides (bismaleimide, BMI), two butadiene dilute acid acid imide/triazine resins.Bismaleimide triazine-based, BT), epoxy resin (epoxy) FR-4 or polyamide materials such as (polyimide).These substrate 31 upper and lower sides are laid with the circuit layer (not shown), and this substrate 31 can be the superimposed substrate form of single or multiple lift.And chip 33 is to utilize gold thread 34 to be coupled on the substrate 31 to beat gold thread mode (wlre-bonding).Sealing 35 is to be overlying at least on chip 33 and near the substrate 31 thereof again, and main purpose is at protection bga component and chip 33.Yet be provided with ground mat (ground pad) 39 on substrate 31 in addition, this ground mat 39 is that design is positioned at sealing 35 and does not cover part.And this integrated circuit structure 3 is to be incorporated on the circuit board by a plurality of tin balls 32 at last.
Connecing down described is one of emphasis of the present invention, give up and knownly make heat-delivery surface metallizing layer in modes such as die-cut, compacting or modules, and change in metal jet mode (metal spray) on surface, the non-conductive district of the part of this formation 3, direct injection forms a surface metal jetted layers 36, and this metal jet layer 36 is constituted by simple metal such as copper (Cu), aluminium (Al), zinc (Zn), other metal or its alloy.And the ground mat 39 on the substrate 31 is also covered by this metal jet layer 36, thereby has caused the increasing contact area, improves the electrical effect of integrated circuit structure 3, shown in Fig. 3 B.
Wherein, this metal jet mode is meant electric arc meltallizing (Arc melting spray), at the electric arc meltallizing that present embodiment imposed is PEC PC-300 electric arc meltallizing, and the metallic roughness size that is ejected is between 1 μ m-10 μ m, and is preferable between 4 μ m-6 μ m; This metallic adhesive force is at 100kg/cm
2-300kg/cm
2Between; 160kg/ μ m
2-281kg/cm
2Between, as aluminium: 160kg/cm
2, zinc: 281kg/cm
2The wire rod feeding style is for pushing away/pull-type (push/pull), and wire rod uses between the diameter 1.0mm to 3.0mm, is preferably between the 1.6mm to 2.4mm; And the melt temperature of this electric arc meltallizing head end point is between 4000 ℃-6000 ℃, the clipped wire of ejection cools off in moment and is covering on applicator, and under the environment of room temperature, can operate, and the thickness of this metal jet layer 36 can be complied with the required control break of doing easily, can reach better heat radiating effect and anti electromagnetic wave (electromagnetic interference, EMI) effect is kept the normal operation of integrated circuit (IC) chip 33.
But, before imposing metal jet, can carry out a step (not shown) that is covered with diaphragm (protective film) earlier on surface, the non-conductive district of the part of this formation 3, as resin (resin) etc., carry out metal jet again.
Certainly, the present invention also can be applied to cover the encapsulation of crystal type (flip-chip) integrated circuit and constitute, and shown in Fig. 4 A to C, is the second embodiment of the present invention.With last embodiment, an integrated circuit structure 4 is provided earlier, it mainly also includes a substrate 41 and arrangement chip 43 thereon, also only represents with a chip 43 in the icon.Described substrate 41 can be a ceramic substrate or plastic base, and its material and design are also described with last embodiment, do not repeat them here.Different is, this chip 43 is to utilize block tin (bump) 44 to be coupled on the substrate 41 to cover crystal type (flip-chip), imposes a sealing (indicating) protection again.And as a same embodiment, on substrate 41, be provided with ground mat (ground pad) 49 in addition, the usefulness of power supply property ground connection.
Connect down and carry out a step (not shown) that is covered with diaphragm (protectivefilm) 45 on surface, the non-conductive district of the part of this formation 4, make protective layer as resin (resin) etc.Be noted that this protective layer 45 is positions of avoiding ground mat 49, does not cover it.
As the foregoing description; directly constitute 4 the non-conductive district of part surperficial (diaphragm 45) at this in the metal jet mode; spray and form a surface metal jetted layers 46; this metal jet layer 46 is constituted by simple metal such as copper (Cu), aluminium (Al), zinc (Zn), other metal or its alloy; and the ground mat 49 on the substrate 41 is also covered by this metal jet layer 46; thereby caused the increasing contact area, improve the electrical effect of integrated circuit structure 4, shown in Fig. 4 C.
Wherein, this metal jet mode is meant the electric arc meltallizing, also is PEC PC-300 electric arc meltallizing at the electric arc meltallizing that present embodiment imposed, and the clipped wire that is ejected is between 1 μ m-10 μ m in size, and is preferable between 4pm-6pm; This metallic adhesive force is at 100kg/cm
2-300kg/cm
2Between, preferable 160kg/cm
2-281kg/cm
2Between; As aluminium: 160kg/cm
2, zinc: 281kg/cm
2The wire rod feeding style for push away/pull-type, wire rod uses between the diameter 1.0mm to 3.0mm, is preferably between the 1.6mm to 2.4mm; Carry out under the room temperature, and the melt temperature of this electric arc meltallizing head end point is between 4000 ℃-6000 ℃ that the metallic moment cooling of ejection is being covered on applicator, and can operate under the environment of room temperature.And the thickness of this metal jet layer 46 can be complied with the required control break of doing easily, can reach the effect of better heat radiating effect and anti electromagnetic wave (EMI), keeps the normal operation of integrated circuit (IC) chip 43.
Certainly, integrated circuit structure 3 is except that the present invention makes metal jet layer 46, also can device have other extra as electronic building brick such as capacitance resistance or other integrated circuit package (not shown) etc. and since this be belong to prior art partly and non-for feature of the present invention so following repeating no more.
Yet except the method for integrated circuit structure surface metallization, the present invention also can make the fin and the electromagnetic shielding (EMI shielding) of various difformity thickness separately, and is applied to multiple integrated circuit structure.Seeing also Fig. 5 A to 5G, is third embodiment of the invention, plants the manufacturing process of the washing framework of integrated circuit structure, and its step includes:
(a) provide one to apply framework 51, this coating framework 51 is to have an accommodation space, and the framework that can finish with general technology;
(b) be covered with a release film (release film) 52 on the accommodation space surface of this coating framework 51 with spray regime, this release film is epoxy resin materials such as (epoxy resin);
(c) then forming a metal level 53 on the surface of this release film 52 with spray regime fills up this accommodation space;
(d) remove this washing framework 51, make this metal level 53 form a washing die body 53a, this washing die body 53a is promptly as the main film body of making the washing framework.
(e) be covered with a mould release (release agent) 54 and one release film 55 in regular turn on the surface of this washing die body 53a with spray regime equally, as materials such as epoxy resin;
(f) form a washing layer 56 on the surface of this release film 55 with spray regime, by simple metal such as copper (Cu), aluminium (Al), zinc (Zn) or its alloy are constituted;
(g) remove this washing die body 53a, make this washing layer 56 form washing framework (frame) 56a.
Wherein, above-mentioned metal jet mode is meant electric arc meltallizing (Arc melting spray) or other high speed metal jet technology, and the metal particle size that is ejected is that metallic adhesive force is at 100kg/cm between 1 μ m-10 μ m
2-300kg/cm
2Between, the melt temperature of this electric arc meltallizing head end point is between 4000 ℃-6000 ℃, the clipped wire of ejection cools off in moment and is covering on applicator, and can operate under the environment of room temperature.
Yet, the washing framework 56a of present embodiment made can be applicable to various integrated circuit structures, make the heat radiation of various difformity thickness and the washing framework 56a of electromagnetic shielding (EMI shielding) separately, as long as make washing die body 53a earlier according to step (a) to (d), be main film body with washing die body 53a again, repeating step (e) to (g) can be produced the washing framework 56a of a plurality of quantity.Constitute to be incorporated into each integrated circuit encapsulation as modes such as stickups again,
As be applied in plastics pin array (plastic pin grid array, PPGA).Baton round array (plastic ball grid array, PBGA) or plastic cylinder array (plastic columngrid array, PCGA) packaged type, or be applied on the module substrate of specific demand, can reach the effect of heat radiation and electromagnetic shielding.
In addition, technical spirit of the present invention also can the 4th embodiment be set forth, and the applied metal spray regime that sees also Fig. 6 A to D and be fourth embodiment of the invention forms the method for integrated circuit structure, and its step comprises:
(a) provide a crystal 60, this crystal 60 is to comprise some integrated circuit (IC) chip (chip) 61 of having finished the semiconductor fabrication process, respectively this chip is a general integrated circuit (IC) chip that can independently operate, because the manufacturing process of each integrated circuit (IC) chip 61 is known by industry, the technology emphasis of yet non-the present invention's original creation does not repeat them here.
(b) the metal jet mode (metal spray) with previous embodiment is covered with a metal level 62 at the back side of this crystal 60.
(c) generally to cut apart this crystal 60 as modes such as machine cuts, make the individual integrated circuit (IC) chip 61a of its plurality of integrated circuit chips 61 units of being split up into, then the integrated circuit (IC) chip 61a of this unit is respectively encapsulated manufacturing process, make the described back side cover the integrated circuit (IC) chip 61a of a metal level 62, be placed on the substrate 63, become an integrated circuit structure.Integrated circuit (IC) chip 61a utilizes gold thread 64 to be coupled on the substrate 63 to beat gold thread mode (wire-bonding).Sealing 65 is to be overlying at least on chip integrated circuit (IC) chip 61a and near the substrate 63 thereof again.
(d) certain, present embodiment also can be applied to cover the encapsulation of crystal type (flip-chip) integrated circuit and constitute, and shown in Fig. 6 D, this integrated circuit (IC) chip 61a that is covering a metal level 62 utilizes block tin (bump) 66 to be coupled on the substrate 63 to cover crystal type.
Equally, present embodiment can be complied with required and be installed one more than the chip, only represents with an integrated circuit (IC) chip 61a in the right icon.The material of described substrate 63, the design all same as the previously described embodiments, repeat no more; And directly be covered with a metal level 62 comprising some crystal 60 back sides of having finished the chip (chip) 61 of semiconductor fabrication process in metal jet mode (metal spray), and when the individuality integrated circuit (IC) chip 61a of the cutting unit of being split up into, respectively this chip back has promptly covered a metal level 62.Then when respectively the integrated circuit (IC) chip 61a of this unit encapsulated manufacturing process, the metal level 62 that each the integrated circuit (IC) chip 61a back side in the formed integrated circuit structure is being covered made chip 61a keep normal effect when running promptly as the usefulness of ready-made fin.
This metal level 62 is constituted by simple metal such as copper (Cu), aluminium (Al), zinc (Zn), other metal or its alloy; Wherein, this metal jet mode is meant the electric arc meltallizing, is PEC PC-300 electric arc meltallizing, and the clipped wire that is ejected is between 1 μ m-10 μ m in the roughness size, and is preferable between 4 μ m-6 μ m; This clipped wire is at 100kg/cm in adhesive force
2-300kg/cm
2Between; Preferable 160kg/cm
2-281kg/cm
2Between, as aluminium: 160kg/cm
2, zinc: 281kg/cm
2The wire rod feeding style is for pushing away/pull-type (push/pull), and wire rod uses between the diameter 1.0mm to 3.0mm, is preferably between the 1.6mm to 2.4mm; And the melt temperature of this electric arc meltallizing head end point is between 4000 ℃-6000 ℃, and the metallic moment cooling of ejection is being covered on applicator, and can operate under the environment of room temperature.And the thickness of this metal level 62 can be complied with the required control break of doing easily, can reach better heat radiating effect.
In sum, the method for integrated circuit structure surface metallization of the present invention has following advantage at least with respect to located by prior art:
(1) the present invention utilizes metal jet to form the method for metal on the integrated circuit structure surface, can be applicable to various integrated circuit encapsulation multi-form and size and constitutes, and is in extensive range not limited.
(2) metal that forms on the integrated circuit structure surface can reach the effect of heat radiation and electromagnetic shielding.
(3) metal thickness that forms on the integrated circuit structure surface can be required according to practice, adjusts metal jet manufacturing process parameter, reaches required thickness.
(4) the present invention also can use as ceramic substrate or plastic base etc. and locate, even crystal or glass substrate all can.
(5) output height, manufacturing process is simplified, and does not need complicated board, easily volume production.
(6) the washing framework of Xing Chenging can be made into arbitrary form and size.
(7) can carry out under the manufacturing process room temperature.
(8) directly utilize the metal level of metal jet in the thermolysis of chip back formation tool, the uniformity is good, and thermal diffusivity is good, and manufacturing process is more simple and easy.
The above is to utilize preferred embodiment to describe the present invention in detail, but not limits the scope of the invention.Those of ordinary skills suitably do change and adjustment slightly, will not lose main idea of the present invention place, also do not break away from the spirit and scope of the present invention.
Claims (12)
1. the method for an integrated circuit structure surface metallization is characterized in that, described method step includes:
(a) provide an integrated circuit structure, this integrated circuit structure includes a substrate and at least one arrangement chip thereon;
(b) form a surface metallization layer in the metal jet mode at the part surface of this integrated circuit structure, this part surface comprises the part surface of this substrate.
2. the method for integrated circuit structure surface metallization as claimed in claim 1 is characterized in that also can comprising a step (b ') before in described step (b): be covered with a diaphragm with spray regime at the part surface of this integrated circuit structure.
3. the method for integrated circuit structure surface metallization as claimed in claim 1 is characterized in that described surface metallization floor is formed on the surface, non-conductive district of this integrated circuit structure.
4. the method for integrated circuit structure surface metallization as claimed in claim 1 is characterized in that described metal jet mode can refer to the electric arc meltallizing.
5. the method for integrated circuit structure surface metallization as claimed in claim 1, it is characterized in that on this substrate, being provided with in addition ground mat, and this surface metallization layer is directly to form to cover on this ground mat, for the bigger contact area of this integrated circuit structure.
6. the method for integrated circuit structure surface metallization as claimed in claim 1, the part surface that it is characterized in that described this integrated circuit structure also comprises the back side of this chip.
7. the method for integrated circuit structure surface metallization as claimed in claim 1 is characterized in that this integrated circuit structure comprises that also a sealing is overlying on chip and near the substrate thereof.
8. the method for integrated circuit structure surface metallization as claimed in claim 7, the part surface that it is characterized in that described this integrated circuit structure also comprises the surface of this sealing.
9. an applied metal spray regime forms the method for integrated circuit structure, it is characterized in that described method step comprises:
(a) provide a crystal, this crystal comprises some chips of having finished the semiconductor fabrication process;
(b) be covered with a metal level with metal arc meltallizing spray regime at the back side of this crystal, and the melt temperature of electric arc meltallizing head end point is between 4000 ℃-6000 ℃;
(c) cut this crystal, make its plurality of chips be divided into the individual chip of unit, this unit chip is respectively encapsulated, make more than one this chip placing on a substrate, become an integrated circuit structure.
10. applied metal spray regime as claimed in claim 9 forms the method for integrated circuit structure, it is characterized in that metallic roughness size that described electric arc meltallizing ejected is between 1 μ m-10 μ m.
11. applied metal spray regime as claimed in claim 9 forms the method for integrated circuit structure, it is characterized in that metallic adhesive force that described electric arc meltallizing ejected is at 100kg/cm
2-300kg/cm
2Between.
12. applied metal spray regime as claimed in claim 9 forms the method for integrated circuit structure, it is characterized in that the described mode that this unit chip is respectively encapsulated is for beating gold thread or the chip package mode is wherein a kind of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021087601A CN1180462C (en) | 2002-04-02 | 2002-04-02 | Method for coating metal on the surface of integrated circuit structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021087601A CN1180462C (en) | 2002-04-02 | 2002-04-02 | Method for coating metal on the surface of integrated circuit structure |
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| Publication Number | Publication Date |
|---|---|
| CN1449004A CN1449004A (en) | 2003-10-15 |
| CN1180462C true CN1180462C (en) | 2004-12-15 |
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|---|---|---|---|
| CNB021087601A Expired - Lifetime CN1180462C (en) | 2002-04-02 | 2002-04-02 | Method for coating metal on the surface of integrated circuit structure |
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| JP5799541B2 (en) | 2011-03-25 | 2015-10-28 | 株式会社ソシオネクスト | Semiconductor device and manufacturing method thereof |
| CN102364666A (en) * | 2011-09-30 | 2012-02-29 | 常熟市广大电器有限公司 | Anti-electromagnetic interference chip encapsulating method |
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