CN118042699A

CN118042699A - Component carrier and method for checking the quality of its electrically conductive interconnections

Info

Publication number: CN118042699A
Application number: CN202211362481.1A
Authority: CN
Inventors: 卢林峰; 端木佳杰; 罗亚格
Original assignee: AT&S Austria Technologie und Systemtechnik AG
Current assignee: AT&S Austria Technologie und Systemtechnik AG
Priority date: 2022-11-02
Filing date: 2022-11-02
Publication date: 2024-05-14

Abstract

A component carrier and a method of inspecting the quality of its electrically conductive interconnections are described, the component carrier comprising a stack, a plurality of components, a plurality of electrically conductive interconnections and a test area, the test area comprising a test component and a second electrically conductive interconnection, the test component having an area to which the second electrically conductive interconnection is connected, the area having the same mechanical/chemical characteristics as a corresponding one of the plurality of components and/or the area having the same location in depth as a corresponding one of the plurality of components, the second electrically conductive interconnection having the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnections and/or the second electrically conductive interconnection having the same location in depth as at least one of the plurality of electrically conductive interconnections, the connection area being exposed on the same side of the component carrier, the area being electrically connected to two end portions of the second electrically conductive interconnection, respectively.

Description

Component carrier and method for checking the quality of its electrically conductive interconnections

Technical Field

The invention relates to a component carrier with electrically conductive interconnects. The invention further relates to a method for checking the quality of an electrically conductive interconnection of a component carrier.

Thus, the present invention may relate to the technical field of component carriers such as printed circuit boards and IC substrates, in particular in the context of testing the reliability of electrically conductive interconnects.

Background

With increasing product functions of component carriers equipped with one or more electronic components, increasing miniaturization of such electronic components, and increasing number of electronic components mounted on component carriers such as printed circuit boards, increasingly powerful array components or packages having a plurality of electronic components are employed, which have a plurality of contacts or connections, with smaller and smaller pitches between the contacts. During operation, removal of heat generated by these electronic components and the component carriers themselves becomes an increasingly greater problem. At the same time, the component carrier should be mechanically strong and electrically and magnetically reliable in order to be operable even under severe conditions.

In particular, it remains a challenge to measure the reliability of electrically conductive interconnects, such as vias (vertical interconnect channels) in component carriers (preforms), to ensure product quality and performance.

Conventionally, the electrically conductive connection can be electrically contacted by a corresponding measuring device, for example by means of a wire. An accepted method may be the so-called Four Wire Test (FWT), which can be used to accurately measure the resistance of an interconnect in a non-destructive manner. The measuring device thus comprises four lines, of which two are dedicated to measuring current and the other two are dedicated to measuring voltage. From the result, the resistance of the electrical connection under test can be obtained. The measured resistance can be used as an electrical parameter to evaluate the quality of the electrically conductive connection.

Conventionally, the FWT method is performed using a so-called daisy chain sample (DAISY CHAIN coupons). Even though the daisy chain test sample may detect an overall defect of an electrically conductive interconnect (e.g., a fully broken via with no remaining bond), this approach may not reliably detect a weaker interconnect, such as a partially broken via (with reduced remaining bond). This may be because the increase in resistance of such weaker interconnects may be very small compared to the increase in resistance of interconnects with integral defects. Furthermore, the daisy-chain approach may only provide results related to all interconnects. Thus, the result of the daisy chain measurement will be: all of the interconnects have sufficient quality or one of the interconnects has a defect.

Furthermore, with daisy chain samples, detectable defects are associated with electrically conductive interconnects (i.e., vias and/or electrical connection structures), and any kind or interaction with additional structures cannot be evaluated; for example, if an electrically conductive interconnect simulates an electrically conductive interconnect that contacts/merges with a component, the defects result from different materials, chemical properties, surface interactions, and different mechanical and/or thermal properties between the electrically conductive interconnect and the component.

Thus, it may also be desirable to reliably measure a single electrically conductive interconnect in an accurate manner only for weaker defects.

Disclosure of Invention

It may be desirable to test electrically conductive interconnects located in a component carrier (preform) in an efficient, accurate, and reliable manner.

A component carrier and a method are provided.

According to a first aspect of the invention, a component carrier (preform) is described, the component carrier (preform) comprising:

a stack comprising at least two electrically conductive layer structures and at least one electrically insulating layer structure;

A plurality of components disposed in or on the stack;

a plurality of electrically conductive interconnects in the stack, the electrically conductive interconnects electrically connecting the at least one electrically conductive layer structure and the respective component; and

A test area disposed in a portion of the component carrier,

The test area includes at least one test component and at least one second electrically conductive interconnect, the test component having the following areas: the second electrically conductive interconnect is connected at the region and has the same mechanical/chemical characteristics as a corresponding one of the plurality of components and/or the region has the same location in depth as a corresponding one of the plurality of components, the second electrically conductive interconnect has the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnects and/or the second electrically conductive interconnect has the same location in depth as at least one of the plurality of electrically conductive interconnects,

Wherein on the same side of the component carrier connection areas are exposed, which areas are electrically connected to both end portions of at least one of said second electrically conductive interconnects, respectively.

According to a second aspect of the invention, a method for checking the quality of an electrically conductive interconnect of a component carrier is described, the component carrier comprising:

-a plurality of components arranged in or on the stack, and

-A plurality of electrically conductive interconnects electrically connecting at least one electrically conductive layer structure with a respective component, and

-At least one test area provided in a portion of the component carrier, the test area comprising at least one test component and at least one second electrically conductive interconnect, the test component having the following areas: at which the second electrically conductive interconnect is connected, which region has the same mechanical/chemical characteristics as a corresponding one of the plurality of components and/or which region has the same position in depth as a corresponding one of the plurality of components, which second electrically conductive interconnect has the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnects and/or which second electrically conductive interconnect has the same position in depth as at least one of the plurality of electrically conductive interconnects,

Wherein,

Both end portions of at least one of said second electrically conductive interconnects are connected to respective connection areas exposed on the same side of the component carrier,

The method comprises the following steps: and evaluating the quality of the further electrical interconnect based on at least one electrical power value obtained from the two exposed areas.

The term "electrically conductive interconnect" may herein denote an electrically conductive structure adapted to connect at least two electrically conductive (layer) structures (located in a component carrier layer stack), wherein one of the electrically conductive (layer) structures is provided on a component. In a preferred example, the electrically conductive interconnect may be a vertical electrically conductive interconnect, such as a blind hole in a component carrier layer stack. These electrically conductive interconnects may be provided on the following active areas of the component carrier: in the region of action, the electrically conductive structure and one or more components may be connected or connectable to each other by the electrically conductive interconnect.

A plurality of electrically conductive interconnects may be arranged in the stack.

The term "second electrically conductive interconnect" may refer herein to an electrically conductive interconnect disposed on a different region of the component carrier, the second electrically conductive interconnect comprising characteristics comparable to the electrically conductive interconnect. In an example, the second electrically conductive interconnect may be arranged at a comparable/similar vertical (in Z-direction) position in the stack. In further examples, the second electrically conductive interconnect includes mechanical/electrical/chemical properties comparable/similar to the electrically conductive interconnect and/or comparable/similar geometry. In a preferred embodiment, all mentioned parameters may be comparable/similar.

The second electrically conductive interconnect may be adapted for electrical testing for electrical parameters (e.g. voltage, current, resistance), in particular by one or more lines of the measuring device.

The term "test component" may herein denote a component, e.g. a virtual component, arranged on a different area of the component carrier, preferably in the test area, the component comprising properties comparable to at least one of the components, in particular the component comprising properties comparable to at least one of the components arranged in the region of action. In an example, the components may be arranged in a stack in a comparable/similar vertical (in the Z-direction) position. In further examples, the test component may have a spatial dimension comparable/similar to the component in the region of action. In further examples, the test component includes a region to which the second electrically conductive interconnect is connected, the region having the same mechanical/chemical characteristics as a corresponding one of the plurality of components, and/or the region having the same location in depth as a corresponding one of the plurality of components. In a preferred embodiment, all mentioned parameters may be comparable/similar.

In particular, the region to which the second electrically conductive interconnect is connected has the same roughness and/or surface tension as one of the plurality of components.

The term "test area" may herein denote an area of the stack (or component carrier, depending on the design) where the measurement device may be in electrical contact with the component carrier for conducting the electrically conductive interconnect test, in particular for conducting the electrically conductive interconnect test according to known requirements of reflow, hot oil, thermal cycling/stability, insulation resistance/bHAST test, e.g. a four wire measurement device, or any other device which measures the (electrical) value (e.g. resistance) under certain environmental conditions of the at least one second electrically conductive interconnect (e.g. at certain temperatures with certain electrical values in case of certain repetition of the test).

In order to provide a reliable test of the second electrically conductive interconnect without affecting the functionality or mechanical integrity of the electrically conductive interconnect and/or the electrically conductive structure and/or the plurality of components, at least one second electrically conductive interconnect may be provided on the test area (e.g. inside or outside the active area) in connection with a test component provided on the same test area, thereby allowing the second electrically conductive interconnect and its interaction with a test component in the test area to be tested, i.e. the second electrically conductive interconnect and its interaction with a test component in the test area without involving an interconnect and a component in the active area, and then preferably by this test evaluating the quality of the electrically conductive interconnect, the second electrically conductive interconnect having the same mechanical/chemical characteristics as at least one of the electrically conductive interconnects and/or the second electrically conductive interconnect having the same position in terms of stack depth as at least one of the electrically conductive interconnects and the corresponding to a plurality of components provided in the test area.

The term "connection region" may refer herein to an electrically conductive region (e.g., pad, terminal, etc.) that is electrically connected to a second electrically conductive interconnect to be tested. Thus, via the connection region, the second electrically conductive interconnect may be electrically contacted even though the second electrically conductive interconnect may be (fully) embedded in the stack. According to an alternative or additional embodiment, the connection region may be formed by a (discontinuous) electrically conductive layer structure arranged at the upper end portion of the respective electrically conductive interconnect. In further examples (particularly when electrically conductive interconnects (devices) are embedded in the stack), the connection region may be electrically connected to the second electrically conductive interconnect (device) by an additional interconnect, such as a via. In a specific example, the connection region has a square shape, with the aim of using as much of the available component carrier surface as possible, for example; more specifically, the square test area of the connection area may be 1×1mm (or less). Other shapes, such as circular, rectangular or irregular shapes, are not excluded from the present invention. According to alternative or additional embodiments of the invention, the shape of the connection region may be a different shape and/or a different size and/or a different material/color/roughness, i.e. the connection region provided for testing reasons is clearly distinguished from other regions provided on the same side of the component carrier and provided for other functions.

In an embodiment, the stack/component carrier surface may comprise a plurality of exposed connection areas, preferably arranged in an array. Thus, a large number of second electrically conductive interconnects (devices) may be tested (individually) from the same component carrier side, even though at least some of them may be embedded in the stack.

In the present context, the term "identical side of the component carrier" may particularly denote the same side in the thickness direction, for which purpose one of the two opposite main surfaces of the component carrier may be at least partially contacted vertically.

In a preferred embodiment, the component carrier comprises a main body, i.e. only a main stack; in this preferred embodiment, "identical sides" refers to identical major surfaces of the body/stack.

In an alternative embodiment, the component carrier comprises at least two bodies, namely a (stacked) PCB and a (stacked) substrate assembled on said PCB; in this embodiment, the term "identical side of the component carrier" may refer to an identical side that is able to at least partially access both major surfaces of both bodies; for this purpose, the connection regions may be provided on one body, or on the other body, or on both bodies (in which case the second electrically conductive interconnect may be provided between the first body and the second body).

In the context of this document, the term "component carrier" may particularly denote any support structure capable of accommodating one or more components on and/or in the component carrier to provide mechanical support and/or electrical connection. In other words, the component carrier may be configured as a mechanical and/or electrical carrier for the component. In particular, the component carrier may be one of the following: printed circuit boards, organic intermediaries, and IC (integrated circuit) substrates. The component carrier may also be a hybrid board incorporating the different types of component carriers described above.

The term "component carrier preform" may particularly denote a component carrier in production, i.e. a semifinished product. One example may be a panel comprising a plurality of component carriers in manufacture, whereby the component carriers will be separated (singulated) after the manufacturing process. In addition to the component carriers under manufacture, the component carrier preform (panel) may also include separation areas between the component carriers under manufacture, which separation areas will no longer form part of the final component carrier product.

In the present context, the term "component carrier" may include separate component carriers, separate component carrier preforms, and component carrier preforms comprising two or more component carriers in manufacture.

Although in one example the connection regions may be arranged on the component carrier under manufacture, in another example the connection regions may be arranged at separate regions of the component carrier preform (panel). In this further example, the connection region may thus not form part of the final component carrier product.

In an embodiment, the component carrier comprises a (layer) stack of at least one electrically insulating layer structure and at least one electrically conducting layer structure. For example, the component carrier may be a laminate of the above-described electrically insulating layer structure and electrically conducting layer structure, which laminate is formed in particular by the application of mechanical pressure and/or thermal energy. The stack may provide a plate-like component carrier that is capable of providing a large mounting surface for further components and yet is very thin and compact. The term "layer structure" may particularly denote a continuous layer, a patterned layer, or a plurality of discontinuous islands in a common plane.

According to an exemplary embodiment, the invention may be based on the idea that: by testing the second electrically conductive interconnects connected to the surface of the test component provided in the dedicated test area, the quality of the electrically conductive interconnects in the component carrier (preform) and their interaction (i.e. connection) with the component can be evaluated in an efficient, accurate and reliable manner without affecting the functionality or mechanical integrity of the electrically conductive interconnects and/or the electrically conductive structure and/or the one or more components when providing the specific architecture.

In particular, the connection region can achieve easy and direct electrical contact with the (four) wires of the (four-wire test) measuring device. Thus, the electrical resistance of the second electrically conductive interconnect can be reliably determined even though the electrically conductive interconnect may be buried in the layer stack. While conventional daisy-chain methods (see above) provide results with respect to all interconnects and electrically conductive structures (electrically) connected to all interconnects, the methods may provide separate results for electrically conductive interconnects so that defects may be detected more accurately and selectively. Furthermore, the method may provide more accurate results compared to conventional methods, which may detect not only interconnects with overall defects (e.g. complete disconnection of the metal structure), but also weaker interconnects, e.g. partial disconnection of the metal structure of the interconnect and (partial) defects of the interconnection of the electrically conductive interconnect with the corresponding component.

Furthermore, a statistical distribution of the measured power parameter, in particular the resistance, can be obtained, providing an accurate statement about the interconnect (process) quality of the component carrier, such as resistance measurement (map).

Exemplary embodiments

In an embodiment, a conductive sub-region is provided on one of the main surfaces of the test part, at least one of the exposed connection regions being electrically connected to one end portion of at least one of the second electrically conductive interconnects through the sub-region. Thus, the conductive subregion and the second electrically conductive interconnect simulate the respective component conductive subregion (e.g., connection region and/or pad) and electrically conductive interconnect such that: by connection with the exposed connection areas, electrical measurements of the second electrically conductive interconnects may be provided for accurate and reliable evaluation of the quality of the respective electrically conductive interconnects.

According to a further embodiment, the exposed connection regions are connected to the respective sub-regions by third electrically conductive interconnects. This may provide the following advantages: even if one end portion of a second electrically conductive interconnect is embedded in the component carrier stack, said end portion from (or joined to) the same exposed area can be connected with end portions of other second electrically conductive interconnects with a simple and inexpensive solution, i.e. a third electrically conductive interconnect connecting the exposed area with the sub-area is provided.

According to a further embodiment, the exposed further connection region is electrically connected to a further end portion of the respective at least one said second electrically conductive interconnect. Preferably, the exposed connection region and the exposed further connection region are provided on the same side of the component carrier. This may provide the following advantages: even if both end portions of the second electrically conductive interconnect are embedded in the component carrier stack, the (electrical) measurement of the second electrically conductive interconnect may be provided by two exposed areas provided on the same side of the component carrier.

According to a further embodiment, the further exposed region is connected to the further terminal portion by a fourth electrically conductive interconnect and/or by one of the at least two electrically conductive layer structures. This may provide the following advantages: even if the end portions of the second electrically conductive interconnects are embedded in the component carrier stack, they can be connected with the exposed areas by a simple and inexpensive solution, i.e. a fourth electrically conductive interconnect is provided which connects the exposed areas with the second electrically conductive interconnects.

According to a further embodiment, wherein at least one of the two end portions of the second electrically conductive interconnect is connected to two areas exposed on the same main surface of the component carrier. This may provide the following advantages: the result of the measurement performed by the measuring device is more accurate.

According to a further embodiment, each end portion of the second electrically conductive interconnect is connected to two areas exposed on the same main surface of the component carrier.

This may provide the following advantages: specific tests involving different and preferably simultaneous measurement members, such as FWTs involving current and voltage measurements, can be performed in a reliable manner, since the wires of one measurement member can be connected to two exposed areas each connected to a respective end portion of the second electrically conductive interconnect, while the wires of the other measurement member can be connected to two other exposed areas each connected to a respective end portion of the second electrically conductive interconnect.

According to a further embodiment, a plurality of second electrically conductive interconnections are provided on the component carrier, a plurality of said second electrically conductive interconnections being provided at different positions in the stacking direction. The advantage of the exposed areas on the same side of the component carrier allows providing the second electrically conductive interconnect at different positions with respect to the stacking direction (in terms of depth) of the stack, allowing electrical contact with the respective end portions by contact with the connected exposed areas. In other words, the location of the second electrically conductive interconnect does not affect its testing process, since the respective exposed areas are provided on the same side of the component carrier.

Each of the plurality of second electrically conductive interconnects may be disposed at the same position in the stacking direction as a corresponding electrically conductive interconnect disposed on the active region.

According to a further embodiment, a plurality of test elements are provided, which are arranged at different positions with respect to the stacking direction. Thus, in terms of the position of the test component in the stacking direction, the interaction between the electrically conductive interconnect and the component arranged in the region of action is simulated by the second electrically conductive interconnect and the test component, thus preferably reflecting the same process steps of the electrically conductive interconnect manufacture, in particular in terms of the layer-to-layer manufacturing process.

Each of the plurality of test components may be disposed at the same position in the stacking direction as a corresponding component disposed on the active region.

According to a further embodiment, the exposed areas respectively connected to a plurality of said second electrically conductive interconnects have an array-like arrangement on the main area of the component carrier. Thus, a large number of second electrically conductive interconnects (devices) may be tested from the same component carrier side (individually), even though at least some of them may be embedded in the stack.

According to a further embodiment, all exposed connection areas have the same surface. This allows the operator to immediately recognize the test area due to the specific pattern generated.

According to a further embodiment, the exposed connection region is tetragonal in shape. This shape provides the following advantages: the area where the line/test contact element has to ensure electrical contact between the measuring device and the end of the second electrically conductive interconnect is improved.

According to a further embodiment, the set of test elements, the respective second electrically conductive interconnections and the respective exposed connection areas are repeatedly arranged in the test area, preferably the set of test elements, the respective second electrically conductive interconnections and the respective exposed connection areas are repeatedly arranged in the test area along a linear direction. This may provide the following advantages: the measuring device can make (electrical) measurements more efficiently.

In particular, the second electrically conductive interconnects, the test components and the exposed connection regions of one group are identical and are disposed in the same position in terms of layer depth as the second electrically conductive interconnects, the test components and the exposed connection regions of the other group.

This provides an advantageous statistical and reliable interconnect quality assessment, as a batch of (electrical) measurements is made on a plurality of second electrically conductive interconnects having the same features/locations and interacting with corresponding test components.

According to a further embodiment, a plurality of subarrays of respective exposed connection areas are provided on the outer main surface of the component carrier. This provides the following advantages: by (electrical) measuring and quality evaluation of a second electrically conductive interconnect arranged in the vicinity of the area where said electrically conductive interconnect is arranged (and in case of a closer approach within the component carrier), evaluation of the electrically conductive interconnect, preferably the electrically conductive interconnect located in the region of action, is improved.

According to a further embodiment, a plurality of said second electrically conductive interconnects are connected on the same side of the test part, the plurality of said second electrically conductive interconnects being connected in series such that: each of the plurality of second electrically conductive interconnects is connected to an adjacent first second electrically conductive interconnect by a sub-region disposed on one of the major surfaces of the test part, and each of the plurality of second electrically conductive interconnects is connected to an adjacent second electrically conductive interconnect by a portion of one of the at least two electrically conductive layer structures, thereby forming a daisy chain structure. This may directly allow a reliable quality assessment of the interaction between the second electrically conductive interconnect and the test part via the daisy chain structure.

According to a further embodiment, each of the two electrical end portions of the daisy chain structure is electrically connected to one of the exposed connection areas, thereby simplifying the testing of the daisy chain structure.

According to a further embodiment, at least one of the two electrical terminal portions of the daisy chain structure is electrically connected to one of the exposed connection areas. This configuration also provides the following structure: the structure is adapted to check the quality of the interaction between the second electrically conductive interconnect and the test component using a specific measurement device, such as FWT in combination with a daisy chain test structure.

According to a further embodiment, at least one of the second electrically conductive interconnects comprises one of: blind vias, through holes, plated through holes, interconnects between component carriers, wires, nanowires, sputtered material, solder material, electrically conductive adhesive.

In an embodiment, a plurality of second electrically conductive interconnects is provided and stacked one above the other in the stack.

According to a further embodiment, the material of the surface of the test component to which the second electrically conductive interconnect is connected is the same as the material of the surface of the component to which the electrically conductive interconnect is connected. This increases the degree of simulation of the interaction between the second electrically conductive interconnect and the test component in terms of the close electrically conductive interconnect and component preferably arranged in the region of action.

According to a further embodiment, the connection joints between the test component and the respective second electrically conductive interconnect are identical to the connection joints between the respective component and the respective electrically conductive interconnect, thereby increasing the degree of simulation of the respective interaction.

More particularly, with the same connection bond, similar, preferably the same, shape and/or roughness and/or size and/or position (i.e. in the stacking direction) and/or structure (i.e. specific layers) and/or process steps are meant.

According to a further embodiment, the at least one power value obtained from the two exposed areas comprises a voltage or current intensity.

According to a further embodiment, the value evaluated by the at least one power value obtained is a resistance.

According to a further embodiment, a plurality of second electrically conductive interconnects and a plurality of exposed areas are provided, both end portions of each second electrically conductive interconnect being connected with two of the exposed areas, the method comprising the steps of; the quality of each further electrically conductive interconnect is evaluated in dependence on at least one electrical power value (preferably resistance and/or inductive reactance (of the inductor) and/or capacitive reactance (of the capacitor)) taken from the respective exposed region.

According to a further embodiment, a plurality of second electrically conductive interconnects are connected on the same side of the test part, the plurality of second electrically conductive interconnects being connected in series such that: each of the plurality of second electrically conductive interconnects is connected to an adjacent first second electrically conductive interconnect by a sub-region disposed on one of the major surfaces of the test part, and each of the second electrically conductive interconnects is connected to an adjacent second electrically conductive interconnect by a portion of one of the at least two electrically conductive layer structures, thereby forming a daisy chain structure, the method comprising the steps of: the quality of the further electrically conductive interconnect is evaluated from at least one electrical power value taken from both end portions of the daisy chain structure.

This may directly allow a reliable quality assessment of the interaction between the second electrically conductive interconnect and the test part via the daisy chain structure.

According to a further embodiment, the component carrier comprises a plurality of test areas on the (same) main surface, the method further comprising a carrier quality evaluation step of evaluating the quality of the electrically conductive interconnects located in the component carrier (active area) based on the evaluated quality of the second electrically conductive interconnects of the plurality of test areas.

This method provides a reliable quality assessment of the electrically conductive interconnects without interacting with the electrically conductive interconnects in the region of action.

In an embodiment, the component carrier is shaped as a plate. This contributes to a compact design, wherein the component carrier still provides a larger base for components mounted on the component carrier. Furthermore, a bare wafer, which is an example of an embedded electronic component in particular, can be conveniently embedded in a thin plate such as a printed circuit board due to a small thickness.

In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate) and an interposer.

In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and/or providing thermal energy. As a preferred material for PCB technology, the electrically conductive layer structure is made of copper, whereas the electrically insulating layer structure may comprise resin and/or glass fibres, so-called prepreg or FR4 material. The electrically conductive layer structures may be connected to each other in a desired manner by forming a via through the laminate, for example by laser drilling or mechanical drilling, and by filling the via with an electrically conductive material, in particular copper, thereby forming a via or any other via connection. The filled holes connect the entire stack, (via connections extend through multiple layers or the entire stack), or the filled holes connect at least two electrically conductive layers, referred to as vias. Similarly, optical interconnects may be formed through the various layers of the stack to receive the optoelectronic circuit board (EOCB). In addition to one or more components that may be embedded in a printed circuit board, the printed circuit board is typically configured to house the one or more components on one or both opposing surfaces of the board-like printed circuit board. The one or more components may be connected to the respective major surfaces by welding. The dielectric portion of the printed circuit board may be formed of a resin having reinforcing fibers, such as fiberglass.

In the context of the present application, the term "substrate" may particularly denote a smaller component carrier. The substrate may be a relatively small component carrier, relative to the PCB, on which one or more components may be mounted, and may serve as a connection medium between one or more chips and the further PCB. For example, the substrate may have substantially the same dimensions as the components (in particular electronic components) to be mounted on the substrate (e.g. in the case of Chip Scale Packages (CSPs)). In further embodiments, the substrate may be substantially larger than the designated components (e.g., in a flip chip ball grid array FCBGA configuration). More specifically, a substrate may be understood as a carrier for an electrical connector or electrical network as well as a component carrier comparable to a Printed Circuit Board (PCB) but having a rather high density of laterally and/or vertically arranged connectors. The lateral connectors are for example conductive paths, while the vertical connectors may be for example boreholes. These lateral and/or vertical connections are arranged within the base plate and may be used to provide electrical, thermal and/or mechanical connection of the accommodated components or the non-accommodated components (such as bare wafers), in particular IC chips, to the printed circuit board or to an intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrate". The dielectric portion of the substrate may comprise a resin with reinforcing particles, such as reinforcing spheres, in particular glass spheres.

The substrate or interposer may include or consist of: at least one layer of glass, silicon (Si), and/or photoimageable or dry etchable organic material such as an epoxy-based laminate material (e.g., an epoxy-based integrated film) or a polymeric compound (which may or may not include photosensitive and/or thermosensitive molecules) such as polyimide or polybenzoxazole.

In an embodiment, the at least one electrically insulating layer structure comprises one of: resins or polymers such as epoxy resins, cyanate ester resins, benzocyclobutene resins, bismaleimide-triazine resins, polyphenyl derivatives (e.g., based on polyphenylene ether, PPE), polyimides (PI), polyamides (PA), liquid Crystal Polymers (LCP), polytetrafluoroethylene (PTFE), and/or combinations thereof. Reinforcing structures such as meshes, fibers, spheres or other types of filler particles made of, for example, glass (multiple layer glass) may also be used to form the composite. The semi-cured resin combined with a reinforcing agent such as a fiber impregnated with the above resin is called a prepreg. These prepregs are often named for their properties, for example FR4 or FR5, FR4 or FR5 describing the flame retardant properties of the prepregs. While prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates (such as epoxy-based laminates) or photoimageable dielectric materials, may also be used. For high frequency applications, high frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and/or cyanate ester resins may be preferred. In addition to these polymers, low Temperature Cofired Ceramics (LTCC) or other low, very low or ultra low DK materials may be used as an electrically insulating layer structure in a component carrier.

In an embodiment, the at least one electrically conductive layer structure comprises at least one of: copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (particularly doped) silicon, titanium and platinum. Although copper is generally preferred, other materials or coated versions thereof, particularly coated with superconducting materials or conductive polymers such as graphene or poly (3, 4-ethylenedioxythiophene) (PEDOT), are also possible.

At least one further component may be embedded and/or surface mounted in the stack. The component and/or at least one further component may be selected from: a non-electrically conductive inlay, an electrically conductive inlay (e.g., a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g., a heat pipe), a light guiding element (e.g., an optical waveguide or a light conductor connection), an electronic component, or a combination thereof. The inlay may be, for example, a metal block with or without a coating of insulating material (IMS-inlay), which inlay may be embedded or surface mounted for the purpose of promoting heat dissipation. Suitable materials are defined in terms of the thermal conductivity of the material, which should be at least 2W/mK. Such materials are typically based on, but are not limited to, metals, metal oxides, and/or ceramics, such as copper, aluminum oxide (Al ₂O₃), or aluminum nitride (AlN). Other geometries with increased surface area are also often used in order to increase heat exchange capacity. Further, the components may be: active electronic components (implementing at least one pn junction), passive electronic components such as resistors, inductors or capacitors, electronic chips, memory devices (e.g., DRAM or other data storage), filters, integrated circuits (such as Field Programmable Gate Arrays (FPGAs), programmable Array Logic (PALs), general purpose array logic (GAL), and Complex Programmable Logic Devices (CPLDs)), signal processing components, power management components (such as Field Effect Transistors (FETs), metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductors (CMOS), junction Field Effect Transistors (JFETs), or Insulated Gate Field Effect Transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga ₂O₃), indium phosphide (InP), indium gallium arsenide (InGaAs), and/or any other suitable inorganic compound), optoelectronic interface elements, light emitting diodes, optocouplers, voltage converters (e.g., DC/DC converters or AC/DC converters), cryptographic components, transmitters and/or receivers, electromechanical actuators, micro-electromechanical systems, micro-processors, charge-controllers, power converters, micro-processors, charge-controllers, and power-collecting devices, and microprocessors. However, other components may also be embedded in the component carrier. For example, a magnetic element may be used as the member. Such magnetic elements may be permanent magnetic elements (e.g., ferromagnetic elements, antiferromagnetic elements, multiferroic elements, or ferrimagnetic elements, such as ferrite cores), or such magnetic elements may be paramagnetic elements. However, the component may also be a substrate, an insert or another component carrier, for example in the form of a plate in a plate. The component may be surface mounted on the component carrier and/or may be embedded in the interior of the component carrier. In addition, other components, in particular those that generate and emit electromagnetic radiation and/or are sensitive to electromagnetic radiation propagating from the environment, may also be used as components.

In an embodiment, the component carrier is a laminate component carrier. In such embodiments, the component carrier is a composite of a multi-layer structure that is stacked and joined together by the application of pressure and/or heat.

After the treatment of the inner layer structure of the component carrier, one main surface or the opposite main surfaces of the treated layer structure may be symmetrically or asymmetrically covered (in particular by lamination) with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, lamination may continue until the desired number of layers is obtained.

After the formation of the stack of electrically insulating layer structures and electrically conducting layer structures is completed, the resulting layer structure or component carrier may be surface treated.

In particular, in terms of surface treatment, an electrically insulating solder resist may be applied to one major surface or the opposite two major surfaces of the layer stack or component carrier. For example, such a solder resist may be formed over the entire major surface and the layer of solder resist subsequently patterned to expose one or more electrically conductive surface portions for electrically coupling the component carrier to the electronic periphery. The surface portions of the component carrier that are covered with the solder resist, in particular the copper-containing surface portions, can be effectively protected from oxidation or corrosion.

In terms of surface treatment, a surface treatment may also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such surface treatments may be electrically conductive covering materials on exposed electrically conductive layer structures (e.g., pads, conductive traces, etc., particularly including or consisting of copper) on the surface of the component carrier. Without protection of such exposed electrically conductive layer structures, the exposed electrically conductive component carrier material (particularly copper) may be oxidized, thereby making the component carrier less reliable. The surface treatment may then be formed as a joint between, for example, a surface mounted component and a component carrier. The surface treatment has the function of protecting the exposed electrically conductive layer structure, in particular the copper circuit, and the surface treatment may effect a bonding process with one or more components, for example by soldering. Examples of suitable materials for the surface treatment are Organic Solderability Preservative (OSP), electroless Nickel Immersion Gold (ENIG), electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (particularly hard gold), electroless tin (chemical and electroplated), nickel gold, nickel palladium, and the like. Nickel-free materials may also be used as surface treatments, particularly for high speed applications. Examples are ISIG (immersion silver immersion gold), and EPAG (electroless palladium autocatalytic gold).

Drawings

The aspects defined above and further aspects of the invention are apparent from the embodiments to be described hereinafter and are explained with reference to examples of these embodiments.

Fig. 1 illustrates a second electrically conductive interconnect located in a test area according to an exemplary embodiment of the present invention.

Fig. 2 shows a cross section of a test area according to an exemplary embodiment of the invention.

Fig. 3 shows a top view of a test area with a connection area according to an exemplary embodiment of the invention.

Fig. 4 shows a top view of a component carrier with an active area and a test area according to an exemplary embodiment of the invention.

Fig. 5 shows a top view of a test area with a connection area according to an exemplary embodiment of the invention according to a further embodiment.

Fig. 6 shows a cross section of a test area according to a further exemplary embodiment of the invention.

Detailed Description

The illustrations in the figures are schematic. It should be noted that in different figures, similar or identical elements or features are provided with the same reference numerals or with the following reference numerals: these reference numerals differ from the corresponding reference numerals only in the first digit. Elements or features that have been elucidated with respect to the previously described embodiments are not elucidated in the following description in order to avoid unnecessary repetition.

Furthermore, spatially relative terms, such as "front" and "rear," "upper" and "lower," "left" and "right," and the like, are used to describe an element's relationship to another element(s) as illustrated in the figures. Thus, spatially relative terms may be applied to orientations that differ from the orientation depicted in the figures in use. It is to be understood that all such spatially relative terms are intended to refer to the orientations shown in the figures for purposes of illustration only and are not necessarily limiting.

Fig. 1 shows a cross-sectional view of a cross-section of a test area 150 of a component carrier 100 according to an exemplary embodiment of the invention, the component carrier 100 comprising a layer stack 101 with two electrically conductive layer structures 130, 130' and one electrically insulating layer structure 102. The electrically insulating layer structure 102 may comprise a reinforcing material, such as glass fibers and/or glass spheres. In addition, the electrically insulating layer structure 102 exposed on the surface of the component carrier may comprise a surface treatment 112, such as a solder resist. The two electrically conductive layer structures 130, 130' may be interconnected vertically by a plurality, in particular three, electrically conductive interconnects 120, 121, 125.

In particular, one of the three electrically conductive interconnects, hereinafter referred to as second electrically conductive interconnect 125, may be provided with the same mechanical/chemical features as at least one of the plurality of electrically conductive interconnects provided in the active region 200 as described below, and/or the second electrically conductive interconnect 125 may be provided with the same location in depth as the at least one electrically conductive interconnect described above. The second electrically conductive interconnect 125 may be configured as a blind via, such as a blind via formed by laser drilling, which produces a tapered shape. The upper portion of the second electrically conductive interconnect 125 is referred to as the "first end portion". In this example, the first end portion is configured as a connection region 140 and is exposed on a major surface of the component carrier 100. The connection region 140 may include a surface treatment 112, such as ENIPEG. In further examples, the first end portion may be embedded in the layer stack 101. The lower portion of the second electrically conductive interconnect 125 is opposite the first end portion and is referred to as a "second end portion". The second end portion may be (electrically) connected to the sub-region and embedded in the layer stack 101.

The sub-regions may be (electrically) connected to the (exposed) main surface of the same side of the layer stack 101 by at least one, in this example three, connection regions (connection regions and/or further connection regions) 140 and may be (electrically) connected to the test component 180. The test component 180 may have a region to which the second electrically conductive interconnect 125 is connected, the region having the same mechanical/chemical characteristics as the corresponding component disposed in the active region 200 described below, and/or the region having the same location in depth as the corresponding component described above.

The measuring device 160, 170 is schematically shown in fig. 1, i.e. a measuring device for a four-wire test, comprising four connection wires which are moved into contact with the exposed areas 140 connected to the three electrically conductive interconnects 120, 121, 125 for testing the second electrically conductive interconnect 125. In particular, the first and second lines of the current measuring device (e.g., ammeter/ammeter) 160 are connected to the exposed area and the further exposed area, respectively, and the third and fourth lines of the voltage measuring device (e.g., voltmeter) 170 are connected to the further exposed area and the further exposed area, respectively.

Due to the fact that the first end portion of the second electrically conductive interconnect 125 is aligned with and/or exposed to the major surface of the component carrier, a respective one of the current measurement device 160 and the voltage measurement device 170 is directly connected with the first end portion. On the other hand, as a second end portion of the second electrically conductive interconnect 125 embedded in the component carrier 100, the connection to the respective further lines in the current measuring device 160 and the voltage measuring device 170 is provided by an electrical connection of the sub-region to the second end portion and to one of the other two electrically conductive interconnects 120, 121, each of the electrically conductive interconnects 120, 121 preferably having one end portion exposed to the same component carrier main surface to which the first end portion of the second electrically conductive interconnect 125 is exposed, thereby exposing the surface of all lines that need to be connected to the measuring device 160, 170 on the same area of the component carrier 100 to provide an electrical connection to both end portions of the second electrically conductive interconnect 125.

The features of the second electrically conductive interconnect 125 simulate all features of one or more electrically conductive interconnects disposed in the active region 200 due to the interaction of the second end portion with the surface of the test component 180, as described below.

Fig. 2 shows another cross-sectional view of a test area 150 of the component carrier 100 as a further exemplary embodiment. Unlike the previous embodiments, the second electrically conductive interconnect 125 is fully embedded in the component carrier such that the upper end portion is also not directly exposed through the exposed region. In this example, three electrically conductive layer structures 130, 130', 130 "are disposed at three different component carrier locations above the major surface of the test component 180. In particular, at least a portion of one (bottom) electrically-conductive layer structure 130 of the three electrically-conductive layer structures is in contact with a surface of the test part 180, thereby providing a connection with the second end portion of the second electrically-conductive interconnect 125. On the other hand, at least a portion of the middle one 130' of the three electrically conductive structures is connected to the first end portion of the second electrically conductive interconnect 125. In addition, the upper electrically-conductive layer structure 130 "of the three electrically-conductive layer structures includes at least two exposed regions (not connected to each other).

In the illustrated embodiment, the connection between the first end portion of the second electrically conductive interconnect 125 and one of the exposed regions 140 is preferably provided by (further) electrically conductive interconnects (i.e. vias) 135 connecting the electrically conductive layer structure 130' of the middle (i.e. connected to the upper end portion of the second electrically conductive interconnect 125) preferably to the electrically conductive layer structure 130″ of the upper (i.e. connected to one of the exposed regions 140).

According to further embodiments, the connection between the second end portion of the second electrically conductive interconnect 125 and the other one of the exposed regions 140' is provided by connecting the bottom (i.e. the bottom end portion connected to the second electrically conductive interconnect 125) electrically conductive layer structure 130 to the upper (i.e. the other one of the exposed regions 140 ') electrically conductive interconnect (i.e. the via) 135' of the electrically conductive layer structure 130 ".

Even though the second electrically conductive interconnect 125 is fully embedded in the component carrier 100, exposing all surfaces of the wires that are needed to connect the measurement devices 160, 170 on the same area of the component carrier 100 allows electrical connection with both end portions of the second electrically conductive interconnect 125.

Fig. 3 shows a top view of a test area 150 according to a preferred exemplary embodiment of the solution disclosed in fig. 2. In this example, two end portions of the second electrically conductive interconnect 125 are each connected to two exposed regions 140, 140'. Preferably, the electrically conductive layer structure 130 and the (further) electrically conductive interconnect 135 are configured to connect the exposed regions 140 and 140 'with a first end portion of the second electrically conductive interconnect 125 and to connect the exposed regions 140 "and 140'" to a second end portion of the second electrically conductive interconnect 125.

As shown in fig. 3, the four exposed regions 140, 140', 140", 140'" preferably have an array-like arrangement 142 on the main surface region of the component carrier 100, preferably the four exposed regions 140, 140', 140", 140'" each comprise a quadrangular connection region. Each element 142 (connection region, further connection region) of the array may have similar/identical mechanical/chemical characteristics.

By connecting the first and second lines of the current measurement device 160 and the third and fourth lines of the voltage measurement device 170 to each of the connection regions 140 such that each of the current measurement device 160 and the voltage measurement device 170 is electrically connected to both end portions of the second electrically conductive interconnect 125, a quality of the second electrically conductive interconnect 125 in terms of at least one power value may be obtained.

Fig. 4 shows a top view of a component carrier 100 according to a further embodiment. In this example, the component carrier 100 includes: a plurality, in particular six, active areas 200, each comprising a stack of at least two electrically conductive layer structures and at least one electrically insulating layer structure; a plurality of components disposed in or on the stack; and a plurality of electrically conductive interconnects in the stack. The active area 200 may be exposed to a major surface of the component carrier 100. Additionally and/or alternatively, the active area 200 may be embedded in the stack. The component carrier 100 further comprises a plurality, in particular thirteen, of test areas 150, each of which is spatially close to at least one active area 200. Each of the plurality of test areas 150 preferably includes an array 142 of exposed areas 140 as shown in fig. 4 (see detailed view below), the exposed areas 140 being seven repetitions (L1-L7) of the exposed areas 140 of fig. 3. From a statistical perspective, this improves the quality assessment of the electrically conductive interconnects located in the active area in the vicinity of the array 142.

Each of the plurality of test areas 150 preferably includes at least one test component 180 and at least one second electrically conductive interconnect 125, the test component 180 having an area to which the second electrically conductive interconnect 125 is connected, the area having the same mechanical/chemical characteristics as a corresponding one of the plurality of components located in an adjacent active area portion 140 and/or the area having the same location in depth as the corresponding one of the plurality of components, the second electrically conductive interconnect 125 having the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnects disposed in an adjacent active area portion, and/or the second electrically conductive interconnect 125 having the same location in depth as the at least one electrically conductive interconnect. Thus, the electrical measurement and associated quality/integrity assessment of the second electrically conductive interconnect 125 is used to assess the quality/integrity of electrically conductive interconnects disposed in adjacent active area portions.

Fig. 5 shows a further top view of a test region 150 of the component carrier 100 according to a further embodiment. The difference from fig. 3 is that the test area 150 comprises a daisy chain structure 126 comprising a plurality of second electrically conductive interconnects 125 which are suitably connected as described later. As can be seen in the enlarged view, the daisy chain structure 126 may be (electrically) connected to a plurality, in particular four, connection areas 140 by second and/or third and/or fourth electrically conductive interconnects, respectively. In this example, the daisy chain structure 126 may be embedded in the stack.

In an alternative example, the daisy chain structure 126 may be exposed on the (main) surface of the stack 101. In this example, the daisy chain structure 126 may include a plurality of the second electrically conductive interconnects 125 connected on the same side of the test part 180, the plurality of second electrically conductive interconnects 125 being connected in series such that: each of the plurality of second electrically conductive interconnects 125 is connected to an adjacent first second electrically conductive interconnect by a sub-region disposed on one of the major surfaces of the test part 180 and to an adjacent second electrically conductive interconnect by a portion of one of the (the at least two) electrically conductive layer structures.

Fig. 6 shows another cross-sectional view of the test area 150 of the component carrier 100 according to an exemplary embodiment. In addition to fig. 2, the stack 101 comprises ten further electrically conductive layer structures 130 and nine electrically insulating layer structures 102. The test part 180 is embedded in the stack 101 centrally in the stacking thickness direction of the stack, sandwiched between a plurality of further electrically conductive layer structures 130 and electrically insulating layer structures 102. The test component 180 is electrically connected to the connection regions 140, and/or further connection regions 140', and/or other connection regions exposed on the (main) surface by a plurality, in particular two, of series of third electrically conductive interconnects 135 and/or fourth electrically conductive interconnects 135' and/or further electrically conductive layer structures 130 '.

Reference numerals

100. Component carrier

101. Stacked piece

102. Electrically insulating layer structure

112. Surface treatment part

120. Electrically conductive interconnect

121. Additional electrically conductive interconnects

125. Second electrically conductive interconnect

126. Daisy chain structure

130. Electrically conductive layer structure

135. Third electrically conductive interconnect

135' Fourth electrically conductive interconnect

140. Connection region, exposure region

140' Further connection regions, further exposed regions

142. Array-like member

150. Test area

160. Current measuring device

170. Voltage measuring device

180. Test part

181. Conductive subregions.

Claims

1. A component carrier (100), wherein the component carrier (100) comprises:

A stack (101), the stack (101) comprising at least two electrically conductive layer structures (130, 130') and at least one electrically insulating layer structure (102);

-a plurality of components arranged in said stack (101) or on said stack (101);

A plurality of electrically conductive interconnects (120, 121), the plurality of electrically conductive interconnects (120, 121) being located in the stack (101) and electrically connecting at least one electrically conductive layer structure (130) with a respective component; and

A test area (150), the test area (150) being provided in a portion of the component carrier (100), the test area (150) comprising at least one test component (180) and at least one second electrically conductive interconnect (125),

The test part (180) has the following regions: the second electrically conductive interconnect (125) is connected at the region and the region has the same mechanical/chemical characteristics as a corresponding one of the plurality of components and/or the region has the same location in depth as a corresponding one of the plurality of components,

The second electrically conductive interconnect (125) having the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnects (120, 121) and/or the second electrically conductive interconnect (125) having the same location in depth as at least one of the plurality of electrically conductive interconnects,

Wherein a connection region (140) is exposed on the same side of the component carrier (100),

The exposed connection regions (140) are electrically connected to both end portions of at least one of the second electrically conductive interconnects (125), respectively.

2. The component carrier (100) according to claim 1, wherein a conductive sub-region (181) is provided on one of the main surfaces of the test component (180), at least one of the exposed connection regions (140) being electrically connected to one end portion of at least one of the second electrically conductive interconnects (125) by means of the sub-region (181).

3. The component carrier (100) according to claim 2, wherein the exposed connection regions (140) are connected to the respective sub-regions (181) by third electrically conductive interconnects (135).

4. The component carrier (100) according to one of claims 2 to 3, wherein a further end portion of the respective at least one second electrically conductive interconnect (125) is electrically connected with an exposed further connection region (140').

5. Component carrier (100) according to claim 4, wherein the exposed further connection region (140 ') is connected to the other end portion by a fourth electrically conductive interconnect (135 ') and/or by one of the at least two electrically conductive layer structures (130, 130 ').

6. The component carrier (100) according to one of claims 1 to 5, wherein at least one of the two end portions of the second electrically conductive interconnect (125) is connected to the connection region (140) and the further connection region (140') exposed on the same main surface of the component carrier (100).

7. The component carrier (100) according to claim 6, wherein each end portion of the second electrically conductive interconnect (125) is connected to the connection region (140) and the further connection region (140') exposed on the same main surface of the component carrier (100).

8. Component carrier (100) according to one of claims 1 to 5, wherein a plurality of second electrically conductive interconnects (125) are provided on the component carrier (100), the plurality of second electrically conductive interconnects (125) being provided at different positions in the stacking direction.

9. The component carrier (100) according to one of claims 1 to 5, wherein the exposed connection region (140) and the exposed further connection region (140') respectively connected to a plurality of the second electrically conductive interconnects (125) have an array-like arrangement (142) on a main region of the component carrier (100).

10. The component carrier (100) according to claim 9, wherein all exposed connection areas (140) have the same surface.

11. The component carrier (100) according to one of claims 6 to 10, wherein the exposed connection region (140) is tetragonal in shape.

12. Component carrier (100) according to one of claims 1 to 11, wherein a set of test components (180), respective second electrically conductive interconnects (125) and respective exposed connection regions (140) are repeatedly arranged in the test region (150), preferably wherein a set of test components (180), respective second electrically conductive interconnects (125) and respective exposed connection regions (140) are repeatedly arranged in the test region (150) along a linear direction.

13. The component carrier (100) according to one of claims 1 to 12, wherein a plurality of sub-arrays of respective exposed connection areas (140) are provided on an outer main surface of the component carrier (100).

14. The component carrier (100) according to one of claims 1 to 5, wherein a plurality of the second electrically conductive interconnects (125) are connected on the same side of the test component (180), the plurality of second electrically conductive interconnects (125) being connected in series such that:

each of the plurality of second electrically conductive interconnects (125) is connected to an adjacent first second electrically conductive interconnect by a sub-region disposed on one of the major surfaces of the test part (180), and

Each second electrically conductive interconnect of the plurality of second electrically conductive interconnects (125) is connected to an adjacent second electrically conductive interconnect by a portion of one of the at least two electrically conductive structures, thereby forming a daisy chain structure (126).

15. The component carrier (100) of claim 14, wherein each of the two electrical end portions of the daisy-chain structure (126) is electrically connected to one of the exposed connection areas (140).

16. The component carrier (100) according to claim 15, wherein at least one of the two electrical end portions of the daisy chain structure (126) is electrically connected to two of the exposed connection areas (140).

17. The component carrier (100) according to one of claims 1 to 16, wherein at least one of the second electrically conductive interconnects (125) comprises one of: blind vias, through holes, plated through holes, interconnects between component carriers, wires, nanowires, sputtered material, solder material, electrically conductive adhesive.

18. The component carrier (100) according to one of claims 1 to 17, wherein the material of the surface of the test component (180) to which the second electrically conductive interconnect (125) is connected is the same as the material of the surface of the component to which the electrically conductive interconnect is connected.

19. The component carrier (100) according to one of claims 1 to 18, wherein the connection joint between the test component (180) and the respective second electrically conductive interconnect (125) is identical to the connection joint between the respective component and the respective electrically conductive interconnect.

20. A method for inspecting quality of an electrically conductive interconnect of a component carrier (100), the component carrier (100) comprising:

-a plurality of components arranged in the stack (101) or on the stack (101); and

-A plurality of electrically conductive interconnects (120, 121) electrically connecting at least one electrically conductive layer structure with a respective component, and

At least one test area (150), said test area (150) being arranged in a portion of said component carrier (100), said test area (150) comprising at least one test component (180) and at least one second electrically conductive interconnect (125),

The test part has the following areas: the second electrically conductive interconnect (125) is connected at the region and the region has the same mechanical/chemical characteristics as a corresponding one of the plurality of components and/or the region has the same location in depth as a corresponding one of the plurality of components, the second electrically conductive interconnect (125) has the same mechanical/chemical characteristics as at least one of the plurality of electrically conductive interconnects (120, 121) and/or the second electrically conductive interconnect (125) has the same location in depth as at least one of the plurality of electrically conductive interconnects (120, 121),

Wherein,

Both end portions of at least one of the second electrically conductive interconnections (125) are connected to respective connection areas (140) exposed on the same side of the component carrier (100),

The method comprises the following steps: the quality of the second electrically conductive interconnect (125) is evaluated from at least one electrical power value obtained from two exposed connection areas (140).

21. The method of claim 20, wherein the at least one power value obtained from two exposed connection areas (140) comprises a voltage or current intensity.

22. The method according to one of claims 20 to 21, wherein the value evaluated by the acquired at least one power value is a resistance.

23. The method according to one of claims 20 to 22, wherein a plurality of second electrically conductive interconnects (125) and a plurality of exposed connection regions (140) are provided, two end portions of each second electrically conductive interconnect (125) being connected with two of the exposed connection regions (140), the method comprising the steps of: the quality of each further electrically conductive interconnect is evaluated from at least one electrical power value obtained from the respective exposed connection region (140).

24. The method of one of claims 20 to 23, wherein a plurality of the second electrically conductive interconnects (125) are connected on the same side of the test component (180), the plurality of second electrically conductive interconnects (125) being connected in series such that: each of the plurality of second electrically conductive interconnects (125) is connected to an adjacent first second electrically conductive interconnect by a sub-region disposed on one of the major surfaces of the test part (180), and each of the plurality of second electrically conductive interconnects (125) is connected to an adjacent second electrically conductive interconnect by a portion of one of the at least two electrically conductive layer structures (130, 130'), thereby forming a daisy chain structure (126), the method comprising the steps of: the quality of the further electrically conductive interconnect is evaluated from at least one electrical power value obtained from both end portions of the daisy chain structure (126).

25. The method according to one of claims 20 to 24, wherein the quality evaluation of each electrically conductive interconnect is influenced by the evaluated quality of the second electrically conductive interconnect (125) belonging to the closest test area (150) having the same mechanical/chemical characteristics and/or the same location.

26. The method according to one of the claims 20 to 25, wherein,

The component carrier (100) comprises a plurality of test areas (150) on a main surface, in particular the component carrier (100) comprises a plurality of test areas (150) on the same main surface,

The method further comprises a carrier quality assessment step of assessing the quality of electrically conductive interconnects located in the component carrier (100) based on the assessed quality of the second electrically conductive interconnects (125) of the plurality of test areas (150).