CN118041347A - Ultra-wideband phase-locked loop circuit - Google Patents

Abstract

The invention discloses an ultra-wideband phase-locked loop circuit, and relates to the technical field of semiconductor integrated circuits. The ultra-wideband phase-locked loop circuit provided by the invention comprises a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain device, a low-pass filter, a ring voltage-controlled oscillator, a prescaler and a multi-harmonic mixer which are connected in sequence; the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division; the prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing; the multi-harmonic mixer is used for extracting and obtaining a mixed output signal; the phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal; the ring voltage-controlled oscillator is used for obtaining an output frequency signal after the loop is locked, and a plurality of harmonic mixer loops can be used for replacing a traditional frequency divider loop to expand the output frequency range while restraining the quantization noise of the differential integral modulator, so that the application field is expanded, and the reliability and the stability of the phase-locked loop circuit can be improved.

Description

Ultra-wideband phase-locked loop circuit

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to an ultra-wideband phase-locked loop circuit.

Background

The design of the integrated circuit of the phase-locked loop is mainly divided into an integer phase-locked loop and a fractional phase-locked loop, and compared with the integer phase-locked loop, the output frequency of the fractional phase-locked loop can be the fractional multiple of the input frequency, so that the fractional phase-locked loop has higher frequency resolution. Meanwhile, the phase-locked loop can be divided into a inductive phase-locked loop and a non-inductive phase-locked loop according to the difference of VCOs (voltage-controlled oscillators). The inductance type phase-locked loop adopts the LC-VCO, and the circuit structure has the advantages of low phase noise, high output frequency and the like, but the circuit has the defects of larger general layout area, lower output frequency range and the like due to the existence of the inductance in the circuit. The non-inductance phase-locked loop adopts Ring_VCO (annular voltage controlled oscillator), and the circuit structure has the advantages of layout area, low output frequency range, low design complexity and the like, but compared with the phase-locked loop with inductance, the non-inductance phase-locked loop has the defects of higher phase noise, lower output frequency and the like. Therefore, a trade-off needs to be made in terms of area and performance for different requirements to choose an optimal circuit architecture.

At present, an existing fractional phase-locked loop architecture is composed of a crystal oscillator, an auxiliary integer phase-locked loop, an auxiliary fractional phase-locked loop and a fractional frequency divider, wherein a front-end auxiliary part is formed by the fractional phase-locked loop, and a rear-end main phase-locked loop mainly comprises a phase discriminator, a low-pass filter, an LC voltage-controlled oscillator and a harmonic mixer. The harmonic mixer is adopted to replace a frequency divider in a main loop, so that the loop transfer function is successfully used as a unit transfer function, but three phase-locked loops exist in the circuit, so that the power consumption and the complexity of the circuit are increased, and the output frequency of the loop is only 2GHz, so that the circuit has certain limitation in the application field.

Another existing compact and flexible single LC VCO with a wide output frequency range is mainly composed of a fractional phase locked loop, a 1.5-fold frequency divider (Div-1.5) with a duty cycle of 50% and a 1/2/4/8 frequency divider, and in order to meet the PAM-4 transmitter output condition of 56Gb/s, a duty cycle corrector circuit (DCC) is also added in the circuit, and the mode of adding DDiv-1.5 by a digital phase locked loop is used instead of using a plurality of LC VCOs in most schemes to realize the ultra-large frequency range output. However, nothing in the whole framework is particularly suppressed in the DSM quantization noise in the framework, so the phase noise performance of the fractional phase-locked loop is not satisfactory.

In summary, the existing phase-locked loop circuit has higher power consumption and complexity, and has certain limitation in application field due to smaller loop output frequency, and higher phase noise, which results in lower reliability and stability of the existing phase-locked loop circuit.

Disclosure of Invention

The invention aims to provide an ultra-wideband phase-locked loop circuit, which solves the problems of lower reliability and stability of the existing phase-locked loop circuit caused by certain limitation in the application field and higher phase noise due to the fact that the power consumption and complexity of the existing phase-locked loop circuit are higher.

The invention provides an ultra-wideband phase-locked loop circuit, which comprises a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain device, a low-pass filter and a ring voltage-controlled oscillator which are sequentially connected, wherein the input end of the differential integral modulator is connected with the input end of the phase discriminator; the circuit further comprises: the input end of the multi-harmonic mixer is connected with the output end of the annular voltage-controlled oscillator;

the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal;

The prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing;

the multi-harmonic mixer is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal;

The phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal;

The gain device and the low-pass filter are used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator;

The annular voltage-controlled oscillator is used for controlling the frequency of the output signal based on the voltage signal, and obtaining an output frequency signal after the loop is locked.

Compared with the prior art, the ultra-wideband phase-locked loop circuit provided by the invention comprises a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain device, a low-pass filter and a ring voltage-controlled oscillator which are sequentially connected, wherein the input end of the differential integral modulator is connected with the input end of the phase discriminator; the circuit further comprises: the input end of the multi-harmonic mixer is connected with the output end of the annular voltage-controlled oscillator; the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal; the prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing; the multi-harmonic mixer is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal; the phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal; the gain device and the low-pass filter are used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator; the ring voltage controlled oscillator is used for controlling the frequency of an output signal based on the voltage signal, obtaining the output frequency signal after the loop is locked, and replacing the traditional frequency divider loop with a multi-harmonic mixer loop to expand the output frequency range while restraining the quantization noise of the differential integral modulator, so that the application field is expanded, and the reliability and the stability of the phase-locked loop circuit can be improved.

In one possible implementation manner, the multi-mode frequency divider is composed of multiple stages of cascaded frequency dividers, and the frequency division ratio corresponding to each stage of frequency dividers is 2 or 3.

In one possible implementation manner, the differential integral modulator and the multi-modulus frequency divider are used for forming fractional frequency division, and the fractional frequency division processing is performed on an input signal to obtain a fractional frequency division signal, which includes:

the differential integral modulator is used for determining a fractional frequency division ratio based on a frequency control signal and an average value of frequency division control in a certain time;

The differential integral modulator is used for controlling the multi-mode frequency divider to carry out frequency division processing based on the fractional frequency division ratio and outputting a fractional frequency division signal by the multi-mode frequency divider.

In one possible implementation, the prescaler is configured to divide an input signal into a baseband signal for post-mixing, and includes:

the prescaler is used for prescaler processing the input signal to obtain the fundamental frequency signal serving as the harmonic mixer.

In one possible implementation manner, the multiple harmonic mixer is configured to mix the fundamental frequency signal with an output signal of the ring voltage-controlled oscillator according to a requirement, and extract the fundamental frequency signal to obtain a mixed output signal, where the multiple harmonic mixer includes:

The multi-harmonic mixer is used for convolving the fundamental frequency signal with the output signal of the annular voltage-controlled oscillator and filtering out the mixed output signal through the low-pass filter.

In one possible implementation, the gain and the low pass filter are configured to convert the phase difference into a voltage signal that controls the output of the ring voltage controlled oscillator, including:

The gain device is used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator;

The low-pass filter is used for filtering the voltage signal and outputting the filtered voltage signal.

In one possible implementation, the ring voltage controlled oscillator is a loop formed by a pseudo-differential inverter architecture in a three-division cascade, and the control supply voltage and the access capacitance are used to control the output frequency and control voltage variation resulting in a voltage controlled oscillator output frequency variation.

In one possible implementation, the control voltage variation causes a slope of the voltage controlled oscillator output frequency variation

Wherein Δf _vco represents the voltage controlled oscillator output frequency variation value; deltaV _c represents the control voltage difference.

In one possible implementation, the differential integral modulator is configured to determine a fractional division ratio based on a frequency control signal and an average value of control division over a time period, and includes:

the differential integral modulator is used for controlling the decimal frequency division signal by inputting Nxbit decimal frequency control words into a digital circuit mode And the integer part frequency control word is Nbit digital signal, output as adding the frequency control word Nbit frequency division control signal of decimal component;

The differential integral modulator is used for determining the average value of the frequency control word FCW signal and the frequency division control within a certain time as the fractional frequency division ratio Na.

In one possible implementation, the multiple harmonic mixer is configured to convolve the fundamental frequency signal with an output signal of the ring voltage controlled oscillator, and filter the mixed output signal through the low pass filter, including:

The multi-harmonic mixer is configured to convolve the fundamental frequency signal with an output signal of the ring voltage-controlled oscillator, and set an upper limit cut-off frequency of a low-pass filter in the harmonic mixer to a preset frequency within a preset frequency range, so as to obtain the mixed output signal corresponding to a target mixed output signal frequency.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

fig. 1 shows a schematic circuit diagram of a conventional fractional phase-locked loop architecture;

Figure 2 shows a circuit schematic of a conventional compact flexible single LC VCO with a fractional phase locked loop of a wide output frequency range;

FIG. 3 illustrates an embodiment of the present invention providing an ultra wideband phase locked loop circuit;

FIG. 4 is a schematic coverage of mixing output preference frequencies of a multi-harmonic mixer according to an embodiment of the present invention;

Fig. 5 shows a schematic diagram of a scenario of an ultra-wideband phase-locked loop circuit corresponding to frequency mixing by using an N1 harmonic according to an embodiment of the present invention;

Fig. 6 shows a schematic diagram of a scenario of an ultra-wideband phase-locked loop circuit corresponding to frequency mixing by using an N2 harmonic according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a scenario of an ultra-wideband phase-locked loop circuit corresponding to frequency mixing using an N3 harmonic according to an embodiment of the present invention;

Fig. 8 shows a schematic diagram of a scenario of an ultra-wideband phase-locked loop circuit corresponding to frequency mixing by using N4 harmonic waves according to an embodiment of the present invention.

Reference numerals:

a DSM-differential integrating modulator, an MMD-multimode divider,

A PD-phase detector, a GM-gain,

LPF-low pass filter, ringVCO-ring voltage controlled oscillator,

PDIV-prescaler, HM-multiple harmonic mixer.

Detailed Description

In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.

In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.

The most outstanding difference between the fractional phase-locked loop and the integer phase-locked loop is that the fractional phase-locked loop can utilize a Sigma-Delta modulator to control a multi-mode frequency divider to carry out fractional frequency division on output frequency, and finally the fractional frequency divider is fed back to a phase frequency detector to realize the fractional phase-locked loop circuit. The use of Sigma-Delta modulator circuits, while capable of achieving the purpose of dividing the output frequency by a fraction, introduces significant quantization noise into the loop. Silicon-based fractional phase-locked loop circuits have been widely studied by the academia from 2000 to 2023. Most of the literature from 2000 to 2008 has mainly studied Sigma-Delta modulator circuits in fractional phase-locked loop circuits. With the continuous development of semiconductor process technology in 2010 to 2023, the output frequency of the fractional phase-locked loop is continuously improved by utilizing a smaller characteristic size process, the power consumption is also improved to a certain extent, and the performance is continuously enhanced. A phase locked loop design based on harmonic mixing techniques was proposed in Sankaran Aniruddhan et al, 2010 TCASI. Then DIHANG YANG et al in 2019 ISSCC applied harmonic mixing techniques to fractional phase locked loops and made significant efforts in fractional phase locked loop circuit design in the next two years. At the same time, the university of tokyo Masaru Osada et al have developed intensive analyses and studies on harmonic mixing techniques and applied the technique to fractional phase-locked loop circuits at 2022.

The ultra-wide output frequency range decimal phase-locked loop is also the focus of research of scholars at home and abroad. The university of Zhejiang, xiang Gao et al, in 2022, in TCAS II paper, proposed a 0.73-15.5GHz high performance LC_VCO based phase locked loop circuit with an ultra-wide output frequency range. The wide frequency coverage for radar systems determines the detection range and detection accuracy of the radar system. For data transmission systems, the wide frequency range determines the compatibility of a variety of data transmission protocols. For bluetooth or other communication systems, the wide frequency coverage determines the link efficiency of the devices. UWB technology such as apple and star flash technology, which are in use, are both indispensable in these systems for phase-locked loops of ultra-wide output frequency range.

On the one hand, modern communication standards require radio frequency clocks with very low phase errors and low spurs. High performance phase locked loops, however, tend to suffer from two problems: in order to reduce the quantization noise of the DSM, a time-to-digital converter (TDC) is often used in the circuit to suppress the quantization noise of the Sigma-Delta modulator (DSM), but there is also nonlinearity and quantization noise, and the nonlinearity of the DTC causes larger spurious generation in the loop as a whole, and the quantization noise of the circuit is also converted into phase noise of the whole circuit. High performance fractional phase locked loops require complex TDC structures and calibration circuits that fit TDCs.

However DIHANG YANG et al in 2019 in the ISSCC article proposed a fractional phase-locked loop architecture without DTC circuitry and corresponding calibration circuitry, in which the architecture is comprised of a main phase-locked loop and two auxiliary phase-locked loops, which combines the advantages of sub-sampling phase-locked loops and switched PD, achieving 131fs jitter and fractional spurs below-70 dBc.

The three-ring phase lock loop architecture is based on harmonic mixing technology proposed by Sankaran Aniruddhan et al in 2011, TCASI, and a specific architecture diagram is shown in fig. 1. The decimal phase-locked loop structure comprises a crystal oscillator, an auxiliary integer phase-locked loop, an auxiliary decimal phase-locked loop and a decimal frequency divider, wherein the front end auxiliary part is formed by the decimal frequency divider, and the rear end main phase-locked loop mainly comprises a phase discriminator, a low-pass filter, an LC voltage-controlled oscillator and a harmonic mixer. The decimal phase-locked loop part of the architecture mainly provides a reference clock signal f _fac with decimal frequency division for the main phase-locked loop, the auxiliary integer phase-locked loop provides a mixing signal f _iac for the main phase-locked loop, and the harmonic mixer in the main phase-locked loop outputs frequency f _if＝f_out-Nf_iac, wherein N is the harmonic frequency of an input mixing signal f _iac in the mixer. In the traditional decimal phase-locked loop, the transfer function isWhere H _ff is the loop open loop transfer function and Na is the fractional division ratio of the fractional phase locked loop. Therefore the number of transfer loops of the DSM, such as quantization noise, through the loop has a Na-fold gain. The fractional divider in the fractional phase-locked loop of the harmonic mixer is replaced by the harmonic mixer, the fractional division ratio does not exist in the loop, and the transfer function of the loop of the phase-locked loop is/>Therefore, the quantization noise of DSM can be well suppressed.

In the circuit structure, under the condition of adopting a DTC circuit, based on a technology of 16nm of station accumulation electricity, 60MHz crystal oscillation in a chip is used as a reference, the output frequency is in the range of 7 GHz-9 GHz, and under the condition of locking to 7.7GHz frequency, when noise is integrated in the range of 10 KHz-10 MHz, the decimal phase-locked loop realizes 131fsrms dithering. The worst fractional phase-locked loop reference spurious for this architecture is-66 dBc. The power supply of the fractional phase-locked loop is 0.9V, and the power consumption of the fractional phase-locked loop cascaded by the frequency divider is 1.9mW; the power consumption of the integer phase-locked loop is 2.8mW; the frequency divider cascaded with the integer phase-locked loop has high input frequency, long wiring, high power consumption of 2.1mW and 6.6mW consumption of the main loop phase-locked loop, so that the total power consumption of the whole three-loop phase-locked loop circuit is 13.4mW, and the FOM of the whole circuit is-246.4 dB. Performance is at a worldwide advanced level.

DIHANG YANG et al replaced the divider in the main loop with a harmonic mixer so that the loop transfer function was successful as a unity transfer function. This strongly suppresses quantization noise from the DSM, and allows the fractional phase locked loop to achieve high phase noise performance and low spurious performance without the use of DTC circuitry and calibration circuitry. But there are three phase-locked loops in the circuit, which increases the power consumption and complexity of the circuit. And the output frequency range of the loop is only 2GHz, so that the loop has a certain limitation in the application field.

On the other hand, modern very large scale data centers and channel infrastructure both require high speed SerDes and speeds as low as a few Gb/s to support many standard and legacy channels, and in order to support all data rates between the two, the university of Zhejiang, xiang Gao et al, in 2022 TCAS II, proposed a 0.73-15.5GHz LC_VCO-based high performance phase-locked loop circuit with an ultra wide output frequency range. It was analyzed in this paper that octave frequency tuning range VCO (voltage controlled oscillator) constitutes a major design challenge for fractional phase locked loops with a wide output frequency range. Ring oscillators can provide a very wide frequency tuning range and have the advantage of a small area. But its new energy difference in phase noise limits the use of the VCO in high-speed interface circuits. LC VCOs provide excellent phase noise performance, but the output frequency adjustment range of such a VCO is very limited, so that a wide frequency output requirement is usually achieved by using a plurality of LC VCOs in the same phase-locked loop to meet the wide output frequency range requirement, but this results in a large area and waste of power consumption.

This article proposes a compact and flexible single LC VCO and a fractional phase locked loop with a wide output frequency range. It can generate 0.73-15GHz clock, and can seamlessly support any data rate between 1Gb/s NRZ and 58 Gb/sPAM-4. It implements a 50% duty cycle and divide by 1.5 divider based on a duty cycle interpolator. The specific architecture is shown in fig. 2 below. The circuit mainly comprises a decimal phase-locked loop, a 1.5-time frequency divider (Div-1.5) with 50% duty ratio and a 1/2/4/8 frequency divider, and a duty ratio corrector circuit (DCC) is added in the circuit for meeting the output condition of the 56Gb/s PAM-4 transmitter. In the circuit, the DSM (derta _sigma modulator) controls the MMD (multi-mode frequency divider) to carry out fractional frequency division, DDiv-1.5 (digital 1.5 times frequency divider) generates two 1.5 times frequency division clocks, the duty ratio is respectively 60% and 30%, and the DI (duty ratio modulator) outputs a signal with the duty ratio of 50%. Finally, the frequency coverage range of the output frequency after frequency division for 2, 4 and 8 times is 0.73GHz to 15GHz clock.

Note that in this circuit configuration, a wide frequency coverage is achieved by one high-bandwidth LC VCO plus a digital 1.5 divider. Wherein the high-bandwidth LC VCO output frequency range is 10GHz-15GHz, so that the output frequency range through DDiv-1.5 is 7.5GHz-10GHz. The output frequency range can cover the octave band and 1/2 of the highest frequency, so that the frequency range can be covered after being divided by 2,4 and 8.

The circuit is based on a silicon-based 12nm technology, and the active area is 0.17mm < 2 >. At 13.2815GHz output frequency, it realizes integration jitter of 101fs and reference spurious of-74.79 dBc, while the power consumption is 19.5mW, and the worst deterministic jitter of the test is 550fs.

The fractional phase-locked loop of the Xiang Gao team replaces the use of multiple LC VCOs in most schemes with a digital phase-locked loop plus DDiv-1.5 to achieve ultra-large frequency range output. Such architecture has the advantage of greatly reducing chip area and power consumption, and also has great advantages in terms of design complexity. But nothing specifically suppresses DSM quantization noise in the architecture throughout the architecture. Therefore, the phase noise performance of the fractional phase locked loop is not satisfactory.

In summary, the existing phase-locked loop circuit has higher power consumption and complexity, and has certain limitation in application field due to smaller loop output frequency, and higher phase noise, which results in lower reliability and stability of the existing phase-locked loop circuit. In order to solve the above-mentioned problems, an embodiment of the present invention provides an ultra-wideband phase-locked loop circuit, which mainly uses a multi-harmonic mixer loop to replace a conventional frequency divider loop to expand the output frequency range while suppressing DSM quantization noise, and specifically includes:

As shown in fig. 3, an embodiment of the present invention provides an ultra wideband phase locked loop circuit, which includes a differential integral modulator DSM, a multi-mode frequency divider MMD, a phase detector PD, a gain GM, a low pass filter LPF and a ring voltage controlled oscillator RingVCO that are sequentially connected, wherein an input end of the differential integral modulator DSM is connected with an input end of the phase detector PD; the circuit further comprises: a prescaler PDIV connected to the input end of the multimode divider MMD, and a multiple harmonic mixer HM having one end connected to the prescaler PDIV and one end connected to the ring voltage-controlled oscillator RingVCO, the output end of the multiple harmonic mixer HM being connected to the phase detector PD, and the input end of the multiple harmonic mixer HM being connected to the output end of the ring voltage-controlled oscillator RingVCO;

The differential integral modulator DSM and the multi-mode frequency divider MMD are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal;

the prescaler PDIV is used for dividing an input signal into a fundamental frequency signal for later mixing;

The multi-harmonic mixer HM is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal;

the phase detector PD is configured to identify a phase difference between the mixed output signal and the fractional frequency signal;

The gain GM and the low pass filter LPF are configured to convert the phase difference into a voltage signal that controls an output of the ring voltage controlled oscillator;

The ring voltage controlled oscillator RingVCO is configured to control the frequency of the output signal based on the voltage signal, and obtain an output frequency signal after the loop is locked.

Under the condition of adopting the technical scheme, the ultra-wideband phase-locked loop circuit provided by the invention comprises a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain, a low-pass filter and a ring voltage-controlled oscillator which are sequentially connected, wherein the input end of the differential integral modulator is connected with the input end of the phase discriminator; the circuit further comprises: the input end of the multi-harmonic mixer is connected with the output end of the annular voltage-controlled oscillator; the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal; the prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing; the multi-harmonic mixer is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal; the phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal; the gain device and the low-pass filter are used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator; the ring voltage controlled oscillator is used for controlling the frequency of an output signal based on the voltage signal, obtaining the output frequency signal after the loop is locked, and replacing the traditional frequency divider loop with a multi-harmonic mixer loop to expand the output frequency range while restraining the quantization noise of the differential integral modulator, so that the application field is expanded, and the reliability and the stability of the phase-locked loop circuit can be improved.

It is understood that the multi-mode frequency divider is composed of multi-stage cascaded frequency dividers, and the frequency division ratio corresponding to each stage of frequency divider is 2 or 3.

In the present invention, the multi-modulus divider may be formed of a multi-stage cascade of 2,3 dividers, each of which may be controlled to have a division ratio of 2 or 3. The input is f _in frequency signals, the Nbit controls the frequency division output of the frequency divider, and the output end is output frequency division signals f _div.

Optionally, the differential integral modulator and the multi-modulus frequency divider are configured to form a fractional frequency division, and perform fractional frequency division processing on an input signal to obtain a fractional frequency division signal, including:

the differential integral modulator is used for determining a fractional frequency division ratio based on a frequency control signal and an average value of frequency division control in a certain time;

The differential integral modulator is used for controlling the multi-mode frequency divider to carry out frequency division processing based on the fractional frequency division ratio and outputting a fractional frequency division signal by the multi-mode frequency divider.

Optionally, the differential integral modulator is configured to determine a fractional division ratio based on the frequency control signal and an average value of the control division over a certain time, and includes:

The differential integral modulator is used for performing decimal control frequency division signals by adopting a digital circuit mode and inputting decimal part Frequency Control Words (FCWF) into Nx bit numbers to control decimal And the integer part Frequency Control Word (FCWI) is an N bit digital signal, and outputs a frequency division control signal of N bit of the Frequency Control Word (FCW) added with decimal components;

The differential integral modulator is configured to determine the Frequency Control Word (FCW) signal and an average value of the control frequency division over a time period as the fractional division ratio Na.

Optionally, the prescaler is configured to divide an input signal into a baseband signal for post-mixing, and includes:

the prescaler is used for prescaler processing the input signal to obtain the fundamental frequency signal serving as the harmonic mixer.

Specifically, the prescaler mainly divides the frequency signal of the input f _in by a frequency to be used as the fundamental frequency signal of the harmonic mixer, and the output frequency is f _sh.

Optionally, the multiple harmonic mixer is configured to mix the fundamental frequency signal with an output signal of the ring voltage-controlled oscillator according to a requirement, and extract to obtain a mixed output signal, where the mixing process includes:

The multi-harmonic mixer is used for convolving the fundamental frequency signal with the output signal of the annular voltage-controlled oscillator and filtering out the mixed output signal through the low-pass filter.

Optionally, the multiple harmonic mixer is configured to convolve the baseband signal with an output signal of the ring voltage controlled oscillator, and filter the mixed output signal through the low-pass filter, and includes:

The multi-harmonic mixer is configured to convolve the fundamental frequency signal with an output signal of the ring voltage-controlled oscillator, and set an upper limit cut-off frequency of a low-pass filter in the harmonic mixer to a preset frequency within a preset frequency range, so as to obtain the mixed output signal corresponding to a target mixed output signal frequency.

Specifically, the multiple harmonic mixer uses the fundamental frequency signal obtained by the output of the frequency divider to be convolved with the RingVCO output signal, and the output signal of the mixer is filtered out by a low-pass filter. The output signal frequency is f _hm, the frequency divider output fundamental frequency signal frequency is f _hs, and the RingVCO output signal frequency is f _vco. If the upper limit cutoff frequency of the low-pass filter in the harmonic mixer is set to about 1GHz (gigahertz), the desired mixed output signal frequency f _hm can be obtained. And f _hm＝f_vco-Nf_sh is obtained by a simple fourier transform. Where N is taken as N1, N2, N3 …, the frequency coverage can be seen approximately by the following fig. 4.

Alternatively, there are many kinds of phase detectors, such as those commonly constructed by a D flip-flop and a nand gate, and the phase difference is derived by comparing the rising edges of the two signals. The phase detector of the sampler mode adopted in the circuit is also provided, and if the sampling positions are the same every time, the phase is not changed any more. The sampler circuit can be used as a phase discriminator, not only can be used for same-frequency phase discrimination, but also can be used as a sub-sampling phase discriminator, namely, the frequency of a sampling signal is an integer multiple of the frequency of a sampled signal.

Optionally, the gain unit and the low-pass filter are configured to convert the phase difference into a voltage signal for controlling the output of the ring voltage-controlled oscillator, and include:

The gain device is used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator;

The low-pass filter is used for filtering the voltage signal and outputting the filtered voltage signal.

Optionally, a second-order low-pass filter is used in the fractional phase-locked loop to filter the ac signals transmitted from the preceding stage circuit, and these ac signals affect the spurious output signals to a large extent. The filtered signal Vc is used to control the VCO (voltage controlled oscillator) output. If the Vc signal is not changed, the decimal phase-locked loop is locked, and a stable fixed frequency signal is output.

Optionally, the ring voltage controlled oscillator is a loop formed by a pseudo-differential inverter architecture of a three-division cascade, and the control supply voltage and the access capacitor are adopted to control the output frequency and control the voltage variation to cause the voltage controlled oscillator output frequency to vary.

Optionally, the control voltage change causes a slope of the voltage controlled oscillator output frequency change

Wherein Δf _vco represents the voltage controlled oscillator output frequency variation value; deltaV _c represents the control voltage difference.

There are many types of voltage controlled oscillators, which can be classified into RingVCO (no inductance) and LC VCO (inductive) according to whether or not an inductance is used in the circuit. The LC VCO adopts the inductance and capacitance resonant cavities to generate the oscillation frequency, and the circuit can realize higher output frequency under the same process condition and has higher phase noise performance. However, the output frequency range of the LC VCO is limited, it is difficult to achieve 1/2 of the highest frequency required in the architecture, and the area of the circuit is much larger than RingVCO circuit area due to the inductance factor used in the circuit. From the above analysis, it can be seen that in order to achieve the architecture output wide frequency range, only the form of a ring voltage controlled oscillator can be used. The voltage-controlled oscillator adopted in the circuit is a ring oscillator loop formed by three cascaded pseudo-differential inverter architectures, and meanwhile, the output frequency and K _VCO are controlled by controlling the power supply voltage and the access capacitor. The ultra-wide output frequency range required in the loop is achieved with K _VCO required by the fractional phase locked loop. Where K _VCO is the slope of the change in control voltage VC resulting in the change in output frequency of the VCO, i.e

FIG. 5 shows a schematic diagram of a ultra wideband PLL circuit corresponding to frequency mixing by N1 harmonic, in which, as shown in FIG. 5, when the output frequency is f _vco1, the input frequency f _in1 is the same time, so that the fundamental frequency signal frequency for frequency mixing is generated after passing through the pre-N frequency dividerAs shown in FIG. 5, the circuit sets a fractional division ratio N.a1, and the DSM is input as N _x bit input in the framework, so that DSM fractional/>Integer input FCWI = N. Thus, a fractional frequency signal can be obtained, the frequency/>, of the signalIf the loop is locked, the output frequency f _VCO1 is thus the output frequency f _hm1＝f_VCO1-N1*f_sh1 after the sum fundamental frequency f _sh signal passes through the multiple harmonic mixer. The frequency of the output signal of the mixer is equal to that of the output signal of the fractional frequency divider, so that the output of the phase discriminator is a fixed value, the control voltage signal is not changed after passing through the GM and the LPF, the whole fractional phase-locked loop is locked, the transfer function of the loop is a unit transfer function, the effect of inhibiting DSM quantization noise can be achieved, and the phase noise of the whole phase-locked loop is greatly improved.

FIG. 6 shows a schematic diagram of a ultra wideband PLL circuit corresponding to frequency mixing by N2 harmonics according to an embodiment of the present invention, where the input frequency f _in2 is the output frequency f _vco2 as shown in FIG. 6, so that the fundamental frequency signal frequency for frequency mixing is generated after passing through the pre-N frequency dividerAs shown in FIG. 6, the circuit sets a fractional division ratio N.a2, and the DSM is input as N _x bit in the architecture, so that DSM fractional/>Integer input FCWI = N. Thus, a fractional frequency signal can be obtained, the frequency/>, of the signalIf the loop is locked, the output frequency f _VCO2 is thus the output frequency f _hm2＝f_VCO2-N2*f_sh2 after the sum fundamental frequency f _sh signal passes through the multiple harmonic mixer. The frequency of the output signal of the mixer is equal to that of the output signal of the fractional frequency divider, so that the output of the phase discriminator is a fixed value, the control voltage signal is not changed after passing through the GM and the LPF, the whole fractional phase-locked loop is locked, the transfer function of the loop is a unit transfer function, the effect of inhibiting DSM quantization noise can be achieved, and the phase noise of the whole phase-locked loop is greatly improved.

FIG. 7 is a schematic diagram of a scenario of an ultra-wideband PLL circuit employing N3 harmonic mixing according to an embodiment of the present invention, where the input frequency f _in3 is f _vco3 when the output frequency is f _vco3, so that the fundamental frequency signal frequency for mixing is generated after passing through a pre-N frequency dividerAs shown in the above figure, the circuit sets the fractional division ratio n.a3 at this time, and the DSM is input as N _x bit input in the architecture, so the DSM fraction/>Integer input FCWI = N. Thus, a fractional frequency signal can be obtained, the frequency/>, of the signalIf the loop is locked, the output frequency f _VCO3 is thus the output frequency f _hm3＝f_VCO3-N3*f_sh3 after the sum fundamental frequency f _sh signal passes through the multiple harmonic mixer. The frequency of the output signal of the mixer is equal to that of the output signal of the fractional frequency divider, so that the output of the phase discriminator is a fixed value, the control voltage signal is not changed after passing through the GM and the LPF, the whole fractional phase-locked loop is locked, the transfer function of the loop is a unit transfer function, the effect of inhibiting DSM quantization noise can be achieved, and the phase noise of the whole phase-locked loop is greatly improved.

FIG. 8 shows a schematic diagram of a ultra wideband PLL circuit corresponding to frequency mixing by N4 harmonic, as shown in FIG. 8, in which the input frequency f _in4 is the output frequency f _vco4, so that the fundamental frequency signal frequency for frequency mixing is generated after passing through the pre-N frequency dividerAs shown in the above figure, the circuit sets the fractional division ratio n.a4 at this time, and the DSM is input as N _x bit input in the architecture, so the DSM fraction/>Integer input FCWI = N. Thus, a fractional frequency signal can be obtained, the frequency/>, of the signalIf the loop is locked, the output frequency f _VCO4 is thus the output frequency f _hm4＝f_VCO4-N4*f_sh4 after the sum fundamental frequency f _sh4 signal passes through the multiple harmonic mixer. The frequency of the output signal of the mixer is equal to that of the output signal of the fractional frequency divider, so that the output of the phase discriminator is a fixed value, the control voltage signal is not changed after passing through the GM and the LPF, the whole fractional phase-locked loop is locked, the transfer function of the loop is a unit transfer function, the effect of inhibiting DSM quantization noise can be achieved, and the phase noise of the whole phase-locked loop is greatly improved.

It is noted that multiple harmonic mixing can be implemented in the same circuit by controlling the input parameters in the circuit, such as integer divide ratio FCWI, fractional divide ratio FCWF, and the number of added cap banks in the input frequency f _in and RingVCO circuits, thereby implementing an ultra-wide output frequency range fractional phase-locked loop.

Through the detailed description of the four harmonic frequencies, it can be seen that the architecture can not only utilize the multiple harmonic mixer to suppress the serious quantization noise caused by the DSM in the loop, but also use the multiple harmonic mixer and RingVCO of the ultra-wide output frequency range to greatly increase the output frequency range of the whole decimal phase-locked loop, so that the output frequency range covers 1/2 of the highest frequency. Finally, the 2,4,8 frequency dividers are used for realizing the coverage of the full frequency band, and the design of the decimal phase-locked loop with high performance, low phase noise and ultra-wide output frequency range is realized.

The phase-locked loop adopting the multiple harmonic mixing technology is provided with multiple harmonic mixing technology, so that multiple mixing modes are realized. The purposes of realizing and meeting the mixing requirement of ultra-wideband output frequency and suppressing DSM quantization noise in a circuit are achieved.

The patent proposes a new fractional phase-locked loop circuit architecture for outputting clocks in ultra-wide frequency range and having high phase noise performance. The circuit adopts a multi-harmonic mixing technology, so that the output frequency range of the decimal phase-locked loop can be expanded, and the transfer function of the loop is changed into a unit transfer function to inhibit quantization noise of DSM in the loop. Thus, the design complexity problem of the decimal phase-locked loop caused by the DTC circuit and the calibration circuit is avoided, and the problem that the decimal phase-locked loop has limited output frequency range and insufficient phase noise performance of the decimal phase-locked loop is solved.

Under the condition of adopting the technical scheme, the ultra-wideband phase-locked loop circuit provided by the invention comprises a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain, a low-pass filter and a ring voltage-controlled oscillator which are sequentially connected, wherein the input end of the differential integral modulator is connected with the input end of the phase discriminator; the circuit further comprises: the input end of the multi-harmonic mixer is connected with the output end of the annular voltage-controlled oscillator; the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal; the prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing; the multi-harmonic mixer is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal; the phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal; the gain device and the low-pass filter are used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator; the ring voltage controlled oscillator is used for controlling the frequency of an output signal based on the voltage signal, obtaining the output frequency signal after the loop is locked, and replacing the traditional frequency divider loop with a multi-harmonic mixer loop to expand the output frequency range while restraining the quantization noise of the differential integral modulator, so that the application field is expanded, and the reliability and the stability of the phase-locked loop circuit can be improved.

Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. The ultra-wideband phase-locked loop circuit is characterized by comprising a differential integral modulator, a multi-mode frequency divider, a phase discriminator, a gain device, a low-pass filter and a ring voltage-controlled oscillator which are sequentially connected, wherein the input end of the differential integral modulator is connected with the input end of the phase discriminator; the circuit further comprises: the input end of the multi-harmonic mixer is connected with the output end of the annular voltage-controlled oscillator;

the differential integral modulator and the multi-mode frequency divider are used for forming fractional frequency division, and fractional frequency division processing is carried out on an input signal to obtain a fractional frequency division signal;

The prescaler is used for dividing the input signal into a fundamental frequency signal for later mixing;

the multi-harmonic mixer is used for carrying out mixing processing on the fundamental frequency signal and the output signal of the annular voltage-controlled oscillator according to requirements, and extracting to obtain a mixed output signal;

The phase discriminator is used for discriminating the phase difference between the mixed output signal and the fractional frequency division signal;

The gain device and the low-pass filter are used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator;

The annular voltage-controlled oscillator is used for controlling the frequency of the output signal based on the voltage signal, and obtaining an output frequency signal after the loop is locked.

2. The ultra-wideband phase-locked loop circuit of claim 1, wherein the multi-modulus divider is comprised of a multi-stage cascade of dividers, each stage having a division ratio of 2 or 3.

3. The ultra-wideband phase-locked loop circuit of claim 1, wherein the differential integral modulator and the multi-modulus divider are configured to divide the input signal by a fractional division process to obtain a fractional-divided signal, comprising:

the differential integral modulator is used for determining a fractional frequency division ratio based on a frequency control signal and an average value of frequency division control in a certain time;

The differential integral modulator is used for controlling the multi-mode frequency divider to carry out frequency division processing based on the fractional frequency division ratio and outputting a fractional frequency division signal by the multi-mode frequency divider.

4. The ultra-wideband phase-locked loop circuit of claim 1, wherein the prescaler is configured to divide an input signal into a baseband signal for post-mixing, comprising:

the prescaler is used for prescaler processing the input signal to obtain the fundamental frequency signal serving as the harmonic mixer.

5. The ultra-wideband phase-locked loop circuit of claim 1, wherein the multi-harmonic mixer is configured to mix the fundamental frequency signal with the output signal of the ring voltage-controlled oscillator according to requirements, and extract a mixed output signal, and comprises:

The multi-harmonic mixer is used for convolving the fundamental frequency signal with the output signal of the annular voltage-controlled oscillator and filtering out the mixed output signal through the low-pass filter.

6. The ultra-wideband phase-locked loop circuit of claim 1, wherein the gain and low pass filter are configured to convert the phase difference to a voltage signal that controls the output of the ring voltage-controlled oscillator, comprising:

The gain device is used for converting the phase difference into a voltage signal for controlling the output of the annular voltage-controlled oscillator;

The low-pass filter is used for filtering the voltage signal and outputting the filtered voltage signal.

7. The ultra wideband phase locked loop circuit of claim 1, wherein the ring voltage controlled oscillator is a loop formed by a pseudo-differential inverter architecture in a three-division cascade, and wherein controlling the output frequency and controlling the voltage variation using the control supply voltage and the access capacitance results in a voltage controlled oscillator output frequency variation.

8. The ultra-wideband phase-locked loop circuit of claim 7, wherein the control voltage variation causes a slope of a voltage-controlled oscillator output frequency variation

Wherein Δf _vco represents the voltage controlled oscillator output frequency variation value; deltaV _c represents the control voltage difference.

9. The ultra-wideband phase-locked loop circuit of claim 3, wherein the differential integral modulator is configured to determine a fractional division ratio based on the frequency control signal and an average value of the control division over time, comprising:

The differential integral modulator is used for performing decimal control frequency division signals by adopting a digital circuit mode and inputting decimal part frequency control words into Nx bit numbers to control decimal And the integer part frequency control word is an N bit digital signal, and outputs a frequency division control signal of a frequency control word Nbit added with decimal components;

the differential integral modulator is used for determining the average value of the frequency control word signal and the frequency division control in a certain time as the fractional frequency division ratio Na.

10. The ultra wideband phase locked loop circuit of claim 5, wherein the multiple harmonic mixer is configured to convolve the baseband signal with the output signal of the ring voltage controlled oscillator and filter out the mixed output signal via the low pass filter, comprising:

The multi-harmonic mixer is configured to convolve the fundamental frequency signal with an output signal of the ring voltage-controlled oscillator, and set an upper limit cut-off frequency of a low-pass filter in the harmonic mixer to a preset frequency within a preset frequency range, so as to obtain the mixed output signal corresponding to a target mixed output signal frequency.