CN118039608A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN118039608A CN118039608A CN202211369587.4A CN202211369587A CN118039608A CN 118039608 A CN118039608 A CN 118039608A CN 202211369587 A CN202211369587 A CN 202211369587A CN 118039608 A CN118039608 A CN 118039608A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 254
- 238000012360 testing method Methods 0.000 claims abstract description 195
- 229910052751 metal Inorganic materials 0.000 claims abstract description 123
- 239000002184 metal Substances 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000011241 protective layer Substances 0.000 claims abstract description 40
- 238000002161 passivation Methods 0.000 claims abstract description 35
- 238000003466 welding Methods 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims description 30
- 238000011049 filling Methods 0.000 claims description 17
- 239000007769 metal material Substances 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
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- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 28
- 238000004891 communication Methods 0.000 abstract description 12
- 235000012431 wafers Nutrition 0.000 description 41
- 230000008569 process Effects 0.000 description 27
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
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- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
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Abstract
The application provides a semiconductor structure and a forming method thereof, wherein the structure comprises: the test device comprises a substrate, a test welding pad, a metal layer and a protective layer, wherein the test welding pad and the metal layer are formed on the surface of the substrate, and the protective layer is positioned on the surfaces of the test welding pad and the metal layer; the first dielectric layer, the passivation layer and the second dielectric layer are sequentially positioned on the surface of the substrate and the surface of the protective layer; and the metal connecting structure penetrates through the second dielectric layer, the passivation layer, the first dielectric layer and the protection layer and is respectively and electrically connected with the extension part of the test welding pad and the metal layer. The application provides a semiconductor structure and a forming method thereof, which are used for distinguishing the position for manufacturing a test opening from the position for manufacturing a metal connecting structure, so that the test opening can not influence the manufacturing of the metal connecting structure any more, wafer bonding or communication failure can be avoided, and the reliability of a device is improved.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Three-dimensional electronic packaging technology (3 DIC) is achieved by vertically stacking two or more layers of chips together. The technology can organically integrate different functions of the stacked chips together, and further improves the functions of the chips. Currently, advanced three-dimensional packaging is developing towards the technical direction of wafer-wafer hybrid bonding, and compared with chip-wafer and chip-chip bonding, wafer-wafer bonding has the advantages of higher yield, easier performance improvement and the like. Wafer-to-wafer bonding often places higher demands on the individual wafers to ensure bond power. These requirements include wafer warpage, surface flatness, defect count, and the like. One of the most important is the surface flatness before bonding the wafer and the fabrication of the metal connection structure required for bonding.
In order to meet the requirement of bonding technology on wafers at present, some manufacturers require that wafers to be bonded are not tested such as yield test and electrical test before leaving the factory, and only a plurality of wafers are extracted from the same batch of wafers to be tested, and the wafers are extracted and are not bonded. And preparing a bonded wafer, after patterning the top metal layer, performing passivation film coating and planarization process, and then manufacturing a metal connection structure for bonding. However, this method has a risk that it is impossible to confirm whether each chip functions normally before bonding, the bonding thinning process is complicated, and once the whole function is tested after the bonding, thinning and backside processes are completed, it is sometimes difficult to confirm whether the bonding process is problematic or the chip itself is problematic. Therefore, it is necessary to perform tests such as yield test and electrical test on each chip of the wafer before bonding.
However, the test opening is required to be opened for testing the wafer, and the position of opening the test opening after the test is completed greatly increases the manufacturing difficulty of the metal connection structure for bonding, and the wafer bonding or communication failure is easy to cause. Therefore, it is necessary to provide a more reliable and efficient technical solution, to avoid wafer bonding or communication failure, and to improve device reliability.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, which can avoid wafer bonding or communication failure and improve device reliability.
One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a substrate; forming a test welding pad, a metal layer and a protective layer on the surfaces of the test welding pad and the metal layer on the surface of the substrate, wherein the test welding pad comprises a main body part and an extension part; sequentially forming a first dielectric layer, a passivation layer and a second dielectric layer on the surface of the substrate and the surface of the protective layer; and forming a metal connection structure penetrating through the second dielectric layer, the passivation layer, the first dielectric layer and the protective layer and respectively and electrically connecting the extension part of the test welding pad and the metal layer in the protective layer, the first dielectric layer, the passivation layer and the second dielectric layer.
In some embodiments of the present application, the extension portion of the test pad is a strip structure, and the metal connection structure electrically connected to the extension portion of the test pad is arranged in a linear manner at the extension portion of the test pad.
In some embodiments of the present application, the extension portion of the test pad includes a block structure, and the metal connection structure electrically connecting the extension portion of the test pad is arranged in a matrix at the extension portion of the test pad.
In some embodiments of the present application, the method for forming a semiconductor structure further includes: forming a test opening exposing the main body part of the test welding pad in the protective layer, the first dielectric layer, the passivation layer and the second dielectric layer; performing an electrical test on the device in the substrate through the main body portion of the test pad; and forming a filling layer filling the test opening in the test opening.
In some embodiments of the present application, a method for forming a test pad and a metal layer and a protective layer on the surface of the test pad and the metal layer includes: sequentially forming a metal material layer and a protective material layer on the surface of the substrate; and etching the metal material layer and the protective material layer to form the test welding pad, the metal layer and the protective layer.
In some embodiments of the present application, the substrate includes a wafer and an interlayer dielectric layer on a surface of the wafer.
Another aspect of the present application also provides a semiconductor structure, comprising: the test device comprises a substrate, a test welding pad, a metal layer and a protective layer, wherein the test welding pad and the metal layer are formed on the surface of the substrate, and the protective layer is positioned on the surfaces of the test welding pad and the metal layer; the first dielectric layer, the passivation layer and the second dielectric layer are sequentially positioned on the surface of the substrate and the surface of the protective layer; and the metal connecting structure penetrates through the second dielectric layer, the passivation layer, the first dielectric layer and the protection layer and is respectively and electrically connected with the extension part of the test welding pad and the metal layer.
In some embodiments of the present application, the extension portion of the test pad is a strip structure, and the metal connection structure electrically connected to the extension portion of the test pad is arranged in a linear manner at the extension portion of the test pad.
In some embodiments of the present application, the extension portion of the test pad includes a block structure, and the metal connection structure electrically connecting the extension portion of the test pad is arranged in a matrix at the extension portion of the test pad.
In some embodiments of the present application, the semiconductor structure further comprises: and the filling layer penetrates through the second dielectric layer, the passivation layer, the first dielectric layer and the protection layer and is connected with the main body part of the test welding pad.
In some embodiments of the present application, the substrate includes a wafer and an interlayer dielectric layer on a surface of the wafer.
The application provides a semiconductor structure and a forming method thereof, which are used for distinguishing the position for manufacturing a test opening from the position for manufacturing a metal connecting structure, so that the test opening can not influence the manufacturing of the metal connecting structure any more, wafer bonding or communication failure can be avoided, and the reliability of a device is improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale. Wherein:
FIGS. 1-4 are schematic diagrams illustrating steps in a method for forming a semiconductor structure;
Fig. 5 to 13 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the invention is described in detail below with reference to the examples and the accompanying drawings.
Fig. 1-4 are schematic structural diagrams illustrating steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, and a test pad 110 and a metal layer 120 and a protective layer 130 on the surface of the test pad 110 and the metal layer 120 are formed on the surface of the substrate 100. The surface of the substrate 100 is further formed with a first dielectric layer 140 covering the substrate 100, the test pad 110, the metal layer 120 and the protective layer 130. The passivation layer 150 and the second dielectric layer 160 are sequentially formed on the surface of the first dielectric layer 140.
Referring to fig. 2, a test opening 170 penetrating the second dielectric layer 160, the passivation layer 150, the first dielectric layer 140, and the protective layer 130 and exposing the test pad 110 is formed in the protective layer 130, the first dielectric layer 140, the passivation layer 150, and the second dielectric layer 160. The substrate 100 is tested, such as yield test or electrical test, by connecting the test pads 110 through the test openings 170 using test probes.
Referring to fig. 3, a filling layer 180 filling the test opening 170 is formed in the test opening 170.
Referring to fig. 4, a metal connection structure 190 electrically connecting the test pad 110 and the metal layer 120 is formed in the filling layer 180 and the protective layer 130, the first dielectric layer 140, the passivation layer 150, and the second dielectric layer 160, respectively.
However, in some of the above-described methods of forming semiconductor structures, since there is a coincidence between the position of fabricating the test opening 170 and the position of fabricating the metal connection structure 190, there are the following drawbacks. On the one hand, the materials of the test pad 110 and the metal layer 120 are generally metal materials such as aluminum or copper, in order to prevent oxidation of metal, a protective layer 130 with a certain thickness is deposited on the surfaces of the test pad 110 and the metal layer 120, and the test opening 170 penetrates through the protective layer 130 to expose the test pad 110, so that the test pad 110 is easily oxidized, which leads to an increase in contact resistance and even failure of communication between the subsequently formed metal connection structure 190 and the test pad 110; on the other hand, after the filling layer 180 is used to fill the test opening 170, a single film layer is disposed above the test pad 110 (the material of the filling layer 180 is typically silicon oxide), but a quadruple structure (typically a four-layer combined film layer of titanium nitride-silicon oxide-silicon nitride-silicon oxide) of the protection layer 120, the first dielectric layer 140, the passivation layer 150 and the second dielectric layer 160 is disposed above the metal layer 120, which results in a relatively high process difficulty when the metal connection structure 190 is fabricated above the test pad 110 and the metal layer 120, which results in a very small process window and greatly limits the yield and the product bonding performance.
In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, which are capable of distinguishing the position of manufacturing a test opening from the position of manufacturing a metal connection structure, so that the test opening can not affect the manufacture of the metal connection structure any more, wafer bonding or communication failure can be avoided, and device reliability is improved.
Fig. 5 to 13 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the application. The method for forming the semiconductor structure according to the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 5, a substrate 200 is provided.
In some embodiments of the present application, the substrate 200 includes a wafer 201 and an interlayer dielectric layer 202 on a surface of the wafer 201. The wafer 201 comprises a semiconductor wafer, such as a silicon wafer. The wafer 201 according to the embodiment of the present application may include any chip, such as a logic chip, a memory chip, an analog circuit chip, a microcontroller, etc.
In some embodiments of the present application, a metal wiring layer (not shown) is formed in the interlayer dielectric layer 202, and the metal wiring layer is used to electrically connect active devices in the wafer 201.
In some embodiments of the present application, the material of the interlayer dielectric layer 202 is, for example, silicon oxide. The method for forming the interlayer dielectric layer 202 includes a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 6 to 9, a test pad 210 and a metal layer 220 and a protective layer 230 on the surfaces of the test pad 210 and the metal layer 220 are formed on the surface of the substrate 200, and the test pad 210 includes a body portion 211 and an extension portion 212.
Referring to fig. 6, a metal material layer 210a and a protective material layer 230a are sequentially formed on the surface of the substrate 200.
In some embodiments of the present application, the material of the metal material layer 210a is, for example, a metal material such as aluminum or copper. The method of forming the metal material layer 210a includes a chemical vapor deposition process, a physical vapor deposition process, or the like.
In some embodiments of the present application, the material of the protective material layer 230a is, for example, titanium nitride or the like. The method of forming the protective material layer 230a includes a chemical vapor deposition process, a physical vapor deposition process, or the like.
Referring to fig. 7, the metal material layer 210a and the protective material layer 230a are etched to form the test pad 210, the metal layer 220, and the protective layer 230. The test pad 210 includes a main body 211 and an extension 212.
In some embodiments of the present application, the method of etching the metal material layer 210a and the protective material layer 230a to form the test pad 210, the metal layer 220, and the protective layer 230 includes: forming a patterned photoresist layer on the surface of the protective material layer 230a, wherein the patterned photoresist layer defines the positions of the test pad 210 and the metal layer 220; and etching the protective material layer 230a and the metal material layer 210a by using the patterned photoresist layer as a mask to form the test pad 210, the metal layer 220 and the protective layer 230.
The test pad 210 and the metal layer 220 are electrically connected to a metal wiring layer in the interlayer dielectric layer 202.
The protection layer 230 is used to protect the test pad 210 and the metal layer 220 from oxidation.
Fig. 8 is a top view of the substrate 200, the test pads 210, and the metal layer 220 in some embodiments of the semiconductor structure shown in fig. 7.
Referring to fig. 8, the test pad 210 and the metal layer 220 are formed on the surface of the interlayer dielectric layer 202. The test pad 210 includes a main body portion 211 and an extension portion 212. The main body 211 of the test pad 210 is used for performing wafer testing, and the extension 212 of the test pad 210 is used for connecting with a metal connection structure, that is, a metal connection structure for electrically connecting with the test pad 210 is formed above the extension 212.
In some embodiments of the present application, for example, as shown in fig. 8, the extension 212 of the test pad 210 has a strip structure, and the metal connection structure electrically connected to the extension 212 of the test pad 210 is arranged in a linear manner at the extension 212 of the test pad 210.
Fig. 9 is a top view of the substrate 200, the test pads 210, and the metal layer 220 in other embodiments of the semiconductor structure shown in fig. 7.
Referring to fig. 9, the test pad 210 and the metal layer 220 are formed on the surface of the interlayer dielectric layer 202. The test pad 210 includes a main body portion 211 and an extension portion 212. The main body 211 of the test pad 210 is used for performing wafer testing, and the extension 212 of the test pad 210 is used for connecting with a metal connection structure, that is, a metal connection structure for electrically connecting with the test pad 210 is formed above the extension 212.
In other embodiments of the present application, referring to fig. 9, the extension 212 of the test pad 210 includes a block structure, and the metal connection structure electrically connected to the extension 212 of the test pad 210 is arranged in a matrix at the extension 212 of the test pad 210. Such an arrangement may increase the distribution density of the metal connection structure.
Referring to fig. 10, a first dielectric layer 240, a passivation layer 250, and a second dielectric layer 260 are sequentially formed on the surface of the substrate 200 and the surface of the protective layer 230.
In some embodiments of the present application, the material of the first dielectric layer 240 is, for example, silicon oxide. The method for forming the first dielectric layer 240 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the passivation layer 250 is made of silicon nitride, for example. The passivation layer 250 is formed by a chemical vapor deposition process, a physical vapor deposition process, or the like.
In some embodiments of the present application, the material of the second dielectric layer 260 is, for example, silicon oxide. The second dielectric layer 260 is formed by a chemical vapor deposition process, a physical vapor deposition process, or the like.
Referring to fig. 11, a test opening 270 exposing the body portion 211 of the test pad 210 is formed in the protective layer 230, the first dielectric layer 240, the passivation layer 250, and the second dielectric layer 260, and the device in the substrate 200 is electrically tested by connecting the body portion 211 of the test pad 210 through the test opening 270 using a test probe.
Referring to fig. 12, a filling layer 280 filling the test opening 270 is formed in the test opening 270.
In some embodiments of the present application, a method of forming a fill layer 280 in the test opening 270 that fills the test opening 270 includes: forming a filling material layer in the test opening 270 and on the surface of the second dielectric layer 260; and grinding to remove the filling material layer higher than the surface of the second dielectric layer 260 to form the filling layer 280.
In some embodiments of the present application, the filler layer 280 is the same material as the first dielectric layer 240 and the second dielectric layer 260, reducing the stress differential between the filler layer 280 and the first dielectric layer 240 and the second dielectric layer 260.
Referring to fig. 13, a metal connection structure 290 penetrating the second dielectric layer 260, the passivation layer 250, the first dielectric layer 240, and the protection layer 230 and electrically connecting the extension 212 of the test pad 210 and the metal layer 220, respectively, is formed in the protection layer 230, the first dielectric layer 240, the passivation layer 250, and the second dielectric layer 260.
In some embodiments of the present application, the material of the metal connection structure 290 includes a metal material such as aluminum, copper, or tungsten.
In some embodiments of the present application, the method of forming the metal connection structure 290 includes a single damascene process or a dual damascene process, etc.
On the one hand, in the method for forming the semiconductor structure shown in fig. 1 to 4, since the difference between the test pad 110 and the film structure above the metal layer 120 is large, the requirements on the manufacturing process of the metal connection structure 190 are high, strict selection of the etching agent and setting of the etching parameters are required, and multiple etching may be required, so that the process window is small. In the embodiment of the present application, the extension 212 of the test pad 210 and the film structure above the metal layer 220 are the same, so that the metal connection structure 290 is relatively simple to manufacture and has a large process window.
On the other hand, in the method for forming the semiconductor structure shown in fig. 1 to 4, since the positions of fabricating the test opening 170 and the metal connection structure 190 overlap, the fabrication of the test opening 170 affects the subsequent fabrication of the metal connection structure 190, which may cause problems or even failure in electrical connection of the test pad 110 of the metal connection structure 190, and reduce the device reliability and yield. In the embodiment of the present application, the test opening 270 and the metal connection structure 290 are respectively formed on the main body 211 and the extension 212 of the test pad 210, so that the manufacture of the test opening 270 no longer affects the manufacture of the metal connection structure 290, but the electrical communication between the metal connection structure 290 and the test pad 210 is not problematic or even fails, and the reliability and yield of the device can be improved.
According to the technical scheme, the yield test and the electrical test can be carried out on different types of chips before wafer-level hybrid bonding, and the bonding process is not affected. And the problems that the test welding pad is oxidized and the manufacturing process window of the metal connecting structure is small due to the test opening required during yield test are solved, the yield of hybrid bonding is greatly improved, and the process implementation difficulty is reduced.
The application provides a method for forming a semiconductor structure, which is characterized in that the position for manufacturing a test opening is distinguished from the position for manufacturing a metal connection structure, so that the test opening can not influence the manufacture of the metal connection structure any more, wafer bonding or communication failure can be avoided, and the reliability of a device is improved.
An embodiment of the present application further provides a semiconductor structure, as shown with reference to fig. 13, including: a substrate 200, wherein a test pad 210, a metal layer 220 and a protective layer 230 are formed on the surface of the substrate 200, and the test pad 210 comprises a main body 211 and an extension 212; the first dielectric layer 240, the passivation layer 250 and the second dielectric layer 260 are sequentially located on the surface of the substrate 200 and the surface of the protection layer 230; the metal connection structure 290 penetrates through the second dielectric layer 260, the passivation layer 250, the first dielectric layer 240 and the protection layer 230 and electrically connects the extension 212 of the test pad 210 and the metal layer 220, respectively.
Referring to fig. 13, in some embodiments of the present application, the substrate 200 includes a wafer 201 and an interlayer dielectric layer 202 on a surface of the wafer 201. The wafer 201 comprises a semiconductor wafer, such as a silicon wafer. The wafer 201 according to the embodiment of the present application may include any chip, such as a logic chip, a memory chip, an analog circuit chip, a microcontroller, etc.
In some embodiments of the present application, a metal wiring layer (not shown) is formed in the interlayer dielectric layer 202, and the metal wiring layer is used to electrically connect active devices in the wafer 201.
In some embodiments of the present application, the material of the interlayer dielectric layer 202 is, for example, silicon oxide.
With continued reference to fig. 13, the surface of the substrate 200 is formed with a test pad 210 and a metal layer 220, and a protective layer 230 on the surface of the test pad 210 and the metal layer 220, where the test pad 210 includes a main body 211 and an extension 212.
In some embodiments of the present application, the material of the test pad 210 is a metal material such as aluminum or copper.
In some embodiments of the present application, the material of the metal layer 220 is, for example, a metal material such as aluminum or copper.
In some embodiments of the present application, the material of the protective layer 230 is, for example, titanium nitride.
The test pad 210 and the metal layer 220 are electrically connected to a metal wiring layer in the interlayer dielectric layer 202.
The protection layer 230 is used to protect the test pad 210 and the metal layer 220 from oxidation.
The main body 211 of the test pad 210 is used for performing wafer testing, and the extension 212 of the test pad 210 is used for connecting with a metal connection structure, that is, a metal connection structure for electrically connecting with the test pad 210 is formed above the extension 212.
In some embodiments of the present application, for example, as shown in fig. 8, the extension 212 of the test pad 210 has a strip structure, and the metal connection structure electrically connected to the extension 212 of the test pad 210 is arranged in a linear manner at the extension 212 of the test pad 210.
In other embodiments of the present application, referring to fig. 9, the extension 212 of the test pad 210 includes a block structure, and the metal connection structure electrically connected to the extension 212 of the test pad 210 is arranged in a matrix at the extension 212 of the test pad 210. Such an arrangement may increase the distribution density of the metal connection structure.
With continued reference to fig. 13, a first dielectric layer 240, a passivation layer 250, and a second dielectric layer 260 are sequentially formed on the surface of the substrate 200 and the surface of the protective layer 230.
In some embodiments of the present application, the material of the first dielectric layer 240 is, for example, silicon oxide.
In some embodiments of the present application, the passivation layer 250 is made of silicon nitride, for example.
In some embodiments of the present application, the material of the second dielectric layer 260 is, for example, silicon oxide.
With continued reference to fig. 13, in some embodiments of the application, the semiconductor structure further comprises: and a filling layer 280 penetrating the second dielectric layer 260, the passivation layer 250, the first dielectric layer 240, and the protection layer 230 and connected to the body portion 211 of the test pad 210.
In some embodiments of the present application, the filler layer 280 is the same material as the first dielectric layer 240 and the second dielectric layer 260, reducing the stress differential between the filler layer 280 and the first dielectric layer 240 and the second dielectric layer 260.
With continued reference to fig. 13, a metal connection structure 290 penetrating the second dielectric layer 260, the passivation layer 250, the first dielectric layer 240, and the protection layer 230 and electrically connecting the extension 212 of the test pad 210 and the metal layer 220, respectively, is formed in the protection layer 230, the first dielectric layer 240, the passivation layer 250, and the second dielectric layer 260.
In some embodiments of the present application, the material of the metal connection structure 290 includes a metal material such as aluminum, copper, or tungsten.
In the semiconductor structure shown in fig. 4, the surface of the test pad 110 is oxidized during the process because the surface of the test pad 110 is not protected by the protection layer, so that the electrical connection of the test pad 110 of the metal connection structure 190 is problematic or even failed, and the reliability and yield of the device are reduced. In the embodiment of the present application, the extension 212 of the test pad 210 is protected by the protection layer 230 and is not oxidized, so that the electrical communication problem or even communication failure between the metal connection structure 290 and the test pad 210 is not caused, and the reliability and yield of the device can be improved.
According to the technical scheme, the yield test and the electrical test can be carried out on different types of chips before wafer-level hybrid bonding, and the bonding process is not affected. And the problems that the test welding pad is oxidized and the manufacturing process window of the metal connecting structure is small due to the test opening required during yield test are solved, the yield of hybrid bonding is greatly improved, and the process implementation difficulty is reduced.
The application provides a semiconductor structure and a forming method thereof, which are used for distinguishing the position for manufacturing a test opening from the position for manufacturing a metal connecting structure, so that the test opening can not influence the manufacturing of the metal connecting structure any more, wafer bonding or communication failure can be avoided, and the reliability of a device is improved.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Claims (11)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
Forming a test welding pad, a metal layer and a protective layer on the surfaces of the test welding pad and the metal layer on the surface of the substrate, wherein the test welding pad comprises a main body part and an extension part;
Sequentially forming a first dielectric layer, a passivation layer and a second dielectric layer on the surface of the substrate and the surface of the protective layer;
and forming a metal connection structure penetrating through the second dielectric layer, the passivation layer, the first dielectric layer and the protective layer and respectively and electrically connecting the extension part of the test welding pad and the metal layer in the protective layer, the first dielectric layer, the passivation layer and the second dielectric layer.
2. The method of claim 1, wherein the extension of the test pad is a stripe structure, and the metal connection structure electrically connected to the extension of the test pad is arranged in a linear manner at the extension of the test pad.
3. The method of claim 1, wherein the extension of the test pad comprises a block structure, and the metal connection structure electrically connecting the extension of the test pad is arranged in a matrix at the extension of the test pad.
4. The method of forming a semiconductor structure of claim 1, further comprising:
Forming a test opening exposing the main body part of the test welding pad in the protective layer, the first dielectric layer, the passivation layer and the second dielectric layer;
Performing an electrical test on the device in the substrate through the main body portion of the test pad;
and forming a filling layer filling the test opening in the test opening.
5. The method of forming a semiconductor structure of claim 1, wherein forming a test pad and a metal layer on a surface of the substrate and a protective layer on the surface of the test pad and the metal layer comprises:
Sequentially forming a metal material layer and a protective material layer on the surface of the substrate;
And etching the metal material layer and the protective material layer to form the test welding pad, the metal layer and the protective layer.
6. The method of claim 1, wherein the substrate comprises a wafer and an interlayer dielectric layer on a surface of the wafer.
7. A semiconductor structure, comprising:
the test device comprises a substrate, a test welding pad, a metal layer and a protective layer, wherein the test welding pad and the metal layer are formed on the surface of the substrate, and the protective layer is positioned on the surfaces of the test welding pad and the metal layer;
The first dielectric layer, the passivation layer and the second dielectric layer are sequentially positioned on the surface of the substrate and the surface of the protective layer;
and the metal connecting structure penetrates through the second dielectric layer, the passivation layer, the first dielectric layer and the protection layer and is respectively and electrically connected with the extension part of the test welding pad and the metal layer.
8. The semiconductor structure of claim 7, wherein the extension of the test pad is a stripe-like structure, and the metal connection structure electrically connecting the extension of the test pad is arranged in a linear arrangement at the extension of the test pad.
9. The semiconductor structure of claim 7, wherein the extension of the test pad comprises a block structure, and the metal connection structure electrically connecting the extension of the test pad is arranged in a matrix at the extension of the test pad.
10. The semiconductor structure of claim 7, further comprising: and the filling layer penetrates through the second dielectric layer, the passivation layer, the first dielectric layer and the protection layer and is connected with the main body part of the test welding pad.
11. The semiconductor structure of claim 7, wherein the substrate comprises a wafer and an interlayer dielectric layer on a surface of the wafer.
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| CN202211369587.4A CN118039608A (en) | 2022-11-03 | 2022-11-03 | Semiconductor structure and forming method thereof |
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| CN202211369587.4A CN118039608A (en) | 2022-11-03 | 2022-11-03 | Semiconductor structure and forming method thereof |
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