CN118039509A

CN118039509A - System and method for soldering semiconductor elements

Info

Publication number: CN118039509A
Application number: CN202410174466.7A
Authority: CN
Inventors: R·N·希拉克; D·A·迪安杰利斯; H·克劳贝格
Original assignee: Kulicke and Soffa Industries Inc
Current assignee: Kulicke and Soffa Industries Inc
Priority date: 2017-03-14
Filing date: 2018-03-14
Publication date: 2024-05-14
Also published as: TW201903911A; TWI752187B; KR20180105088A; CN108573883A; KR102453172B1

Abstract

A method of ultrasonically bonding a semiconductor element, comprising the steps of: (a) Aligning surfaces of the plurality of first conductive structures of the first semiconductor element with corresponding surfaces of the plurality of second conductive structures of the second semiconductor element; (b) Ultrasonically forming a locating bond between a number of the first conductive structures and a corresponding number of the second conductive structures; and (c) forming a complete bond between the first conductive structure and the second conductive structure.

Description

System and method for soldering semiconductor elements

The application is a divisional application of China patent application No. 201810210143.3 with the application date of 2018, 3-14 and the name of "System and method for bonding semiconductor elements".

Cross Reference to Related Applications

The present application is a partial continuation of the 15/147,015 application filed 5/2016, which 15/147,015 application is a divisional application of the 14/822,164 application filed 10/2015, which 14/822,164 application is a continuation of the 14/505,609 application filed 3/2014 (now U.S. patent 9,136,240), which 14/505,609 application claims the benefit of the provisional application 61/888,203 filed 8/2013, each of which is incorporated herein by reference.

Technical Field

The present invention relates to the formation of semiconductor packages, and more particularly to an improved system and method for bonding semiconductor elements together.

Background

Conventional semiconductor packages typically include a die attach process and a wire bonding process. In this industry, advanced semiconductor packaging techniques (e.g., flip chip bonding, thermocompression bonding, etc.) are gaining more attention. For example, in thermocompression bonding, heat and pressure are used to form a plurality of interconnections between semiconductor elements.

While the use of advanced packaging techniques is increasing, there are many limitations in these techniques, including, for example, limitations associated with the relatively early stages (RELATIVE INFANCY) of some advanced packaging techniques. Accordingly, it is desirable to provide improved systems and methods for bonding semiconductor elements together.

Disclosure of Invention

According to an exemplary embodiment of the present invention, a method of ultrasonically bonding a semiconductor element is provided. The method comprises the following steps: (a) Aligning surfaces of the plurality of first conductive structures of the first semiconductor element with corresponding surfaces of the plurality of second conductive structures of the second semiconductor element; (b) Forming a positioning bonding portion ultrasonically between a plurality of first conductive structures of the first conductive structures and a corresponding plurality of second conductive structures of the second conductive structures; and (c) forming a complete bond between the first conductive structure and the second conductive structure.

According to another exemplary embodiment of the present invention, a bonding system is provided. The bonding system includes a support structure for supporting a first semiconductor element including a plurality of first conductive structures. The bonding system further includes a bonding tool for carrying a second semiconductor element including a plurality of second conductive structures and for applying ultrasonic energy to the second semiconductor element to form positional bonds between a number of the plurality of second conductive structures and a corresponding number of the plurality of first conductive structures.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, according to common practice, the various features of the drawings are not drawn to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. The following figures are included in the drawings:

fig. 1A to 1C are block diagrams of portions of an ultrasonic bonding machine, which illustrate a structure and a method of bonding an upper semiconductor element to a lower semiconductor element according to an exemplary embodiment of the present invention;

Fig. 2A is a block diagram of a portion of an ultrasonic bonder showing a structure and method of bonding an upper semiconductor element to a lower semiconductor element according to another exemplary embodiment of the invention;

FIG. 2B is an enlarged view of the "FIG. 2B" portion of FIG. 2A;

FIG. 2C is a view of FIG. 2B after ultrasonic bonding;

Fig. 3 is a block diagram of a portion of an ultrasonic bonding machine showing a structure and method of bonding an upper semiconductor element to a lower semiconductor element according to yet another exemplary embodiment of the present invention;

fig. 4A is a block diagram of a portion of an ultrasonic bonder showing a structure and method of bonding an upper semiconductor element to a lower semiconductor element according to yet another exemplary embodiment of the invention;

FIG. 4B is an enlarged view of the "FIG. 4B" portion of FIG. 4A;

FIG. 4C is a view of FIG. 4B after ultrasonic bonding;

Fig. 5A is a block diagram of a portion of an ultrasonic bonder showing a structure and method of bonding an upper semiconductor element to a lower semiconductor element according to another exemplary embodiment of the invention;

FIG. 5B is an enlarged view of the "FIG. 5B" portion of FIG. 5A;

FIG. 5C is a view of FIG. 5B after ultrasonic bonding;

Fig. 6A is a block diagram of a portion of an ultrasonic bonder showing a structure and method of bonding an upper semiconductor element to a lower semiconductor element according to yet another exemplary embodiment of the invention;

FIG. 6B is an enlarged view of the "FIG. 6B" portion of FIG. 6A;

FIG. 6C is a view of a portion of FIG. 6A after contact between conductive structures;

Fig. 7 is a flowchart illustrating a method of ultrasonically bonding a semiconductor element according to an exemplary embodiment of the invention;

Fig. 8A to 8E are block diagrams of portions of an ultrasonic bonding machine, which illustrate a structure and a method of bonding an upper semiconductor element to a lower semiconductor element according to an exemplary embodiment of the present invention;

fig. 9 is a flowchart illustrating a method of ultrasonically bonding a semiconductor element according to an exemplary embodiment of the invention;

fig. 10A to 10E are block diagrams of portions of an ultrasonic bonding machine, which illustrate another structure and method of bonding an upper semiconductor element to a lower semiconductor element according to still another exemplary embodiment of the present invention;

fig. 11 is a flowchart illustrating yet another method of ultrasonically bonding a semiconductor element in accordance with yet another exemplary embodiment of the invention;

Fig. 12A to 12D are block diagrams of portions of an ultrasonic bonding machine, which illustrate yet another structure and method of bonding an upper semiconductor element to a lower semiconductor element according to yet another exemplary embodiment of the present invention;

Fig. 13 is a flowchart illustrating yet another method of ultrasonically bonding a semiconductor element in accordance with yet another exemplary embodiment of the invention;

Fig. 14A to 14D are block diagrams of portions of an ultrasonic bonding machine, which illustrate yet another structure and method of bonding an upper semiconductor element to a lower semiconductor element according to yet another exemplary embodiment of the present invention; and

Fig. 15 is a flowchart illustrating yet another method of ultrasonically bonding a semiconductor element according to yet another exemplary embodiment of the invention.

Detailed Description

As used herein, the term "semiconductor element" is intended to mean any structure that includes (or is configured to include in a subsequent step) a semiconductor chip or die. Exemplary semiconductor elements include bare semiconductor die, semiconductor die on a substrate (e.g., leadframe, PCB, carrier, etc.), packaged semiconductor devices, flip-chip semiconductor devices, die embedded in a substrate, stacks of semiconductor die, etc. Further, the semiconductor element may include elements (e.g., spacers, substrates, etc., incorporated in a stacked die configuration) configured to be bonded or otherwise included in a semiconductor package.

In accordance with certain exemplary embodiments of the present invention, innovative techniques (and structures) are provided for assembling semiconductor devices such as package-on-package (i.e., poP) structures. For example, a plurality of semiconductor elements (which may be packages) may be arranged in a stacked configuration. Each of these elements preferably comprises an aluminum (or aluminum alloy, or partially aluminum (PARTIALLY ALUMINUM)) conductive structure that is ultrasonically bonded together. This technique has certain advantages, including, for example: density reduction compared to other interconnect technologies (e.g., solder-based PoP technology); in contrast to other interconnect technologies, solder bump reflow is not used; and in some applications enables room temperature ultrasonic bonding through the use of aluminum-aluminum interconnects.

Fig. 1A shows a portion of an ultrasonic bonder 100, the ultrasonic bonder 100 including a bonding tool 124 and a support structure 150. As will be appreciated by those skilled in the art, a thermocompression bonding machine (such as machine 100 or any other machine embodiment described herein) may include many elements that are not shown in the figures for simplicity. Exemplary elements include, for example: an input element for providing an input workpiece to be bonded with other semiconductor elements; an output element for receiving the processed workpiece including the other semiconductor elements at this time; a conveyor system for moving the workpiece; an imaging system for imaging and aligning a workpiece; a bond head assembly carrying a bonding tool; a motion system for moving the bond head assembly; a computer system including software for operating the machine; as well as other elements.

Referring again to fig. 1A, the upper semiconductor element 108 is held by the holding portion 110 of the bonding tool 124 (e.g., by vacuum, such as through a vacuum port defined by a holding surface of the holding portion 110). The upper semiconductor element 108 includes upper conductive structures 112a and 112b on its lower surface. The lower semiconductor element 160 includes a semiconductor die 102 bonded to the substrate 104 (or otherwise supported by the substrate 104). Lower conductive structures 106a and 106b are disposed on the upper surface of the lower semiconductor die 102. The substrate 104 is in turn supported by a support structure 150 (e.g., a heating block of the machine 100, an anvil of the machine 100, or any other desired support structure). In the configuration shown in fig. 1A (ready for bonding), each of the upper conductive structures 112a and 112b is generally aligned with the opposing respective lower conductive structures 106a and 106 b. The semiconductor element 108 is moved downward by the motion of the bonding tool 124 (as indicated by arrow 126 in fig. 1A). After this movement, fig. 1B shows the contact between the respective conductive structures 106a and 112a and 106B and 112B. Ultrasonic energy 114 is applied to the upper semiconductor element 108 and the upper conductive structures 112a and 112b by a bonding tool 124 using an ultrasonic transducer (not shown, but represented in the figures as a "USG," i.e., an ultrasonic generator). For example, an ultrasonic transducer carrying bonding tool 124 may in turn be carried by a bond head assembly of machine 100.

During ultrasonic bonding, the lower conductive structures 106a and 106b may remain relatively stationary by the support provided to the lower semiconductor element 160 by the support structure 150 (e.g., the support surface of the support structure 150 may include one or more vacuum ports to secure the substrate 104 to the support structure 150 during bonding). Ultrasonic energy 114 (along with optional bonding forces and/or heat) may locally deform the conductive structure. For example, in fig. 1C, conductive structures 106a and 106b and 112a and 112b are shown as being partially deformed. In fig. 1C, ultrasonic bonding portions are formed between respective pairs of conductive structures. For example, ultrasonic bonds 128a are formed between deformed conductive structures 112a '/106a', and ultrasonic bonds 128b are formed between deformed conductive structures 112b '/106 b'. The conductive structures 106a and 106b and 112a and 112b may be formed of aluminum or an aluminum alloy, or may include aluminum at their bonding surfaces, or the like.

The respective pairs of conductive elements 106a and 112a and 106b and 112b may be bonded together at room temperature (without the addition of heat during the bonding process). Optionally, additional heat may be applied, for example: (1) During the bonding process, additional heat is applied to the upper semiconductor element 108 by the bonding tool 124, thereby heating the upper conductive elements 112a and 112b; and/or (2) during the bonding process, additional heat is applied to the lower semiconductor element 160 through the support structure 150 (e.g., the heating block 150), thereby heating the lower conductive structures 106a and 106b. Such optional heating (e.g., by a bonding tool and/or support structure, etc.) is applicable to any of the embodiments of the invention shown and described herein.

The semiconductor elements 160 and 108 shown in fig. 1A to 1C may be any one of a plurality of semiconductor elements configured to be bonded together. In one particularly specific example (which may also be suitable for the other embodiments shown and described herein), semiconductor element 160 is a processor (e.g., a mobile phone processor, which may also be referred to as an APU (application processor unit)), and semiconductor element 108 is a memory device configured to be bonded to the processor as shown in fig. 1A-1C.

The conductive structures (i.e., 112a, 112b, 106a, 106 b) shown in fig. 1A-1C are shown as generic structures. These structures may take many different forms, such as conductive pillars, stud bumps (e.g., formed using a stud bumping machine), plated conductive structures, sputtered conductive structures, lead portions, bond pads, contact pads, and others. Various other figures provided herein illustrate specific examples of these structures. According to some embodiments of the application, the conductive structure is that the contact area (i.e., bonding surface) at which the conductive structure is to be bonded to other conductive structures comprises aluminum. In these embodiments, the conductive structure may be formed from aluminum or an aluminum alloy (e.g., aluminum alloyed with copper, aluminum alloyed with silicon and copper, etc.). In other examples, the conductive structure may include a base conductive material other than aluminum (e.g., copper) and aluminum (or aluminum alloy) at the contact region. In the present application, if the conductive structure is referred to as "aluminum", it is understood that the structure may be aluminum, may be an aluminum alloy, or may include aluminum (or an aluminum alloy) in the contact area of such a conductive structure.

Fig. 2A shows a portion of an ultrasonic bonder 200, the ultrasonic bonder 200 including a bonding tool 224 and a support structure 250. The upper semiconductor element 208 is held by the holding portion 210 of the bonding tool 224 (e.g., by vacuum), and includes upper conductive structures 222a and 222b (i.e., conductive aluminum pads 222a and 222 b) disposed at a lower surface thereof. The lower semiconductor element 260 includes a semiconductor die 202 bonded to the substrate 204 (or otherwise supported by the substrate 204). Lower conductive structures 206a and 206b are disposed on an upper surface of the lower semiconductor die 202. The substrate 204 is in turn supported by a support structure 250. In the configuration shown in fig. 2A, each of the upper conductive structures 222A and 222b is generally aligned with (and configured to be ultrasonically bonded to) the opposing respective lower conductive structures 206a and 206 b. The lower conductive structure 206a includes copper (Cu) pillars 230 disposed on an upper surface of the lower semiconductor die 202 and an upper aluminum contact structure 216 located on an upper surface of the Cu pillars 230. The upper aluminum contact structure 216 may be, for example, electroplated or sputtered onto the upper surface of the lower copper pillar 230. Fig. 2B is an enlarged view of the portion "B" of fig. 2A and shows the top of the lower conductive structure 206a in contact with the upper conductive element 222A.

Ultrasonic energy is applied to the upper semiconductor element 208 by the bonding tool 224 using an ultrasonic transducer (not shown). As shown in fig. 2C, the ultrasonic energy may locally deform the conductive structure. That is, the ultrasonic bonding portion 228 is formed between the deformed upper conductive structure 222a 'and the deformed contact structure 216' (as shown in fig. 2C).

As will be appreciated by those skilled in the art, cu pillars 230 (including electroplated or sputtered aluminum contact structures/portions 216) are but one example of conductive structures that include aluminum. Fig. 2A also illustrates another exemplary conductive structure 206b. The lower conductive structure 206b is an aluminum structure (or aluminum alloy structure) such as a portion of an aluminum wire (which may be bonded using a wire bonding process), an aluminum pillar, or the like.

Fig. 3 shows a portion of an ultrasonic bonder 300, the ultrasonic bonder 300 including a bonding tool 324 and a support structure 350. The upper semiconductor element 308 is held by the holding portion 310 of the bonding tool 324 (e.g., by vacuum) and includes upper conductive structures 322a and 322b (i.e., conductive aluminum pads 322a and 322 b). Fig. 3 illustrates the bonding of a packaged semiconductor device 360 (i.e., a lower semiconductor element 360) to an upper semiconductor element 308. The lower semiconductor element 360 includes a semiconductor die 302 bonded to a substrate 304 (or otherwise supported by the substrate 304). Lower conductive structures 306a and 306b are disposed on an upper surface of substrate 304. The substrate 304 is in turn supported by a support structure 350. Wire loops 320a and 320b are bonded between semiconductor die 302 and substrate 304 (although not shown in fig. 3, die 302 may be flip-chip bonded to substrate 304 as opposed to or in addition to wire loop interconnection). A coating/encapsulation 334 (e.g., epoxy molding compound) has been applied over die 302 and wire loops 320a and 320 b. As shown, the upper portions of the lower conductive structures 306a and 306b are exposed above the coating/encapsulation 334 to allow electrical connection to the upper semiconductor element 308.

In the configuration shown in fig. 3, each of the upper conductive structures 322a and 322b is generally aligned with (and configured to be ultrasonically bonded to) the opposing respective lower conductive structures 306a and 306 b. As shown in fig. 3, each of the lower conductive structures 306a and 306b includes a respective Cu pillar 330a and 330b on an upper surface of the substrate 304, and a respective upper aluminum contact structure 316a and 316b on an upper surface of the Cu pillar 330a and 330 b. The upper aluminum contact structures 316a and 316b may be electroplated or sputtered onto the respective upper surfaces of the Cu pillars 330a and 330 b. As shown, semiconductor element 308 has been moved downward by movement of bonding tool 324 (as indicated by the arrow in fig. 3), such that fig. 3 shows contact between conductive structures 306a and 322a and 306b and 322 b. Ultrasonic energy (along with optional heat and/or bonding forces) is applied to the upper semiconductor element 308 (e.g., by bonding tool 324) using an ultrasonic transducer to form an ultrasonic bond between the aluminum conductive structures 322a and 322b and the respective aluminum contact structures 316a and 316b.

Fig. 4A shows a portion of an ultrasonic bonder 400, the ultrasonic bonder 400 including a bonding tool 424 and a support structure 450. The upper semiconductor element 408 is held by a holding portion 410 of a bonding tool 424 (e.g., by vacuum) and includes upper conductive structures 412a and 412b (i.e., e.g., sputtered aluminum bumps, aluminum pillar bumps, etc.) on its lower surface. The lower semiconductor element 460 includes the semiconductor die 402 bonded to the support structure 404 (e.g., FR4 support structure) (or otherwise supported by the support structure 404). Lower conductive structures 406a and 406b (i.e., e.g., sputtered aluminum bumps, aluminum pillar bumps, etc.) are disposed on the upper surface of the lower semiconductor die 402. The substrate 404 is in turn supported by a support structure 450. In the configuration shown in fig. 4A, each of the upper conductive structures 412a and 412b is generally aligned with (and configured to be ultrasonically bonded to) the opposing respective lower conductive structures 406a and 406 b. Fig. 4B shows details of structures 412a and 406a (prior to ultrasonic bonding). Referring again to fig. 4A, semiconductor element 408 has been moved downward by movement of bonding tool 424 (as indicated by the arrow in fig. 4A) such that contacts are shown between conductive structures 406a and 412a and 406b and 412 b. Ultrasonic energy 414 (together with optional heat and/or bonding forces) is applied to the upper semiconductor element 408 (e.g., by the bonding tool 424) using an ultrasonic transducer to form ultrasonic bonds 428a and 428b between the deformed upper aluminum conductive structure and the deformed corresponding lower aluminum contact structure (see, e.g., completed ultrasonic bonds 428a ' formed between deformed structures 412a ' and 406a ' as shown in fig. 4C).

Fig. 5A shows a portion of an ultrasonic bonder 500, the ultrasonic bonder 500 including a bonding tool 524 and a support structure 550. The upper semiconductor element 508 is held by the holding portion 510 of the bonding tool 524 (e.g., by vacuum) and includes upper conductive structures 522a and 522b (i.e., conductive aluminum pads 522a and 522 b). The lower semiconductor element 560 includes a semiconductor die 502 bonded to a substrate 504 (e.g., FR4 support structure) (or otherwise supported by the substrate 504). Lower conductive structures 506a and 506b (i.e., e.g., sputtered aluminum bumps, aluminum pillar bumps, etc.) are disposed on an upper surface of the lower semiconductor die 502. The substrate 504 is in turn supported by a support structure 550. In the configuration shown in fig. 5A, each of the upper conductive structures 522a and 522b is generally aligned with (and configured to be ultrasonically bonded to) the opposing respective lower conductive structures 506a and 506 b. Fig. 5B shows details of structures 522a and 506a (prior to ultrasonic bonding). As shown, semiconductor element 508 has been moved downward by movement of bonding tool 524 (as indicated by the arrow in fig. 5A) such that fig. 5A illustrates contact between conductive structures 506a and 522 a. Ultrasonic energy (together with optional heat and/or bonding forces) is applied to the upper semiconductor element 508 (e.g., by bonding tool 524) using an ultrasonic transducer to form ultrasonic bonds 528a and 528b between the deformed upper aluminum conductive structure and the deformed corresponding lower aluminum contact structure (see, e.g., completed ultrasonic bonds 528a ' formed between deformed structures 522a ' and 506a ' as shown in fig. 5C).

Fig. 6A shows a portion of an ultrasonic bonder 600, the ultrasonic bonder 600 including a bonding tool 624 and a support structure 650. In fig. 6, a plurality of semiconductor elements have been bonded together in a stacked configuration in accordance with the teachings of the present invention. Specifically, the semiconductor element 660a includes a semiconductor die 602a bonded to a substrate 604a (or otherwise supported by the substrate 604 a), with conductive structures 606a and 606b (i.e., e.g., sputtered aluminum bumps, aluminum pillar bumps, etc.) disposed on an upper surface of the semiconductor die 602 a. The semiconductor element 660a is supported by a support structure 650.

Another semiconductor element 660b (comprising a respective semiconductor die 602b bonded to substrate 604b or otherwise supported by substrate 604b, and comprising conductive structures 612a and 612b on substrate 604 b) has been previously bonded to semiconductor element 660a. Specifically, the bonding tool 624 previously bonds (e.g., ultrasonically bonds) the element 660b to the element 660a such that ultrasonic bonds 628a and 628b are formed between respective pairs of aluminum conductive structures 612a and 606a and 612b and 606 b. Element 660b also includes conductive structures 606a 'and 606b', which have been bonded to the conductive structure of element 660c in the steps described below. Fig. 6B shows a detailed view of an ultrasonic bond 628a that includes deformed conductive structures 612a and 606 a.

Similarly, yet another semiconductor element 660c (including a respective semiconductor die 602c bonded to substrate 604c or otherwise supported by substrate 604c, and including conductive structures 612a 'and 612 b') on substrate 604c has been previously bonded to semiconductor element 660b. Specifically, the bonding tool 624 previously bonds (e.g., ultrasonically bonds) the element 660c to the element 660b such that ultrasonic bonds 628a 'and 628b' are formed between respective pairs of aluminum conductive structures 612a 'and 606a' and 612b 'and 606 b'. Element 660c also includes conductive structures 606a "and 606b" that have been bonded to the conductive structure of element 660d in the steps described below.

As shown in fig. 6A, the upper semiconductor element 660d is held by the holding portion 610 of the bonding tool 624 (e.g., by vacuum) and includes a semiconductor die 602d bonded to the substrate 604d (or otherwise supported by the substrate 604 d). Conductive structures 612a "and 612b" (i.e., sputtered aluminum bumps, aluminum pillar bumps, etc., for example) are disposed on the lower surface of the substrate 604 d. The conductive structures 612a "and 612b" are generally aligned with (and configured to be ultrasonically bonded to) the opposing respective conductive structures 606a "and 606 b"). The semiconductor element 660d is moved downward by the movement of the bonding tool 624 (as indicated by the arrow in fig. 6A). After this downward movement, contact occurs between the respective pairs of conductive structures 612a "and 606a" and 612b "and 606b" (see, e.g., a detailed view of contact between structures 612a "and 606a" of fig. 6C prior to deformation by ultrasonic bonding). Ultrasonic energy is applied to the upper semiconductor element 604d by bonding tool 624 using an ultrasonic transducer (not shown) to form an ultrasonic bond between the respective pairs of conductive structures 612a "and 606a" and 612b "and 606 b".

While specific exemplary upper and lower aluminum conductive structures have been shown, those skilled in the art will appreciate that various shapes and designs of upper and lower aluminum conductive structures are permitted within the teachings of the present invention.

Fig. 7 is a flowchart illustrating a method of bonding semiconductors together according to an exemplary embodiment of the present invention. As will be appreciated by those of skill in the art, certain steps included in the flow diagrams may be omitted; additional steps may be added; and the order of the steps may be changed relative to the order shown. In step 700, a first semiconductor element (e.g., including a semiconductor die on a substrate) is supported on a support structure of a bonder. The first semiconductor element (e.g., the upper surface of the semiconductor structure) includes a plurality of first conductive structures (see, e.g., structures 106A and 106b of element 160 in fig. 1A, structures 206A and 206b of element 260 in fig. 2A, structures 306A and 306b of element 360 in fig. 3, structures 406A and 406b of element 460 in fig. 4A, structures 506A and 506b of element 560 in fig. 5A, and structures 606A "and 606b" of element 660c in fig. 6A) that are at least partially composed of aluminum. In step 702, a second semiconductor element is held by a holding portion of a bonding tool of a bonding machine (see, e.g., elements 108, 208, 308, 408, 508, and 660d in the respective figures). The second semiconductor element includes a plurality of second conductive structures (e.g., located on a lower surface of the second semiconductor element) that are at least partially composed of aluminum. In step 704, the first conductive structure and the second conductive structure are aligned with each other (see, e.g., fig. 1A and 6A), and then brought into contact with each other. In optional step 706, the plurality of aligned first and second conductive structures are pressed together with a predetermined amount of bonding force. The predetermined magnitude of the bonding force may be a single bonding force value, or may be a bonding force profile in which an actual bonding force varies during a bonding operation. In optional step 708, heat is applied to the plurality of aligned first conductive structures and/or second conductive structures. For example, a support structure supporting the first semiconductor element may be used to apply heat to the first conductive structure. Similarly, a bonding tool holding the second semiconductor element may be used to apply heat to the second conductive structure. In step 710, a plurality of first conductive structures and second conductive structures are ultrasonically bonded together to form an ultrasonic bond therebetween.

As will be appreciated by those skilled in the art, the present invention is particularly advantageous when ambient/lower temperature bonding operations are desired, as the present invention bonds aluminum materials to aluminum materials, which can be readily accomplished using ultrasonic energy and/or bonding forces, without generally requiring heating.

Although the invention has been shown and described primarily with respect to two pairs of conductive structures that are ultrasonically bonded together, the invention is of course not limited thereto. Indeed, a semiconductor package (e.g., advanced package) assembled in accordance with the present invention may have any number of conductive structures, and may have hundreds (or even thousands) of pairs of conductive structures ultrasonically bonded together. Furthermore, the conductive structures do not need to be bonded in pairs. For example, one structure may be bonded to two or more opposing structures. Thus, any number of conductive structures from one semiconductor element may be ultrasonically bonded to any number of conductive structures of another semiconductor.

Although the present invention is primarily described (and illustrated) with respect to the application of ultrasonic energy by a bonding tool (e.g., where the bonding tool engages an ultrasonic transducer), the present invention is not so limited. Rather, the ultrasonic energy may be transmitted through any desired structure, such as a support structure.

As will be appreciated by those skilled in the art, the details of the ultrasonic bonding may vary widely depending on the particular application. Nonetheless, some non-limiting exemplary details are now described. For example, the frequency of an ultrasonic transducer may be designed in conjunction with the design of conductive structures (e.g., post structures, etc.) such that the resonant frequency of the transducer approximately coincides with the resonant frequency of a given semiconductor element, in which case the conductive structures may act dynamically as cantilever beams. In another exemplary alternative, the transducer can be operated in a simple "driven" type manner in a non-resonant state with respect to the semiconductor element.

Exemplary ranges of energy applied to the ultrasonic transducer (e.g., to the piezoelectric crystal/ceramic in the transducer driver) may be in the range of 0.1kHz to 160kHz, 10kHz to 120kHz, 20kHz to 60kHz, etc. During bonding, a single frequency may be applied, or multiple frequencies may be applied (e.g., sequentially, simultaneously, or sequentially and simultaneously). Scrubbing (scrub) of the semiconductor element (i.e., vibrational energy applied to the semiconductor element held by the bonding tool) may be applied in any of a number of desired directions, and may be applied by the bonding tool holding the semiconductor element (as shown herein), by a support structure supporting the semiconductor element, and other configurations. With specific reference to the embodiments shown herein in which ultrasonic energy is applied by a bonding tool holding a semiconductor element, scrubbing may be applied in a direction generally parallel to or generally perpendicular to the longitudinal axis of the bonding tool (or in other directions).

The vibrational energy applied by the ultrasonic transducer may be applied, for example, in a peak-to-peak amplitude range of 0.1um to 10um (e.g., with feedback control over a constant voltage, constant current, or an alternating control scheme including, but not limited to, a ramp current, ramp voltage, or proportional feedback control based on one or more inputs).

The bonding force may also be applied during at least a portion of the ultrasonic bonding cycle, as described herein. An exemplary range of bonding forces is 0.1kg to 100kg. The bonding force may be applied as a constant value or may be a bonding force profile that changes during the bonding cycle. In a controlled bond force embodiment, feedback control of the bond force may be constant, ramped or proportional based on one or more inputs (e.g., ultrasonic amplitude, time, velocity, deformation, temperature, etc.).

As described herein, one or more of the semiconductor elements may be heated prior to and/or during the bonding cycle. An exemplary temperature range for the semiconductor element is between 20 ℃ and 250 ℃. The heat (e.g., applied by one or both of the bonding tool and the support structure, or other elements) may be applied as a constant value, or may be a temperature profile that changes during the bonding cycle, and may be controlled using feedback control.

Although the invention has been shown and described primarily with respect to forming ultrasonic bonds between aluminum conductive structures located on respective semiconductor elements, the invention is of course not limited thereto. That is, the teachings of the present invention may be applied to forming ultrasonic bonds between conductive structures having different compositions. An exemplary list of materials for the connected conductive structures includes: aluminum and copper (i.e., forming an ultrasonic bond between an aluminum conductive structure on one semiconductor element and a copper conductive structure on the other semiconductor element); lead-free solders (e.g., consisting essentially of tin) and copper; lead-free solder and aluminum; copper and copper; aluminum and silver; copper and silver; aluminum and gold; gold and gold; and copper and gold. Of course, other combinations of conductive structural components (e.g., indium) are contemplated.

As provided above, although aspects of the present invention have been described in connection with aluminum materials included in various conductive structures of semiconductor elements, the present invention is not limited thereto. That is, the conductive structures located on the semiconductor element may include (or be formed of) a variety of different materials. For example, the conductive structures located on the upper semiconductor element (e.g., the element that is carried and bonded using the bonding tool) and/or the conductive structures located on the lower semiconductor element (e.g., the element to which the upper conductive element is bonded) may be formed of (or include) copper.

According to certain aspects of the invention, ultrasonic scrubbing/energy may be used in conjunction with a multi-step bonding process. For example, ultrasonic scrubbing/energy may be used as a start of flip chip and/or thermocompression bonding process (initiator). For example, ultrasonic scrubbing may be used to remove oxide associated with forming the initial bond, thereby providing for a final connection process (e.g., a diffusion connection process). Such a multi-step bonding process may have many different configurations. For example, using ultrasonic scrubbing/energy, the bonding tool may form an initial bond (e.g., a "tack" bond) between a first conductive structure located on a first semiconductor element and a second conductive structure located on a second semiconductor element. The bond may be accomplished using the same bonding tool (e.g., by applying heat and/or force), with fig. 8A-8D showing one example of such a process. In another example, bonding may be accomplished later using a different process (e.g., on the same bonder, on a different bonder, etc.). Using this subsequent (different) process, the bonding of multiple elements can be accomplished simultaneously by a "gang" bonding process, with the addition of fig. 8E showing one example of such a process along with fig. 8A-8C.

Thus, in accordance with certain embodiments of the present invention, stable and robust soldering is initiated using ultrasonic scrubbing (along with force, as needed) prior to subsequent flip-chip and/or thermocompression bonding of a semiconductor element (e.g., semiconductor die) to another semiconductor element (e.g., to a substrate, to another die, to a wafer, etc.). The ultrasonic motion erases the oxide on the surface to be connected. The ultrasonic scrubbing and/or force is intended to position the interconnects (i.e., the conductive structures of the first semiconductor element and the conductive structures of the second semiconductor element) together, which helps to prevent oxidation of the bonding surfaces of the conductive structures. Examples of conductive structures to be connected include: sn and Cu, cu and Al, al and Al, and Cu. Of course, other combinations of conductive structural materials are contemplated. After positioning, the semiconductor elements (e.g., die) may be bonded individually or in groups.

Fig. 8A-8E (along with the flowchart of fig. 9), fig. 10A-10E (along with the flowchart of fig. 11), fig. 12A-12D (along with the flowchart of fig. 13), and fig. 14A-14D (along with the flowchart of fig. 15) illustrate a system and method for forming an interconnect between semiconductor elements using an exemplary multi-step bonding process. Fig. 9, 11, 13, and 15 are flowcharts illustrating a method of bonding semiconductor elements together according to an exemplary embodiment of the present invention. As will be appreciated by those of skill in the art, certain steps included in the flow diagrams may be omitted; certain additional steps may be added; and the order of the steps may be changed relative to the order shown.

Referring specifically to fig. 8A, the upper semiconductor element 808 is held by a holding portion 810 of a bonding tool 824 (e.g., by vacuum, such as through a vacuum port defined by a holding surface of the holding portion 810). The upper semiconductor element 808 includes upper conductive structures 812a and 812b (e.g., copper conductive structures such as copper pillars or other conductive structures) on its lower surface. The lower semiconductor element 860 includes a semiconductor die 802 bonded to a substrate 804 (or otherwise supported by the substrate 804). For example, the substrate 804 may be an organic substrate, a semiconductor wafer, a temporary support structure (e.g., a silicon, metal, or glass wafer or panel), and other substrates. In another example, the semiconductor die 802 may be part of a semiconductor wafer regardless of how the figures show a separate substrate 804. Lower conductive structures 806a and 806b (e.g., copper conductive structures such as copper pillars or other conductive structures) are disposed on an upper surface of the lower semiconductor die 802. The substrate 804 is in turn supported by a support structure 850 (e.g., a heating block of the machine 800, an anvil of the machine 800, or any other desired support structure). Alternatively, the semiconductor die 802 may still be part of a whole or part of a wafer directly supported by the support structure 850 without any additional intervening substrate (INTERVENING SUBSTRATE) 804. In the configuration shown in fig. 8A (ready for bonding), each of the upper conductive structures 812a and 812b is generally aligned with the opposing respective lower conductive structures 806a and 806 b. The semiconductor element 808 is moved downward by the motion of the bonding tool 824 (as indicated by arrow 826 in fig. 8A). After this movement, fig. 8B shows the contact between the respective conductive structures 806a and 812a and 806B and 812B. Ultrasonic energy 814 is applied to the upper semiconductor element 808 and the upper conductive structures 812a and 812b by a bonding tool 824 using an ultrasonic transducer (not shown, but represented in the figures as a "USG," i.e., an ultrasonic generator). For example, the ultrasonic transducer carrying the bonding tool 824 may in turn be carried by the bond head assembly of the flip chip bonder 800. During ultrasonic bonding, the lower conductive structures 806a and 806b may remain relatively stationary by the support provided to the lower semiconductor element 860 by the support structure 850 (e.g., the support surface of the support structure 850 may include one or more vacuum ports to secure the substrate 804 to the support structure 850 during bonding). Ultrasonic energy 814 (along with optional bonding forces and/or heat) may locally deform the conductive structure. For example, in fig. 8C, conductive structures 806a and 806b and 812a and 812b are shown deformed (or at least partially deformed). In fig. 8C, initial (positioning) ultrasonic bonding portions are formed between respective pairs of conductive structures. For example, as shown in fig. 8C, an initial (e.g., locating) ultrasonic bond 828a is formed between deformed conductive structures 812a '/806a', and an initial (e.g., locating) ultrasonic bond 828b is formed between deformed conductive structures 812b '/806 b'.

In some embodiments of the present invention, a multi-step bonding process may be accomplished as shown in fig. 8D. That is, an initial (locating) bond has been formed in fig. 8C, and heat and/or force from bonding tool 824 or a different bonding tool 824a (e.g., on the same or a different machine) may be used to form a final bond in fig. 8D.

In other embodiments of the invention, different bonding tools (e.g., on the same or different machines) may be used to form the final bond on a group or "group" basis (e.g., simultaneously bonding multiple semiconductor elements) as shown in fig. 8E. In such an embodiment, after fig. 8C, the conductive structures of semiconductor elements 808 and 860 are "positionally" bonded together. Subsequently, in fig. 8E, a set of upper semiconductor elements 808 are "group" bonded (e.g., using heat and/or force) to a corresponding set of lower semiconductor elements 860. In the example shown in fig. 8E, a cluster bonding tool 875 is provided, which tool 875 may be used on the machine 800 of fig. 8A or a different flip chip and/or thermocompressor. If on the same machine, a support structure 850 (fig. 8A) may be used to support the plurality of lower semiconductor elements 860 during the "group" bonding process. The support structure 879 may be used to support a plurality of lower semiconductor elements 860 during a "group" bonding process if on a different machine. The "group" bonding tool 875 (including the retention portion 877) completes the bonding of the conductive structures of the plurality of upper semiconductor elements 808 to the conductive structures of the corresponding lower semiconductor elements 860 (wherein each element 860 includes a die 802 as described above in connection with fig. 8A). During this final bonding process, heat and/or force may be provided by the bonding tool 875, by the support structure 850/879, or by the bonding tool 875 and the support structure 850/879.

Referring specifically to fig. 9, in step 900, a first semiconductor element (e.g., comprising a semiconductor die on a substrate, such as element 860 shown in fig. 8A) is supported on a support structure of a bonding machine. The first semiconductor element (e.g., an upper surface of the semiconductor structure) includes a plurality of first conductive structures. In step 902, a second semiconductor component (see, e.g., component 808 in fig. 8A) is held by a holding portion of a bonding tool of a bonding machine. The second semiconductor element includes a plurality of second conductive structures (e.g., located on a lower surface of the second semiconductor element). In step 904, the first conductive structure and the second conductive structure are aligned with each other (see, e.g., fig. 8A), and then brought into contact with each other (see, e.g., fig. 8B). In step 906, ultrasonic energy is applied to the second semiconductor element (such as in fig. 8B, by a bonding tool carrying the second semiconductor element) such that the conductive structure of the second semiconductor element is "initially" bonded (e.g., positionally bonded) to the conductive structure of the first semiconductor element as shown in fig. 8C (see positional bonds 828a and 828B).

Step 908A, step 908B, and step 908C are generally considered to be mutually replaceable herein. In step 908A, a flip chip (e.g., thermocompression) bonding process of the first conductive structure to the second conductive structure is completed one-by-one (by bonding the semiconductor elements one at a time) using the same bonding tool used in step 906. For example, referring to the example shown in fig. 8D, bonding tool 824 may be used to apply heat and/or pressure to form complete bonds 828a '(including further deformed conductive structures 806a "and 812 a") and 828b' (including further deformed conductive structures 806b "and 812 b").

As an alternative to step 908A, in step 908B, a flip-chip (e.g., thermocompression) bonding process of the first conductive structure to the second conductive structure is completed one-by-one (by bonding the semiconductor elements one at a time) using a different tool than the bonding tool used in step 906 (e.g., a different bonding tool on the same machine, a different bonding tool on a different machine). For example, referring again to the example shown in fig. 8D (where element 860 is supported by support structure 850 a), bonding tool 824a (including holding portion 810 a) may be used to apply heat and/or pressure to form completed bonds 828a '(including further deformed conductive structures 806a "and 812 a") and 828b' (including further deformed conductive structures 806b "and 812 b").

As an alternative to steps 908A, 908B, in step 908C, a flip-chip (e.g., thermal compression) bonding process of the first conductive structure to the second conductive structure is accomplished on a group basis (by simultaneously bonding multiple semiconductor elements) using a different tool than the bonding tool used in step 906 (e.g., a different bonding tool on the same machine, a different bonding tool on a different machine). For example, referring now to the example shown in fig. 8E, a bonding tool 875 (comprising a holding portion 877 to bond a plurality of semiconductor elements 808 to respective semiconductor elements 860) (wherein the elements 860 may be supported by a support structure 850 if on the same bonding machine 800, or the elements 860 may be supported on a support structure 879 if on a different bonding machine) may be used to apply heat and/or pressure to form a complete bond comprising further deformed pairs of conductive structures 806a 'a and 812a' a and 806b 'b and 812b' b.

Thus, by the options depicted in fig. 9 (and shown in fig. 8A-8E), various types of systems and methods for positioning and soldering (or positioning and cluster) bonding are described. Of course, further variations of forming an initial (locating) bond and subsequently forming a complete (final) bond are considered to be within the scope of the present invention. Certain variations of the systems and processes shown and described in connection with fig. 8A-8E and 9 (as well as other systems and processes within the scope of the invention) involve the use of non-conductive materials (e.g., pastes, epoxies, acrylates, silicones, bismaleimides, polyimides, polyesters, etc., or non-conductive films) disposed between the bonded together semiconductor elements. Such non-conductive materials may contain inorganic filler materials such as powders of silica or alumina. Fig. 10A-10E (and the flow chart in fig. 11), fig. 12A-12D (and the flow chart in fig. 13), and fig. 14A-14D (and the flow chart in fig. 15) illustrate examples of such systems and processes.

Referring specifically to fig. 10A, the upper semiconductor element 1008 is held by a holding portion 1010 of a bonding tool 1024 (e.g., by vacuum, such as through a vacuum port defined by a holding surface of the holding portion 1010). The upper semiconductor element 1008 includes upper conductive structures 1012a and 1012b (e.g., copper conductive structures such as copper pillars or other conductive structures) on a lower surface thereof. The lower semiconductor element 1060 includes a semiconductor die 1002 bonded to a substrate 1004 (or otherwise supported by the substrate 1004). For example, the substrate 1004 may be an organic substrate, a semiconductor wafer, a temporary support structure (e.g., a silicon, metal, or glass wafer or panel), and other substrates. In another example, the semiconductor die 1002 may be part of a semiconductor wafer, regardless of how the figures show a separate substrate 1004. Lower conductive structures 1006a and 1006b (e.g., copper conductive structures such as copper pillars or other conductive structures) are disposed on an upper surface of lower semiconductor die 1002. The substrate 1004 is in turn supported by a support structure 1050 (e.g., a heating block of the machine 1000, an anvil of the machine 1000, or any other desired support structure). Alternatively, the semiconductor die 1002 may still be part of a whole or part of a wafer directly supported by the support structure 1050 without any additional intervening substrate 1004. In the configuration shown in fig. 10A (ready for bonding), each of the upper conductive structures 1012a and 1012b is generally aligned with the opposing respective lower conductive structures 1006a and 1006 b. The semiconductor element 1008 is moved downward by the movement of the bonding tool 1024 (as indicated by arrow 1026 in fig. 10A). After this movement, fig. 10B shows the contact between the respective conductive structures 1006a and 1012a and 1006B and 1012B. Ultrasonic energy 1014 is applied to the upper semiconductor element 1008 and the upper conductive structures 1012a and 1012b by a bonding tool 1024 using an ultrasonic transducer (not shown, but represented in the figures as a "USG," i.e., an ultrasonic generator). For example, an ultrasonic transducer carrying bonding tool 1024 may in turn be carried by the bond head assembly of flip chip bonder 1000. During ultrasonic bonding, the lower conductive structures 1006a and 1006b may be held relatively stationary by the support provided to the lower semiconductor element 1060 by the support structure 1050 (e.g., the support surface of the support structure 1050 may include one or more vacuum ports to secure the substrate 1004 to the support structure 1050 during bonding). Ultrasonic energy 1014 (along with optional bonding forces and/or heat) may locally deform the conductive structure. For example, in fig. 10C, conductive structures 1006a 'and 1006B' and 1012a 'and 1012B' are shown deformed (or at least partially deformed) (as compared to fig. 10A-10B). In fig. 10C, initial (locating) ultrasonic bonds 1028a and 1028b are formed between respective pairs of conductive structures. For example, as shown in fig. 10C, an initial (e.g., locating) ultrasonic bond 1028a is formed between deformed conductive structures 1012a '/1006a' and an initial (e.g., locating) ultrasonic bond 1028b is formed between deformed conductive structures 1012b '/1006 b'.

After forming the initial (positioning) ultrasonic bond as shown in fig. 10C, as shown in fig. 10D, a non-conductive material 1040 (e.g., a non-conductive paste, an epoxy, an acrylate, a silicone, a bismaleimide, a polyimide, a polyester, or the like, wherein such a non-conductive material may include inorganic particles such as silica or alumina particles, or the like) is applied between the semiconductor element 1008 and the semiconductor element 1002. Depending on the material selected and other details of the application, material 1040 may be applied in any desired manner (e.g., as a fluid dispense, dispense using capillary underfill techniques, etc.). In fig. 10E, bonding of the first conductive structure to the second conductive structure has been completed (e.g., with heat, pressure, etc.) to form completed bonds 1028a '(including further deformed conductive structures 1006a "and 1012 a") and 1028b' (including further deformed conductive structures 1006b "and 1012 b"). In fig. 10E, the non-conductive material applied in fig. 10D has been cured to form a cured non-conductive material 1040'.

Referring specifically to fig. 11, in step 1100, a first semiconductor element (e.g., comprising a semiconductor die on a substrate, such as element 1060 shown in fig. 10A) is supported on a support structure of a bonding machine. The first semiconductor element (e.g., an upper surface of the semiconductor structure) includes a plurality of first conductive structures. In step 1102, a second semiconductor element (see, e.g., element 1008 in fig. 10A) is held by a holding portion of a bonding tool of a bonding machine. The second semiconductor element includes a plurality of second conductive structures (e.g., located on a lower surface of the second semiconductor element). In step 1104, the first conductive structure and the second conductive structure are aligned with each other (see, e.g., fig. 10A), and then brought into contact with each other (see, e.g., fig. 10B). In step 1106, ultrasonic energy is applied to the second semiconductor element (such as in fig. 10B, by a bonding tool carrying the second semiconductor element) such that the conductive structure of the second semiconductor element is "initially" bonded (e.g., positionally bonded) to the conductive structure of the first semiconductor element as shown in fig. 10C (see positional bonds 1028a and 1028B). In step 1108, a non-conductive material (see, e.g., material 1040 applied in fig. 10D) is applied between the first semiconductor element and the second semiconductor element. Flip chip and/or thermocompression bonding of the first and second conductive structures is accomplished (e.g., by applying heat and/or force) in step 1110, and the non-conductive material has been cured in step 1112 (see fig. 10E). As will be appreciated by those skilled in the art, step 1110 and step 1112 may be performed simultaneously, if desired.

Referring specifically to fig. 12A, the upper semiconductor element 1208 is held by a holding portion 1210 of a bonding tool 1224 (e.g., by vacuum, such as through a vacuum port defined by a holding surface of the holding portion 1210). The upper semiconductor element 1208 includes upper conductive structures 1212a and 1212b (e.g., copper conductive structures such as copper pillars or other conductive structures) on a lower surface thereof. The lower semiconductor element 1260 includes a semiconductor die 1202 bonded to a substrate 1204 (or otherwise supported by the substrate 1204). For example, the substrate 1204 may be an organic substrate, a semiconductor wafer, a temporary support structure (e.g., a silicon, metal, or glass wafer or panel), and other substrates. In another example, the semiconductor die 1202 may be part of a semiconductor wafer regardless of how the figures show a separate substrate 1204. Lower conductive structures 1206a and 1206b (e.g., copper conductive structures such as copper pillars or other conductive structures) are disposed on an upper surface of the lower semiconductor die 1202. The substrate 1204 is in turn supported by a support structure 1250 (e.g., a heating block of the machine 1200, an anvil of the machine 1200, or any other desired support structure). Alternatively, the semiconductor die 1202 may still be part of a whole or part of a wafer directly supported by the support structure 1250 without any additional intervening substrate 1204. In the configuration shown in fig. 12A (ready for bonding), each of the upper conductive structures 1212A and 1212b is generally aligned with the opposing corresponding lower conductive structure 1206a and 1206 b. As shown in fig. 12A, a non-conductive material 1240 is applied (e.g., a non-conductive paste, an epoxy, an acrylate, a silicone, a bismaleimide, a polyimide, a polyester, etc., where such non-conductive material may include inorganic particles such as silica or alumina particles, etc.) between the semiconductor element 1208 and the semiconductor element 1202 (in this example, the material 1240 is actually applied onto the semiconductor die 1202). Depending on the material selected and other details of the application, material 1240 may be applied in any desired manner (e.g., as a fluid dispense, dispense using capillary underfill techniques, etc.).

As shown in fig. 12A, semiconductor element 1208 is moved downward by the motion of bonding tool 1224 (as indicated by arrow 1226 in fig. 12A). This movement causes non-conductive material 1240 to be distributed between semiconductor element 1208 and semiconductor element 1260, including around 1206a and 1212a and 1206b and 1212b. After this movement, fig. 12B shows the contact between the respective conductive structures 1206a and 1212a and 1206B and 1212B. Ultrasonic energy 1214 is applied to the upper semiconductor element 1208 and the upper conductive structures 1212a and 1212b by a bonding tool 1224 using an ultrasonic transducer (not shown, but represented in the figures as a "USG", i.e., an ultrasonic generator). For example, the ultrasonic transducer carrying the bonding tool 1224 may in turn be carried by the bond head assembly of the flip chip bonding machine 1200. During ultrasonic bonding, the lower conductive structures 1206a and 1206b may be held relatively stationary by the support provided to the lower semiconductor element 1260 by the support structure 1250 (e.g., the support surface of the support structure 1250 may include one or more vacuum ports to secure the substrate 1204 to the support structure 1250 during bonding). Ultrasonic energy 1214 (along with optional bonding forces and/or heat) may locally deform the conductive structure. For example, in fig. 12C, conductive structures 1206a 'and 1206B' and 1212A 'and 1212B' are shown as deformed (or at least partially deformed) (as compared to fig. 12A-12B). In fig. 12C, initial (positioning) ultrasonic bonding portions 1228a and 1228b are formed between respective pairs of conductive structures. For example, as shown in fig. 12C, an initial (e.g., locating) ultrasonic bond 1228a is formed between deformed conductive structures 1212a '/1206a', and an initial (e.g., locating) ultrasonic bond 1228b is formed between deformed conductive structures 1212b '/1206 b'.

After the initial (positioning) ultrasonic bond as shown in fig. 12C is formed, in fig. 12D, bonding of the first conductive structure to the second conductive structure has been completed (e.g., with heat, pressure, etc.) to form full bonds 1228a '(including further deformed conductive structures 1206a "and 1212 a") and 1228b' (including further deformed conductive structures 1206b "and 1212 b"). In fig. 12D, the non-conductive material applied in fig. 12A has been cured to form a cured non-conductive material 1240'.

Referring specifically to fig. 13, in step 1300, a first semiconductor element (e.g., comprising a semiconductor die on a substrate, such as element 1360 shown in fig. 12A) is supported on a support structure of a bonding machine. The first semiconductor element (e.g., an upper surface of the semiconductor structure) includes a plurality of first conductive structures. In step 1302, a second semiconductor component (see, e.g., component 1308 in fig. 12A) is held by a holding portion of a bonding tool of a bonding machine. The second semiconductor element includes a plurality of second conductive structures (e.g., located on a lower surface of the second semiconductor element). In step 1304, a non-conductive material (see, e.g., material 1240 applied in fig. 12A) is applied between the first semiconductor element and the second semiconductor element. In step 1306, the first conductive structure and the second conductive structure are aligned with each other (see, e.g., fig. 12A), and then brought into contact with each other (see, e.g., fig. 12B). In step 1308, ultrasonic energy is applied to the second semiconductor element (such as in fig. 12B, by a bonding tool carrying the second semiconductor element) such that the conductive structure of the second semiconductor element is "initially" bonded (e.g., positionally bonded) to the conductive structure of the first semiconductor element as shown in fig. 12C (see positional bonds 1228a and 1228B). Flip chip and/or thermocompression bonding of the first and second conductive structures is accomplished (e.g., by applying heat and/or force) in step 1310, and the non-conductive material has been cured in step 1312 (see fig. 12D). As will be appreciated by those skilled in the art, step 1310 and step 1312 may be performed simultaneously, if desired.

Referring specifically to fig. 14A, the upper semiconductor element 1408 is held by a holding portion 1410 of a bonding tool 1424 (e.g., by vacuum, such as by a vacuum port defined by a holding surface of the holding portion 1410). The upper semiconductor element 1408 includes upper conductive structures 1412a and 1412b (e.g., copper conductive structures such as copper pillars or other conductive structures) on a lower surface thereof. The lower semiconductor element 1460 includes a semiconductor die 1402 bonded to the substrate 1404 (or otherwise supported by the substrate 1404). For example, the substrate 1404 may be an organic substrate, a semiconductor wafer, a temporary support structure (e.g., a silicon, metal, or glass wafer or panel), and other substrates. In another example, the semiconductor die 1402 may be part of a semiconductor wafer regardless of how the figures show a separate substrate 1404. Lower conductive structures 1406a and 1406b (e.g., copper conductive structures such as copper pillars or other conductive structures) are disposed on an upper surface of the lower semiconductor die 1402. The substrate 1404 is in turn supported by a support structure 1450 (e.g., a heating block of the machine 1400, an anvil of the machine 1400, or any other desired support structure). Alternatively, the semiconductor die 1402 may still be part of a whole or part of a wafer directly supported by the support structure 1450 without any additional intervening substrate 1404. In the configuration shown in fig. 14A (ready for bonding), each of the upper conductive structures 1412a and 1412b is generally aligned with the opposing respective lower conductive structures 1406a and 1406 b. As shown in fig. 14A, a non-conductive film 1440 (e.g., applied as a solid non-conductive film, etc.) is applied between the semiconductor element 1408 and the semiconductor element 1402 (in this example, the film 1440 is actually applied to the semiconductor die 1402).

As shown in fig. 14A, the semiconductor element 1408 is moved downward by movement of the bonding tool 1424 (as indicated by arrow 1426 in fig. 14A). This movement causes the non-conductive film 1440 to be distributed between the semiconductor element 1408 and the semiconductor element 1460, including around 1406a and 1412a and 1406b and 1412b. Following this movement, fig. 14B shows contact between the respective conductive structures 1406a and 1412a and 1406B and 1412B. Ultrasonic energy 1414 is applied to the upper semiconductor element 1408 and the upper conductive structures 1412a and 1412b by a bonding tool 1424 using an ultrasonic transducer (not shown, but represented in the figures as a "USG," i.e., an ultrasonic generator). For example, an ultrasonic transducer carrying bonding tool 1424 may in turn be carried by the bond head assembly of flip chip bonder 1400. During ultrasonic bonding, the lower conductive structures 1406a and 1406b may be held relatively stationary by the support provided to the lower semiconductor element 1460 by the support structure 1450 (e.g., the support surface of the support structure 1450 may include one or more vacuum ports to secure the substrate 1404 to the support structure 1450 during bonding). Ultrasonic energy 1414 (along with optional bonding forces and/or heat) may locally deform the conductive structure. For example, in fig. 14C, conductive structures 1406a 'and 1406B' and 1412a 'and 1412B' are shown as deformed (or at least partially deformed) (as compared to fig. 14A-14B). In fig. 14C, initial (positioning) ultrasonic bonding portions 1428a and 1428b are formed between respective pairs of conductive structures. For example, as shown in fig. 14C, an initial (e.g., positioning) ultrasonic bonding portion 1428a is formed between the deformed conductive structures 1412a '/1406a', and an initial (e.g., positioning) ultrasonic bonding portion 1428b is formed between the deformed conductive structures 1412b '/1406 b'.

After the initial (localized) ultrasonic bond illustrated in fig. 14C is formed, in fig. 14D, bonding of the first conductive structure to the second conductive structure has been completed (e.g., with heat, pressure, etc.) to form a full bond 1428a '(including further deformed conductive structures 1406a "and 1412 a") and 1428b' (including further deformed conductive structures 1406b "and 1412 b"). In fig. 14D, the non-conductive material applied in fig. 14A has been cured to form a cured non-conductive material 1440'.

Referring specifically to fig. 15, in step 1500, a first semiconductor element (e.g., comprising a semiconductor die on a substrate, such as element 1460 shown in fig. 14A) is supported on a support structure of a bonder. The first semiconductor element (e.g., an upper surface of the semiconductor structure) includes a plurality of first conductive structures. In step 1502, a second semiconductor component (see, e.g., component 1408 in fig. 14A) is held by a holding portion of a bonding tool of a bonding machine. The second semiconductor element includes a plurality of second conductive structures (e.g., located on a lower surface of the second semiconductor element). In step 1504, a non-conductive film (see, e.g., film 1440 applied in fig. 14A) is applied between the first semiconductor element and the second semiconductor element. In step 1506, the first and second conductive structures are aligned with each other (see, e.g., fig. 14A) and then brought into contact with each other (see, e.g., fig. 14B). In step 1508, ultrasonic energy is applied to the second semiconductor element (such as in fig. 14B, by a bonding tool carrying the second semiconductor element) such that the conductive structure of the second semiconductor element is "initially" bonded (e.g., positionally bonded) to the conductive structure of the first semiconductor element as shown in fig. 14C (see, positionally bonded portions 1428a and 1428B). In step 1510, flip chip and/or thermocompression bonding of the first and second conductive structures is completed (e.g., by applying heat and/or force), and in step 1512, the non-conductive film has been cured (see fig. 14D). As will be appreciated by those skilled in the art, step 1510 and step 1512 may be performed simultaneously, if desired.

Each of fig. 10A-10E, 12A-12D, and 14A-14D is shown as utilizing the original bonding tool to complete the initial (positional) ultrasonic bonding and subsequent full bonding steps. However, it should be understood that each of these embodiments (and the corresponding flowcharts shown in fig. 11, 13, and 15) may utilize different tools to accomplish the final bonding, wherein the different tools may be located on the same bonder or different bonders, and the different tools may bond the semiconductor elements one by one or in groups (e.g., as shown in fig. 8E). Each of the embodiments shown in fig. 8A-8E, 9, 10A-10E, 11, 12A-12D, 13, 14A-14D, 15 is particularly suitable for use in a positioning and group process (TACK AND GANG processes) in which the elements are first ultrasonically positioned bonded as individual elements (see, e.g., fig. 8C, 10C, 12C, 14C) and then group bonded (using a group bonding tool, such as tool 875 shown in fig. 8E) using heat and/or pressure to further deform the conductive structure into a final, fully bonded state. Such positioning and group processes are well suited for chip-to-wafer ("C2W") applications, i.e., ultrasonically positioning and bonding individual semiconductor die (chips) to a wafer using an ultrasonic bonding tool alone, followed by group bonding of a set of bonded die using a group bonding tool (e.g., using heat and/or pressure).

Multi-step bonding utilizes (i) an initial ultrasonic positional bonding process in which individual semiconductor elements (e.g., die) are positionally bonded using an ultrasonic bonding tool; subsequently utilizing (ii) a group bonding process wherein the plurality of semiconductor elements are subjected to a final bonding process (using a bonding tool with heat and/or pressure); such multi-step bonding is particularly suitable for bonding an upper copper conductive structure (located on an upper semiconductor element) to a lower copper conductive structure (located on a lower semiconductor element). The process of forming the final bond tends to involve heat treating the growth particles (grow gains) that cross the interface of the upper conductive structure and the lower conductive structure. Such processes tend to involve considerable time. Group bonding is particularly useful in order to provide efficient process yields (e.g., UPH or hourly yields). Thus, a relatively fast "positional" ultrasonic bonding process can be accomplished one semiconductor element at a time, while a relatively time-consuming "group" bonding process (involving heat and/or pressure) can be accomplished in a manner that bonds multiple semiconductor elements simultaneously.

Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.

Claims

1. A welding system, comprising:

a support structure for supporting a first semiconductor element, the first semiconductor element comprising a plurality of first conductive structures;

A bonding tool for carrying a second semiconductor element, the second semiconductor element comprising a plurality of second conductive structures, and the bonding tool applying ultrasonic energy to the second semiconductor element so as to form tack welds between each of the plurality of second conductive structures and a corresponding one of the plurality of first conductive structures, wherein a curable non-conductive material is applied between the first semiconductor element and the second semiconductor element prior to forming a completed weld between the first conductive structure and the second conductive structure.

2. The welding system of claim 1, wherein after forming the tack weld, the welding tool is configured to form a completed weld between each of the plurality of second conductive structures and a corresponding each of the plurality of first conductive structures.

3. The bonding system of claim 2, wherein the bonding tool is a heated bonding tool and the bonding tool applies heat to the second semiconductor element to form the finished bond.

4. The welding system of claim 1, further comprising a second welding tool, wherein after a tack weld is formed by the welding tool, the second welding tool is configured to form a completed weld between each of the plurality of second conductive structures and a corresponding each of the plurality of first conductive structures.

5. The bonding system of claim 4, wherein the second bonding tool is a heated bonding tool and the second bonding tool applies heat to a second semiconductor element for forming the finished bond.

6. The bonding system of claim 1, further comprising a group bonding tool, wherein after a tack weld is formed by the bonding tool, the group bonding tool is configured to form a completed bond between a plurality of first semiconductor elements and a corresponding plurality of second semiconductor elements.

7. The bonding system of claim 6, wherein the group bonding tool is a heated bonding tool and the group bonding tool applies heat to a second semiconductor element for forming the finished bond.

8. A method of soldering a semiconductor element using ultrasonic waves, the method comprising the steps of:

(a) Aligning surfaces of the plurality of first conductive structures of the first semiconductor element with corresponding surfaces of the plurality of second conductive structures of the second semiconductor element;

(b) Forming tack welds between each of the first conductive structures and respective ones of the second conductive structures using ultrasonic waves; and

(C) A completed weld between the first conductive structure and the second conductive structure is formed,

Wherein the method further comprises the step of applying a curable non-conductive material between the first semiconductor element and the second semiconductor element prior to step (c).

9. The method of claim 8, wherein the first semiconductor element is a semiconductor die.

10. The method of claim 8, wherein each of the first semiconductor element and the second semiconductor element is a respective semiconductor die.