CN118038801B - Low-power-consumption micro-display screen driving circuit suitable for multiple resolutions and driving method thereof - Google Patents
Low-power-consumption micro-display screen driving circuit suitable for multiple resolutions and driving method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuits, and discloses a low-power-consumption micro display screen driving circuit suitable for multiple resolutions and a driving method thereof, wherein the driving method comprises the following steps: the display control system comprises a first control signal unit C 1, a mapping operation unit, a second control signal unit C 2, a clock gating unit, a display data input register and a display data buffer; the device also comprises a gating signal rising edge pulse unit and a DFF clock control unit. The invention realizes the display of the multi-resolution image through the mapping operation unit, and even if the resolution of the display image is smaller than the actual physical resolution, the image can be displayed in a translation way, and the buffer for buffering one line of display data does not need to latch the data under the clock action all the time, only needs to latch the data once when the gating is finished, thereby greatly reducing the clock turnover times in the buffer and simultaneously reducing the power consumption of the buffer.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption micro display screen driving circuit suitable for multiple resolutions and a driving method thereof.
Background
Micro-display technology based on Micro-LEDs or Micro-OLEDs refers to display technology in which self-luminous Micro-scale LEDs or OLEDs are used as luminous pixel units, and the luminous pixel units are assembled on a driving panel to form a high-density LED array. The micro display chip has the advantages of small size, high integration level, self-luminescence and the like, and has the advantages of display brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like. Based on the above advantages, the micro display chip-based display device can be manufactured as a miniature and portable product, which allows the micro display chip-based display device to be applied to an AR or VR display device.
The driving circuit structure of the related art micro display panel as shown in fig. 1 includes n display data input registers of Q1 to Qn, which sequentially output input display data to a display data buffer to complete latching of one line of display data, for example. Each row of data corresponds to 640 pixels, n=8 display data input registers are set, and 8-bit data is transmitted each time, namely 8 pixel data are transmitted each time, so that the display data buffer is required to transmit 80 times of data, transmission of one row of display data is completed, and then one row of pixel data is latched and written into the corresponding row together to realize display.
As can be seen from the above-mentioned driving circuit structure, the first disadvantage of the prior art is that the display data buffer performs data refresh under the clock action before receiving a complete line of display data, and the data refresh is meaningless, which essentially only needs to perform data refresh after receiving a complete line of display data to latch a line of display data. The second aspect is that the existing driving circuit cannot be suitable for accurately displaying low-resolution image data, that is, when low-resolution display data is input through n display data input registers, the input of the display data is finished in advance due to the fact that the specified data quantity cannot be reached, so that abnormal display of the micro display screen is caused.
Accordingly, there is a need in the art for a micro-display driving circuit suitable for low-resolution image display in a low-power state and a driving method thereof.
Disclosure of Invention
The invention aims to provide a low-power consumption display screen driving circuit and a driving method thereof, which are suitable for multiple resolutions, wherein the micro display screen driving circuit and the driving method thereof can realize controllable display of images lower than actual physical pixels of a micro display screen on a preset area of the micro display screen.
Based on the technical purpose, the invention provides a low-power consumption micro display screen driving circuit suitable for multiple resolutions, which comprises a first control signal unit C 1, a mapping operation unit, a second control signal unit C 2, a clock gating unit, a display data input register and a display data buffer; the system also comprises a gating signal rising edge pulse unit and a DFF clock control unit;
The first control signal unit C 1 is configured by a plurality of D flip-flops arranged in sequence, and each D flip-flop outputs a first control signal, and the first control signal unit C 1 receives a rising edge pulse signal of the strobe signal, and the plurality of D flip-flops arranged in sequence outputs a plurality of first control signals C 1 (0) to C 1 (n);
The mapping operation unit receives the first control signals C 1 (0) to C 1 (n), and maps the first control signals C 1 (0) to C 1 (n) into a plurality of mapping signals M (0) to M (n) according to a display data panning scaling parameter;
After the second control signal unit C 2 receives the plurality of mapping signals M (0) to M (n), a plurality of second control signals C 2 (0) to C 2 (n) are generated according to the plurality of mapping signals M (0) to M (n);
the clock gating unit consists of a plurality of clock gating subunits, each clock gating subunit corresponds to a second control signal, the second control signals are used as enabling signals to be input into the clock gating subunits, and when the second control signals are effective signals, the clock gating subunits transmit clock signals of an input end to an output end;
The display data input register is composed of a plurality of register units Q (0) to Q (n), the input end of each register unit inputs data to be displayed, and the clock input end of each register unit is connected with a clock gating subunit in the corresponding clock gating unit; when a clock gating subunit in the clock gating unit inputs a clock signal to the register unit, the register unit inputs data to be displayed to the display data buffer;
The display data buffer is used for buffering one line of data information of the data to be displayed, and outputting the buffered data to be displayed after receiving the clock signal transmitted by the DFF clock control unit.
In one embodiment, the strobe signal rising edge pulse unit extracts a rising edge of the strobe signal and converts the rising edge of the strobe signal into a strobe signal rising edge pulse signal.
In one embodiment, the DFF clocking unit is configured to detect a falling edge of a strobe signal and output a clock signal to the display data buffer when the falling edge occurs.
In one embodiment, the display data pan scaling parameter includes a front-end mask value Q F and a back-end mask value Q E.
In one embodiment, the mapping rule executed by the mapping operation unit is: of the plurality of mapping signals M (0) to M (n), the mapping signals M (0) to M (Q F -1) and the mapping signals M (n-Q E +1) to M (n) are fixedly set to output 0; the remaining mapping signals M (i) are set as: m (i) =c 1(i-QF); wherein Q F≤i≤n-QE.
In one embodiment, the strobe signal rising edge pulse unit is composed of a D flip-flop, an or gate, and an and gate.
In one embodiment, the DFF clock unit is comprised of a first D flip-flop, an or gate, an and gate, at least one second D flip-flop, and clock gating.
The invention also provides a low-power consumption micro display screen driving method suitable for multiple resolutions, which comprises the following steps:
S100, converting a rising edge signal of a gating signal into a rising edge pulse signal;
S101, inputting a rising edge pulse signal into a first control signal unit C 1, where the first control signal unit C 1 outputs a plurality of first control signals C 1 (0) to C 1 (n);
S102, the mapping operation unit receives the first control signals C 1 (0) to C 1 (n), and maps the first control signals C 1 (0) to C 1 (n) into a plurality of mapping signals M (0) to M (n) according to display data translation scaling parameters;
S103, after the second control signal unit C 2 receives the mapping signals M (0) to M (n), generating a plurality of second control signals C 2 (0) to C 2 (n) according to the mapping signals M (0) to M (n);
s104, controlling whether to transmit a clock signal to a display data input register by the clock gating unit according to a plurality of second control signals C 2 (0) to C 2 (n);
s105, the display data input register outputs the display data to the display data buffer after receiving the clock signal;
and S106, the display data buffer latches one line of the buffered display data after receiving the clock signal.
In one embodiment, the clock signal received by the display data buffer is determined by the falling edge of the strobe signal.
One or more embodiments of the present invention may have the following advantages over the prior art:
1. In the invention, the mapping operation unit is utilized to realize the display of the multi-resolution image, the resolution of the timely displayed image is smaller than the actual physical resolution, and the image can be displayed in a translation way through the parameters related to the register.
2. In the invention, the buffer for buffering one line of display data does not need to latch data under the action of a clock all the time, and only needs to latch data once at the falling edge of the strobe signal, namely at the end of strobe. Therefore, the clock turnover frequency in the buffer memory is greatly reduced, and the power consumption of the buffer memory is reduced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art micro display column pixel driving circuit;
FIG. 2 is a block diagram of a micro-display panel row or column pixel driving circuit according to one embodiment of the present invention;
FIG. 3 is a block diagram of a micro-display row or column pixel drive circuit according to one embodiment of the invention;
FIG. 4 is a schematic circuit diagram of a mapping operation unit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a circuit structure of a strobe signal rising edge pulse unit according to an embodiment of the present invention;
FIG. 6 is a signal timing diagram of a strobe signal rising edge pulse unit according to an embodiment of the present invention;
Fig. 7 is a schematic circuit diagram of a DFF clock unit according to an embodiment of the invention;
Fig. 8 is a signal timing diagram of a DFF clock unit according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
As shown in fig. 2, the micro-display pixel driving circuit of the present invention includes a first control signal unit C 1, a mapping operation unit 2, a second control signal unit C 2, a clock gating unit 4, a display data input register 5, and a display data buffer 6.
The micro display screen pixel driving circuit of the present invention further comprises a strobe signal rising edge pulse unit 100 and a DFF clock control unit 600.
As shown in fig. 3, in the embodiment, the first control signal unit C 1 is formed by a plurality of D flip-flops arranged in sequence, and each D flip-flop outputs a first control signal, i.e., the ith D flip-flop outputs a first control signal C 1 (i), where the first control signal C 1 (0) is an original strobe signal rising edge pulse signal. After receiving the rising edge pulse signal of the strobe signal, the plurality of first control signals C 1 (0) to C 1 (n) output by the plurality of D flip-flops arranged in sequence sequentially output the rising edge pulse signal of the DE signal under the action of the clock signal.
The mapping operation unit 2 receives the first control signals C 1 (0) to C 1 (n), and maps them into a plurality of mapping signals M (0) to M (n). As shown in fig. 4, each mapping signal M (i) is correspondingly generated by one data selector output. The input of the data selector is the plurality of first control signals C 1 (0) to C 1 (n), and the enabling end signal of the data selection is controlled by the display data translation scaling parameter.
After the second control signal unit C 2 receives the plurality of mapping signals M (0) to M (n), a plurality of second control signals C 2 (0) to C 2 (n) are generated according to the plurality of mapping signals M (0) to M (n), and the generating process is that the mapping signals and the gating signals perform an and operation to generate corresponding second control signals, that is, M (i) & de=c 2 (i).
The clock gating unit 4 is composed of a plurality of clock gating subunits, each clock gating subunit corresponds to a second control signal, the second control signal is input into the clock gating subunit as an enabling signal, and when the second control signal is a valid signal, the clock gating subunit transmits a clock signal of an input end to an output end. The effective signal in this embodiment refers to a high level pulse signal corresponding to a rising edge pulse signal of the strobe signal.
The display data input register 5 is composed of a plurality of register units Q (0) to Q (n), the input ends of the register units input data to be displayed, and the clock input ends of the register units are connected with the clock gating sub-units in the corresponding clock gating units 4. That is, when the clock gating subunit in the clock gating unit 4 inputs a clock signal to the register unit Q (i), the register unit Q (i) can input data to be displayed to the display data buffer 6.
The display data buffer 6 is configured to buffer a line of data information of the data to be displayed, and output the buffered data to be displayed after receiving a clock signal transmitted by the DFF clock control unit.
In this embodiment, the mapping operation unit is configured to implement panning and zooming of a frame to be displayed, for example, when the micro display screen has X columns of actual physical pixels, and x=656. The resolution of the image data to be displayed is x columns of pixels, and x=632. When n is 82, that is, when the number of register units in the display data input register 5 is 82, it is known that the data of the image to be displayed output by each register unit is X/n bits. I.e. each register unit outputs 8bits of image data to be displayed, which corresponds to 8 columns of image data of pixels. According to the column number difference X-X between the actual physical pixel of the micro display screen and the pixel of the image to be displayed, a 24-column pixel difference exists between the actual pixel of the micro display screen and the pixel of the image to be displayed. I.e. if the image to be displayed is to be displayed using a micro-display screen, 24 columns of pixels need to be masked, whereas the 24 columns of pixels correspond to a number of register units of 24/8=3. Here, the display data pan scaling parameter should include at least two defined parameters, namely a front-end mask value Q F and a back-end mask value Q E. The front-end mask value Q F refers to the number of register units masked before the image to be displayed is actually displayed. The back-end mask value Q E refers to the number of register units masked after the image to be displayed completes the actual display. The present implementation can also be regarded as the number of physical pixel columns masked before the image to be displayed is actually displayed and after the display is completed. For example, in this embodiment, the front-end mask value Q F is set to 2, and the back-end mask value Q E is set to 1, that is, the outputs of two register units (16 columns of pixels) are masked before the image to be displayed is actually displayed, and the output of one register unit (8 columns of pixels) is masked after the image to be displayed is actually displayed. After determining the front-end mask value Q F and the back-end mask value Q E, the mapping rule executed by the mapping operation unit 2 is:
M(0)=0；
M(1)=0；
M(2)=C1(0)；
M(3)=C1(1)；
M(4)=C1(2)；
……
M(i)=C1(i-2)；
……
M(n-1)=C1(n-2)；
M(n)=0。
That is, among the plurality of mapping signals M (0) to M (n), the mapping signals M (0) to M (Q F -1), and the mapping signals M (n-Q E +1) to M (n) are fixedly set to output 0. The remaining mapping signals M (i) are set to M (i) =c 1(i-QF); or M (i) =c 1 (i-2); wherein Q F≤i≤n-QE.
According to the above mapping relationship, the pixel driving circuit in combination with the present embodiment can know that the register units corresponding to the front-end mask value Q F and the back-end mask value Q E cannot receive the clock signal transmitted by the clock gating unit, and thus cannot input the display data into the buffer.
As shown in fig. 5, the rising edge pulse unit 100 of the strobe signal extracts the rising edge of the strobe signal to convert the rising edge of the strobe signal into a corresponding pulse signal. In this embodiment, the strobe signal is an effective data strobe signal DE, i.e., a DE signal. The strobe signal rising edge pulse unit 100 is composed of a D flip-flop, an or gate, and an and gate. The gating signal is input into the input end triggered by the D trigger, the output end of the D trigger is connected with the OR gate, the output end of the OR gate and the gating signal are simultaneously input into the AND gate, and the output end of the AND gate outputs the gating signal rising edge pulse signal. The signal timing diagram of the strobe signal rising edge pulse unit 100 is shown in fig. 6.
As shown in fig. 7, the DFF clock control unit 600 in the present embodiment is configured to generate a clock signal for controlling the display data buffer 6 to latch data. The DFF clock unit 600 is comprised of a first D flip-flop, an or gate, an and gate, a second D flip-flop, and clock gates. The gate signal is input into the input end of the first D trigger and the input end of the OR gate, the output end of the first D trigger and the output end of the OR gate are connected with the two input ends of the AND gate, the output end of the AND gate outputs a falling edge pulse signal of the gate signal, and the falling edge pulse signal is input into the second D trigger and then is delayed to be output to the enabling end of clock gating. Whereby the DFF clock control unit 600 outputs a clock signal to said display data buffer 6 only when a falling edge pulse signal arrives. The signal timing diagram of the DFF clock control unit 600 is shown in fig. 8.
The embodiment also comprises a low-power consumption micro display screen driving method suitable for multiple resolutions, and the method comprises the following steps:
S100, converting a rising edge signal of a gating signal into a rising edge pulse signal;
S101, inputting a rising edge pulse signal into a first control signal unit C 1, where the first control signal unit C 1 outputs a plurality of first control signals C 1 (0) to C 1 (n);
S102, the mapping operation unit receives the first control signals C 1 (0) to C 1 (n), and maps the first control signals C 1 (0) to C 1 (n) into a plurality of mapping signals M (0) to M (n) according to display data translation scaling parameters;
S103, after the second control signal unit C 2 receives the mapping signals M (0) to M (n), generating a plurality of second control signals C 2 (0) to C 2 (n) according to the mapping signals M (0) to M (n);
s104, controlling whether to transmit a clock signal to a display data input register by the clock gating unit according to a plurality of second control signals C 2 (0) to C 2 (n);
s105, the display data input register outputs the display data to the display data buffer after receiving the clock signal;
And S106, the display data buffer latches the buffered display data of one row or one column after receiving the clock signal.
The present invention may be any possible integrated technology level system, method and/or computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to perform the various aspects of the invention.
A computer readable storage medium may be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device such as a punch card or a protrusion structure in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through a fiber optic cable), or an electrical signal transmitted through a wire.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a corresponding computing/processing device or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for performing operations of the present invention can be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer, partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may perform aspects of the invention by utilizing state information of computer-readable program instructions to execute the computer-readable program instructions to personalize the electronic circuitry.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus, to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, with some or all of the blocks being time-wise overlapped, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Claims (8)
1. A low power consumption micro display driving circuit suitable for multiple resolutions, the low power consumption micro display driving circuit comprising: the display control system comprises a first control signal unit C 1, a mapping operation unit, a second control signal unit C 2, a clock gating unit, a display data input register and a display data buffer; the system also comprises a gating signal rising edge pulse unit and a DFF clock control unit;
The first control signal unit C 1 is configured by a plurality of D flip-flops arranged in sequence, and each D flip-flop outputs a first control signal, and the first control signal unit C 1 receives a rising edge pulse signal of the strobe signal, and the plurality of D flip-flops arranged in sequence outputs a plurality of first control signals C 1 (0) to C 1 (n);
The mapping operation unit receives the first control signals C 1 (0) to C 1 (n), and maps the first control signals C 1 (0) to C 1 (n) into a plurality of mapping signals M (0) to M (n) according to a display data panning scaling parameter;
After the second control signal unit C 2 receives the plurality of mapping signals M (0) to M (n), a plurality of second control signals C 2 (0) to C 2 (n) are generated according to the plurality of mapping signals M (0) to M (n);
the clock gating unit consists of a plurality of clock gating subunits, each clock gating subunit corresponds to a second control signal, the second control signals are used as enabling signals to be input into the clock gating subunits, and when the second control signals are effective signals, the clock gating subunits transmit clock signals of an input end to an output end;
The display data input register is composed of a plurality of register units Q (0) to Q (n), the input end of each register unit inputs data to be displayed, and the clock input end of each register unit is connected with a clock gating subunit in the corresponding clock gating unit; when a clock gating subunit in the clock gating unit inputs a clock signal to the register unit, the register unit inputs data to be displayed to the display data buffer;
The display data buffer is used for buffering one line of data information of the data to be displayed, and outputting the buffered data to be displayed after receiving the clock signal transmitted by the DFF clock control unit;
The display data translation scaling parameters include a front-end mask value Q F and a back-end mask value Q E;
The mapping rule executed by the mapping operation unit is as follows: of the plurality of mapping signals M (0) to M (n), the mapping signals M (0) to M (Q F -1) and the mapping signals M (n-Q E +1) to M (n) are fixedly set to output 0; the remaining mapping signals M (i) are set as: m (i) =c 1(i-QF); wherein Q F≤i≤n-QE.
2. The low power consumption micro display screen driving circuit as claimed in claim 1, wherein the gate signal rising edge pulse unit extracts a rising edge of the gate signal and converts the rising edge of the gate signal into a gate signal rising edge pulse signal.
3. The low power consumption micro display screen driving circuit as claimed in claim 1, wherein the DFF clock control unit is configured to detect a falling edge of the strobe signal and output a clock signal to the display data buffer when the falling edge occurs.
4. The low power consumption micro display driving circuit as claimed in claim 1, wherein the gate signal rising edge pulse unit is composed of a D flip-flop, an or gate and an and gate.
5. The low power consumption micro-display screen driving circuit of claim 1, wherein the DFF clocking unit is comprised of a first D flip-flop, an or gate, an and gate, at least a second D flip-flop, and clock gating.
6. A low power consumption micro display driving method suitable for multi-resolution, the method comprising:
S100, converting a rising edge signal of a gating signal into a rising edge pulse signal;
S101, inputting a rising edge pulse signal into a first control signal unit C 1, where the first control signal unit C 1 outputs a plurality of first control signals C 1 (0) to C 1 (n);
S102, receiving the first control signals C 1 (0) to C 1 (n) by a mapping operation unit, and mapping the first control signals C 1 (0) to C 1 (n) into a plurality of mapping signals M (0) to M (n) according to a display data translation scaling parameter;
S103, after the second control signal unit C 2 receives the mapping signals M (0) to M (n), generating a plurality of second control signals C 2 (0) to C 2 (n) according to the mapping signals M (0) to M (n);
S104, controlling whether to transmit the clock signal to the display data input register by the clock gating unit according to a plurality of second control signals C 2 (0) to C 2 (n);
s105, the display data input register outputs the display data to the display data buffer after receiving the clock signal;
and S106, the display data buffer latches one line of the buffered display data after receiving the clock signal.
7. The method of claim 6, wherein the clock signal received by the display data buffer is determined by a falling edge of a strobe signal.
8. A micro display panel, wherein the micro display panel comprises the low power consumption micro display screen driving circuit according to any one of claims 1 to 5.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003255263A (en) * | 2001-12-25 | 2003-09-10 | Ricoh Co Ltd | Image display device and image display method |
| CN1992842A (en) * | 2005-12-30 | 2007-07-04 | 联发科技股份有限公司 | Luminance compensation apparatus and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003255263A (en) * | 2001-12-25 | 2003-09-10 | Ricoh Co Ltd | Image display device and image display method |
| CN1992842A (en) * | 2005-12-30 | 2007-07-04 | 联发科技股份有限公司 | Luminance compensation apparatus and method |
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