CN118036763A - Superconducting quantum chip expansion method and system and large-scale superconducting quantum chip - Google Patents
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Abstract
The invention relates to the technical field of superconducting quantum computing, in particular to a superconducting quantum chip expansion method, a superconducting quantum chip expansion system and a large-scale superconducting quantum chip, wherein the types and the numbers of the superconducting quantum chips to be expanded are determined according to the requirements of a modularized chip architecture; constructing an upper modularized single-chip structure to be interconnected in a two-dimensional array mode based on the superconducting quantum chip to be expanded; the method comprises the steps of arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to an upper modular single-chip structure, and carrying out expansion interconnection on quantum bits of superconducting quantum chips in the upper modular single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling so as to obtain a large-scale superconducting quantum chip. The invention can reduce the research and development time and cost of a new structure suitable for large-scale expansion of superconducting quantum chips while ensuring the performance of single chips, can be suitable for the expansion of any type and any scale of planar superconducting quantum chips, and has better application prospect in the field of superconducting quantum computation.
Description
Technical Field
The invention relates to the technical field of superconducting quantum computing, in particular to a superconducting quantum chip expansion method and system and a large-scale superconducting quantum chip.
Background
The superconducting quantum computer is a physical device for performing high-speed logic operation and quantum information processing based on quantum mechanics principles such as superposition, interference, entanglement and the like, and the operation speed of the superconducting quantum computer is even higher than that of classical calculation, so that the superconducting quantum computer becomes one of the most attractive research fields at present. One of the core challenges of current superconducting quantum computers is to expand the number of qubits of superconducting quantum chips without increasing noise or crosstalk, and to realize a large-scale number of qubits for application to practical and useful algorithms. However, the potential nonlinear expansion of physical resources and qubit numbers or chip sizes may hinder useful quantum advantages. The modular chip architecture scheme is the only viable method to extend to very large qubit numbers in a short period of time. Modular chip architecture is where smaller scale quantum chips are individually built and calibrated and then assembled into larger architectures using quantum coherent interconnects. However, achieving high quality interconnects while transporting fragile quantum states between different chips remains a significant challenge. Therefore, the expansion of high-fidelity interconnected large-scale superconducting quantum chips is of paramount importance. In the prior art, quantum multi-bit interactive design among multiple chips is realized by a modularized interconnection coupling technology, but research blank exists in large-scale chip-to-chip expansion interconnection.
Disclosure of Invention
Therefore, the invention provides a superconducting quantum chip expansion method, a superconducting quantum chip expansion system and a large-scale superconducting quantum chip, solves the problem of large-scale expansion and interconnection among superconducting quantum chips, ensures the performance of a single chip, and can be suitable for expansion of planar superconducting quantum chips in any scale.
According to the design scheme provided by the invention, in one aspect, a superconducting quantum chip expansion method is provided, which comprises the following steps:
Determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, wherein the superconducting quantum chips to be expanded adopt planar structures of superconducting quantum bits, reading resonant cavities, control lines and transmission lines on the same substrate;
Based on the superconducting quantum chip to be expanded, constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode;
and arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modular single-chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modular single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
As the superconducting quantum chip expansion method of the invention, further, determining the types and the number of the superconducting quantum chips to be expanded according to the requirements of the modularized chip architecture comprises the following steps:
And selecting a plurality of superconducting quantum chips of corresponding service types according to the modularized chip architecture requirements, wherein each superconducting quantum chip comprises a plurality of quantum bits.
As the superconducting quantum chip expansion method of the invention, further, based on the superconducting quantum chip to be expanded and in a two-dimensional array form, an upper layer modularized single chip structure to be interconnected is constructed, comprising:
and arranging and combining the superconducting quantum chips to be expanded in an M multiplied by N two-dimensional array form to form an upper-layer modularized single-chip structure to be interconnected, wherein M, N is a positive integer, and the total number of the superconducting quantum chips to be expanded is less than or equal to M multiplied by N.
As the superconducting quantum chip expansion method of the invention, further, the pin circuit of the lower carrier chip and the edge quantum bit coupling line distribution are arranged according to the upper modularized single chip structure, comprising the following steps:
Arranging a lower carrier chip pin circuit according to the pin distribution of the transmission line and the control line of the upper modular single chip structure, and enabling the transmission line and the superconducting welding column distribution structure of the control line of the upper modular single chip structure and the lower carrier chip to be consistent; and arranging the edge quantum bit coupling line distribution of the lower carrier chip according to the quantum bit distribution of the upper modular single-chip structure, and overlapping the coupling lines of the quantum bits of the upper modular single-chip structure and the lower carrier chip.
As the superconducting quantum chip expansion method of the invention, further, the expansion interconnection of the quantum bit in the upper modular single chip structure is carried out based on the lower carrier chip through the superconducting welding column and bit coupling, comprising the following steps:
two pins of a transmission line and a control line in the upper modularized single-chip structure are led to the lower carrier chip through the superconducting welding column, and quantum bits of adjacent superconducting quantum chips to be expanded of the upper modularized single-chip structure are connected through bit coupling between edge quantum bit coupling lines.
As the superconducting quantum chip expansion method, further, the bit coupling is capacitive coupling or resonant cavity coupling.
In yet another aspect, the present invention also provides a superconducting quantum chip expansion system, including: a selecting module, an arranging module and an expanding module, wherein,
The selection module is used for determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, wherein the superconducting quantum chips to be expanded adopt planar structures of superconducting quantum bits, reading resonant cavities, control lines and transmission lines on the same substrate;
the array module is used for constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode based on the superconducting quantum chip to be expanded;
The expansion module is used for arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modularized single-chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modularized single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
In yet another aspect, the present invention also provides a large-scale superconducting quantum chip, comprising: the upper layer modularized single chip and the lower layer carrier chip stacked with the upper layer modularized single chip are arranged and combined in a two-dimensional array mode by a plurality of superconducting quantum chips, and superconducting quantum chip quantum bits in the upper layer modularized single chip structure are expanded and interconnected through superconducting welding columns and bit coupling based on the lower layer carrier chip.
The invention has the beneficial effects that:
The invention takes the planar superconducting quantum chip as an upper modularized single chip to directly carry out interconnection expansion, can reduce the research and development time and cost of a new structure suitable for large-scale expansion of the superconducting quantum chip, can ensure the high performance of the single chip, and can be suitable for large-scale expansion of any type of planar superconducting quantum chip, such as a fixed-frequency superconducting quantum chip or a variable-frequency superconducting quantum chip; the method can be suitable for expanding planar superconducting quantum chips in any scale, can be assembled into a two-dimensional array form for interconnection according to requirements, so as to obtain the number of quantum bits required by superconducting quantum calculation, and has a good application prospect.
Description of the drawings:
FIG. 1 is a schematic flow of expansion of a superconducting quantum chip in an embodiment;
FIG. 2 is a schematic diagram of connection between upper and lower chips in the embodiment;
FIG. 3 is a schematic cross-section of an interconnection of upper and lower chips in an embodiment;
FIG. 4 is an edge bit coupling schematic in an embodiment;
Fig. 5 is a schematic illustration of the preparation process in the examples.
In the figure, reference numeral 11 denotes a single-chip transmission line/control line, reference numeral 12 denotes a single-chip coupling line, reference numeral 21 denotes a lower carrier chip transmission line/control line, reference numeral 22 denotes a lower carrier chip coupling line, and reference numeral 3 denotes a superconducting welding column.
The specific embodiment is as follows:
the present invention will be described in further detail with reference to the drawings and the technical scheme, in order to make the objects, technical schemes and advantages of the present invention more apparent.
Aiming at the problem of expansion among chips of the existing superconducting quantum chip, the embodiment of the invention provides a superconducting quantum chip expansion method, which is shown in fig. 1 and comprises the following steps:
S101, determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, wherein the superconducting quantum chips to be expanded adopt a planar structure in which superconducting quantum bits, a reading resonant cavity, a control line and a transmission line are all on the same substrate;
A plurality of superconducting quantum chips with corresponding service types can be selected according to the requirements of a modularized chip architecture, wherein each superconducting quantum chip comprises a plurality of quantum bits.
Selecting superconducting quantum chip types, such as superconducting quantum chips with fixed frequency or variable frequency and other planar structures, wherein the superconducting quantum chips with planar structures require superconducting quantum bits, reading resonant cavities, control lines, transmission lines and the like to be on the same substrate; and selecting a single chip with optimal performance and containing a certain number of quantum bits as a modularized single chip according to the preparation process limitation, wherein the modularized single chip is an upper-layer chip which can be finally prepared to obtain a large-scale expandable superconducting quantum chip and can be called as an upper-layer modularized single chip.
S102, constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode based on a superconducting quantum chip to be expanded;
According to the total number of the required quantum bits and the number of the quantum bits contained in the single chip, determining the number of upper-layer modularized single chips which need to be interconnected, and arranging and combining the superconducting quantum chips to be expanded in an M multiplied by N two-dimensional array form to form an upper-layer modularized single chip structure to be interconnected, wherein M, N is a positive integer, and the total number of the superconducting quantum chips to be expanded is less than or equal to M multiplied by N. The two-dimensional array formed by any number of superconducting quantum chips with planar structures can be interconnected and expanded.
S103, arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modularized single chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modularized single chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
The lower carrier chip pin circuit and the edge quantum bit coupling line distribution are arranged according to the upper modularized single chip structure, and can be designed to comprise the following contents:
Arranging a lower carrier chip pin circuit according to the pin distribution of the transmission line and the control line of the upper modular single chip structure, and enabling the transmission line and the superconducting welding column distribution structure of the control line of the upper modular single chip structure and the lower carrier chip to be consistent; and arranging the edge quantum bit coupling line distribution of the lower carrier chip according to the quantum bit distribution of the upper modular single-chip structure, and overlapping the coupling lines of the quantum bits of the upper modular single-chip structure and the lower carrier chip.
The method for expanding and interconnecting the quantum bits in the upper modular single chip structure based on the lower carrier chip through the superconducting welding column and bit coupling can comprise the following steps:
two pins of a transmission line and a control line in the upper modularized single-chip structure are led to the lower carrier chip through the superconducting welding column, and quantum bits of adjacent superconducting quantum chips to be expanded of the upper modularized single-chip structure are connected through bit coupling between edge quantum bit coupling lines. Wherein the bit coupling may be capacitive coupling or resonant cavity coupling.
The upper and lower chip interconnection parts can mainly comprise two types, namely a control line and a transmission line pin part, and the upper modularized single chip interconnection part is positioned at the upper layer when in expansion due to the limitation of a flip-chip bonding process, so that the circuit on the chip faces downwards, and therefore, the control line and the transmission line pin part cannot be directly connected to the packaging box through wire bonding. Therefore, the corresponding pin circuit distribution and structure on the lower carrier chip are defined according to the distribution and structure of the pins of the transmission line and the control line on the upper modularized single chip, and the pins of the transmission line and the control line on the upper modularized single chip are led out and interconnected to the lower carrier chip, so that the connection of the lead bonding to the packaging box is facilitated. The other type is a coupling line part between two chips which are required to be interconnected and correspond to interconnection edge quantum bits when the chips are expanded, the coupling line distribution and the structure which are required to be interconnected and correspond to the two-bit coupling of the edge quantum bits on the lower carrier chip and the upper modularized chip are defined according to the quantum bit distribution and the structure which are required to be interconnected between the upper modularized single chips, and the coupling can be direct capacitive coupling or resonant cavity coupling.
As shown in fig. 2, (a) for combining 4 selected superconducting quantum chips to be expanded into a 2 x 2 array form, the interconnection expansion is prepared, and because the circuit diagram on the chip is complex, the complete circuit is not drawn, and the circuits such as superconducting quantum bits, reading resonant cavities, control lines, transmission lines and the like are not drawn. Only the distribution and structure of control lines and transmission line pins, coupling lines and superconducting welding columns are shown. Only the coupled line portions of the edge qubits to be interconnected, and the corresponding control line and transmission line pin portions of the edge qubits, are shown on a single chip, substantially identical to (b) the underlying carrier chip, wherein two edge qubits are required to be interconnected with the edge qubits on an adjacent chip, and (b) the coupled line portions in (b) are transverse and longitudinal. One qubit corresponds to one control line and one transmission line. The control lines and the transmission lines are interconnected in the same way, and are not distinguished in the schematic diagram. The number of qubits on the upper modular single chip is selected according to the requirement, and only two edge qubit parts needing interconnection are shown in fig. 2, wherein a circular area in (a) represents the distribution and the structure of the superconducting welding columns.
In fig. 2, the transmission line and the control line lead part shown in (a) are overlapped with the corresponding circuit part in (b), the upper and lower chips can be connected by a flip-chip bonding process, and the chips shown in (c) can be obtained by connecting the upper and lower chips through superconducting solder columns. A cross-sectional view of the overlapping portion of the upper and lower chips corresponding to the lead portions of the transmission lines and control lines is shown in FIG. 3, and the lead portions of the transmission lines and control lines are shown in FIG. 3. The superconducting bond post distribution and structure of control and transmission lines on the upper modular chip and the lower carrier chip are identical, as shown in the cross-sectional view of the superconducting indium posts in fig. 3. The control wire and the transmission wire pins on the upper chip can be connected and led to the lower carrier chip through the superconducting welding columns, and circuit parts corresponding to the control wire and the transmission wire pins on the lower carrier chip can be just exposed, so that the lead bonding connection to the packaging box is facilitated. The other type is a coupling line part between two chips which are required to be interconnected and correspond to interconnection edge quantum bits when the chips are expanded, the coupling line distribution and the structure which are required to be interconnected and correspond to the two-bit coupling of the edge quantum bits on the lower carrier chip and the upper modularized chip are defined according to the quantum bit distribution and the structure which are required to be interconnected between the upper modularized single chips, and the coupling can be direct capacitive coupling or resonant cavity coupling. One end of the superconducting welding column is connected with a transmission line and a control line pin circuit part of the upper chip, and the other end is a circuit defined on the lower chip, and the circuit is used for leading the control line and the transmission line pin circuit part on the upper chip out and exposing the control line and the transmission line pin circuit part so as to be convenient for lead bonding connection to the packaging box.
In fig. 2, the coupling lines for realizing two-bit gates by connecting the upper edge qubits of two adjacent chips shown in (b) have overlapping parts with the corresponding coupling lines of (a), and the chips shown in (c) can be obtained by connecting the upper and lower chips by a flip-chip bonding process and connecting the upper and lower chips by superconducting welding columns. The cross-sectional view of the overlapping part of the upper chip and the lower chip corresponding to the coupling lines is shown in fig. 3, the pattern shown in fig. 3 is provided with the coupling line parts, and the upper chip and the lower chip are connected through the superconducting welding columns. The superconducting bond posts of the coupling lines on the upper modular chip and the lower carrier chip are distributed and structured in accordance with the cross-sectional view of the superconducting bond posts shown in fig. 3. The coupling lines on the upper and lower chips can be connected and conducted through the superconducting welding columns, and the edge quantum bits on the two adjacent chips can be coupled through the coupling lines. Finally, the interconnected large-scale superconducting quantum chips can be realized. The coupling can be direct capacitive coupling or resonant cavity coupling when realizing two-chip edge qubit two-bit coupling interconnection, as shown in fig. 4. One end of the superconducting welding column is one end of a coupling line extending out of a plate capacitor in a quantum bit of an upper chip, and the other end of the superconducting welding column is one end of a coupling line circuit defined on a lower chip, wherein the fixed-frequency quantum bit is generally composed of a Josephson junction and the plate capacitor.
Referring to fig. 5, in a specific preparation, the upper modular single chip and the lower carrier chip may be prepared by a metal thin film deposition process, a photolithography process, an etching process, a lift-off process, a dual dip coating process, and an oxidation process. The large circuit material can be Al or Ta, and the Josephson junction can be a commonly used Al/AlO x/Al material structure. The flip chip technology is a technology for vertically interconnecting circuits on an upper chip and a lower chip through a welding column under a certain pressure and temperature. Before preparation, the distribution and structure of the superconducting welding columns are defined according to the distribution and structure of the interconnection areas required by the upper chip and the lower chip. The superconducting bond post is typically a cylindrical bond post of 10-100 microns diameter. Then the pattern of the superconducting welding column is defined by adopting the photoetching technology, then the pre-defined height of the superconducting welding column is deposited by utilizing the thermal evaporation coating equipment, the photoresist is melted by the developing solution, the film of the superconducting welding column connected with the photoresist is removed (the stripping process) and the remained undissolved part forms a series of superconducting welding columns. The height of the superconducting bond posts is typically 1-10 microns. The materials of the superconducting welding column can be selected from In, tiN/In/TiN material structures and the like, and good electrical performance of the superconducting welding column needs to be ensured. In the preparation and connection process, the superconducting welding column is carefully treated, an oxide layer on the surface of the superconducting welding column is removed, and good superconducting connection between the upper chip and the lower chip is ensured. The areas of the circuits on the upper chip and the lower chip, which need to be interconnected, are electrically connected through the superconducting welding columns, so that the preparation and the treatment of the superconducting welding columns are strictly ensured, and good superconducting connection between the upper chip and the lower chip is ensured. And the superconducting welding column is lossless after being superconducting, so that the performance of the chip can be ensured by interconnecting the chips through the superconducting welding column.
Further, based on the above method, the embodiment of the present invention further provides a superconducting quantum chip expansion system, including: a selecting module, an arranging module and an expanding module, wherein,
The selection module is used for determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, wherein the superconducting quantum chips to be expanded adopt planar structures of superconducting quantum bits, reading resonant cavities, control lines and transmission lines on the same substrate;
the array module is used for constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode based on the superconducting quantum chip to be expanded;
The expansion module is used for arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modularized single-chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modularized single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
Further, based on the above method, the embodiment of the present invention further provides a large-scale superconducting quantum chip, including: the upper layer modularized single chip and the lower layer carrier chip stacked with the upper layer modularized single chip are arranged and combined in a two-dimensional array mode by a plurality of superconducting quantum chips, and superconducting quantum chip quantum bits in the upper layer modularized single chip structure are expanded and interconnected through superconducting welding columns and bit coupling based on the lower layer carrier chip.
The relative steps, numerical expressions and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The elements and method steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or a combination thereof, and the elements and steps of the examples have been generally described in terms of functionality in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different methods for each particular application, but such implementation is not considered to be beyond the scope of the present invention.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the above methods may be performed by a program that instructs associated hardware, and that the program may be stored on a computer readable storage medium, such as: read-only memory, magnetic or optical disk, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits, and accordingly, each module/unit in the above embodiments may be implemented in hardware or may be implemented in a software functional module. The present invention is not limited to any specific form of combination of hardware and software.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A superconducting quantum chip expansion method, comprising:
Determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, wherein the superconducting quantum chips to be expanded adopt planar structures of superconducting quantum bits, reading resonant cavities, control lines and transmission lines on the same substrate;
Based on the superconducting quantum chip to be expanded, constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode;
and arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modular single-chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modular single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
2. The method of claim 1, wherein determining the type and number of superconducting quantum chips to be expanded based on modular chip architecture requirements comprises:
And selecting a plurality of superconducting quantum chips of corresponding service types according to the modularized chip architecture requirements, wherein each superconducting quantum chip comprises a plurality of quantum bits.
3. The method of expanding superconducting quantum chips according to claim 1, wherein the constructing of the upper modular single chip structure to be interconnected in a two-dimensional array based on the superconducting quantum chips to be expanded comprises:
and arranging and combining the superconducting quantum chips to be expanded in an M multiplied by N two-dimensional array form to form an upper-layer modularized single-chip structure to be interconnected, wherein M, N is a positive integer, and the total number of the superconducting quantum chips to be expanded is less than or equal to M multiplied by N.
4. The method of claim 1, wherein the step of providing the lower carrier chip pin circuit and edge qubit coupled line distribution according to the upper modular single chip structure comprises:
Arranging a lower carrier chip pin circuit according to the pin distribution of the transmission line and the control line of the upper modular single chip structure, and enabling the transmission line and the superconducting welding column distribution structure of the control line of the upper modular single chip structure and the lower carrier chip to be consistent; and arranging the edge quantum bit coupling line distribution of the lower carrier chip according to the quantum bit distribution of the upper modular single-chip structure, and overlapping the coupling lines of the quantum bits of the upper modular single-chip structure and the lower carrier chip.
5. The method of claim 1, wherein expanding and interconnecting the qubits in the upper modular single chip structure based on the lower carrier chip and through the superconducting bond post and bit coupling comprises:
two pins of a transmission line and a control line in the upper modularized single-chip structure are led to the lower carrier chip through the superconducting welding column, and quantum bits of adjacent superconducting quantum chips to be expanded of the upper modularized single-chip structure are connected through bit coupling between edge quantum bit coupling lines.
6. The superconducting quantum chip expansion method according to claim 1 or 5, wherein the bit coupling is capacitive coupling or resonant cavity coupling.
7. A superconducting quantum chip expansion system, comprising: the device comprises a selection module, an arrangement module and an expansion module, wherein the selection module is used for determining the types and the quantity of superconducting quantum chips to be expanded according to the requirements of a modularized chip architecture, and the superconducting quantum chips to be expanded adopt planar structures of superconducting quantum bits, reading resonant cavities, control lines and transmission lines on the same substrate;
the array module is used for constructing an upper-layer modularized single-chip structure to be interconnected in a two-dimensional array mode based on the superconducting quantum chip to be expanded;
The expansion module is used for arranging a lower carrier chip pin circuit and edge quantum bit coupling line distribution according to the upper modularized single-chip structure, and expanding and interconnecting quantum bits of the superconducting quantum chips in the upper modularized single-chip structure based on the lower carrier chip through superconducting welding columns and bit coupling.
8. A large scale superconducting quantum chip, comprising: the upper layer modularized single chip and the lower layer carrier chip stacked with the upper layer modularized single chip are arranged and combined in a two-dimensional array mode by a plurality of superconducting quantum chips, and superconducting quantum chip quantum bits in the upper layer modularized single chip structure are expanded and interconnected through superconducting welding columns and bit coupling based on the lower layer carrier chip.
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