CN118036760A - Method and device for adjusting two-quantum bit logic gate and quantum computer - Google Patents
Method and device for adjusting two-quantum bit logic gate and quantum computer Download PDFInfo
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Abstract
The application discloses a method and a device for adjusting a two-quantum bit logic gate, and a quantum computer. And then, obtaining a first test value of the conditional phase of the two-quantum bit logic gate according to the result of the two Ramsey experiments. And finally, judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition. According to the scheme, the result of the Ramsey experiment is utilized to obtain the test value of the conditional phase of the two-quantum bit logic gate, and the magnitude of the conditional phase can be effectively adjusted according to the test value so as to meet the requirement, so that the blank of the prior art is made up.
Description
Technical Field
The invention relates to the technical field of quantum computing, in particular to a method and a device for adjusting a two-quantum bit logic gate and a quantum computer.
Background
Quantum computation and quantum information are a cross subject for realizing computation and information processing tasks based on the principle of quantum mechanics, and have very close connection with subjects such as quantum physics, computer science, informatics and the like. There has been a rapid development in the last two decades. Quantum computer-based quantum algorithms in factorization, unstructured search, etc. scenarios exhibit far beyond the performance of existing classical computer-based algorithms, and this direction is expected to be beyond the existing computing power. Since quantum computing has a potential to solve specific problems far beyond the development of classical computer performance, in order to realize a quantum computer, it is necessary to obtain a quantum chip containing a sufficient number and a sufficient mass of qubits, and to enable quantum logic gate operation and reading of the qubits with extremely high fidelity. The quantum chip is the core component of the quantum computer, and the quantum chip is the processor for executing quantum computation. Before each quantum chip is formally used on line, each parameter of the quantum bit in the quantum chip needs to be tested and characterized.
Similar to classical bits, in performing quantum computation with qubits, it is inevitably necessary to apply a qubit logic gate to the qubits, for which the qubit logic gate actually refers to a series of regulatory signals for which the accuracy of the parameters is important. The qubit logic gate mainly comprises two types of single-qubit logic gates and two-qubit logic gates, wherein the two-qubit logic gates comprise a CNOT gate, a SWAP gate, a CZ gate and the like, and the condition phase of the two-qubit logic gate is an important parameter. Taking the CZ gate as an example, a single bit phase is generated during the process of adjusting the qubit frequency, and for a qubit, the process of adjusting the qubit from the working point to the two-bit resonance point and returning to the initial position can be written as follows:
Wherein phi A and phi B are respectively single bit phases generated by two bits, and the CZ gate is realized when the single bit phases in the matrix are eliminated by the following steps:
Where Φ=Φ AB-φA-φB, which is the conditional phase, the ideal case for a CZ gate is that the conditional phase is equal to pi. However, in actual operation, it is only possible to determine whether the condition phase of the CZ gate satisfies the requirement by the specific execution result.
Therefore, it is becoming an urgent problem in the art to propose a scheme that can effectively adjust the conditional phase of the two-qubit logic gate.
It should be noted that the information disclosed in the background section of the present application is only for enhancement of understanding of the general background of the present application and should not be taken as an admission or any form of suggestion that this information forms the prior art already known to those skilled in the art.
Disclosure of Invention
The invention aims to provide a method and a device for adjusting a two-quantum bit logic gate and a quantum computer, which are used for solving the problem that a scheme capable of effectively adjusting the conditional phases of the two-quantum bit logic gate is lacking in the prior art.
In order to solve the above technical problems, the present invention provides a method for adjusting a two-qubit logic gate, including:
executing two-quantum bit logic gates on a first quantum bit and a second quantum bit, and executing two-time Ramsey experiments on the second quantum bit, wherein the first quantum bit is respectively in a first selected eigenstate and a second selected eigenstate in the two-time Ramsey experiments, and the first quantum bit and the second quantum bit are two quantum bits directly coupled in a quantum chip;
Based on the results of the two Ramsey experiments, acquiring a first test value of the conditional phase of the two-quantum bit logic gate;
and judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition.
Optionally, the obtaining the first test value of the conditional phase of the two-qubit logic gate based on the results of the two Ramsey experiments includes:
respectively obtaining oscillation curves in experimental results of each Ramsey experiment;
and acquiring a first test value of the conditional phase based on the phase difference value of the oscillation curve in the two experimental results.
Optionally, the first test value is a phase difference value of an oscillation curve in the results of two experiments.
Optionally, the determining whether the parameters of the two-qubit logic gate are adjusted based on whether the first test value meets a preset condition includes:
Judging whether the first test value is a first preset value or not;
if not, the parameters of the two-quantum bit logic gate are adjusted, the two-quantum bit logic gate is executed on the first quantum bit and the second quantum bit in a return mode, and the Ramsey experiment is executed on the second quantum bit twice;
if yes, the adjustment of the two-quantum bit logic gate is completed.
Optionally, the parameters of the two-qubit logic gate include an amplitude and a duration.
Optionally, the first preset value is pi.
Optionally, the quantum chip further includes a third qubit, the third qubit being in a direct coupling relationship with the first qubit but not with the second qubit;
the adjustment method further comprises the following steps:
executing the two-qubit logic gate on the first qubit and the second qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate, and executing the Ramsey experiment on the second qubit twice;
Respectively obtaining first test values of the conditional phases of the two-qubit logic gates corresponding to the third qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate;
And acquiring the conditional phase difference of the two-qubit logic gate based on the acquired difference value of the two first test values.
Optionally, the adjusting method further includes:
and adjusting the conditional phase of the two-qubit logic gate by using the acquired conditional phase difference.
Optionally, the number of the third qubits is a plurality;
the adjustment method further comprises the following steps:
respectively obtaining a conditional phase difference corresponding to each third quantum bit;
and adjusting the conditional phase of the qubit logic gate by using the acquired plurality of conditional phase differences.
Optionally, the adjusting the conditional phase of the qubit logic gate using the acquired plurality of conditional phase differences includes:
acquiring a sum of the plurality of conditional phase differences;
And adjusting the conditional phase of the qubit logic gate by using the sum value.
Based on the same inventive concept, the invention also provides an adjusting device of the two-quantum bit logic gate, which comprises:
an experiment execution unit configured to execute a two-qubit logic gate on a first qubit and a second qubit, and execute a two-time Ramsey experiment on the second qubit, in which the first qubit is in a first selected eigenstate and a second selected eigenstate, respectively, wherein the first qubit and the second qubit are two qubits directly coupled in a quantum chip;
A conditional phase acquisition unit configured to acquire a first test value of a conditional phase of the two-qubit logic gate based on a result of two Ramsey experiments;
and the adjusting unit is configured to judge whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition.
Based on the same inventive concept, the invention also provides a quantum control system, which utilizes the adjusting method of the two-quantum bit logic gate described in any one of the above feature descriptions to adjust the two-quantum bit logic gate, or comprises the adjusting device of the two-quantum bit logic gate described in the above feature descriptions.
Based on the same inventive concept, the invention also provides a quantum computer, which comprises the quantum control system described in the above characteristic description.
Based on the same inventive concept, the present invention also proposes a readable storage medium having stored thereon a computer program which, when executed by a processor, is capable of implementing the method for adjusting a two-qubit logic gate according to any of the above-mentioned feature descriptions.
Compared with the prior art, the invention has the following beneficial effects:
1. The application provides a method for adjusting a two-quantum bit logic gate, which comprises the steps of firstly executing the two-quantum bit logic gate on a first quantum bit and a second quantum bit, and executing Ramsey experiments on the second quantum bit twice, wherein in the Ramsey experiments, the first quantum bit is respectively in a first selected eigenstate and a second selected eigenstate. And then, obtaining a first test value of the conditional phase of the two-quantum bit logic gate according to the result of the two Ramsey experiments. And finally, judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition. According to the scheme, the result of the Ramsey experiment is utilized to obtain the test value of the conditional phase of the two-quantum bit logic gate, and the magnitude of the conditional phase can be effectively adjusted according to the test value so as to meet the requirement, so that the blank of the prior art is made up.
2. When two qubits on a quantum chip are used for making a two-qubit logic gate, any other adjacent qubit with a dispersion coupling effect with the two qubits can influence the resonance condition of the two-qubit logic gate to a certain extent, and the adjacent qubit and the dispersion coupling of the qubit used for executing the two-qubit logic gate cause energy level shift of the two qubits, so that the condition phase change of the CZ gate is indirectly influenced, and the fidelity is reduced, so that the fidelity of the two-qubit logic gate is reduced. The application further provides a scheme capable of acquiring the conditional phase difference, and the fidelity of the two-quantum logic gate can be effectively improved.
The adjusting device, the quantum control system, the quantum computer and the readable storage medium of the two-quantum bit logic gate provided by the invention belong to the same invention conception as the adjusting method of the two-quantum bit logic gate, so that the adjusting device has the same beneficial effects and is not repeated herein.
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Fig. 1 is a flow chart of a method for adjusting a two-qubit logic gate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an adjusting device for a two-qubit logic gate according to another embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In order to better understand the technical scheme of the application, the Ramsey experiment related to the application is briefly described below:
The Ramsey experiment refers to a process of applying two pi/2 quantum logic gate operations to one qubit with a time interval τ while applying a read pulse to the qubit after the second pi/2 quantum logic gate operation to obtain an excited state distribution P 1 (τ) of the qubit, and changing the time interval τ to obtain P 1 (τ). The result of a typical Ramsey experiment is that P 1 (τ) is a mathematical model that satisfies the exponential oscillation decay over time interval τ as follows:
In formula 1, a and B are fitting coefficients, T 0 is decoherence time of a quantum bit, f d is carrier frequency of a microwave pulse signal corresponding to pi/2 quantum logic gate operation, f 0 is oscillation frequency of the quantum bit, and f 0 and real frequencies f q of the quantum bit, carrier frequency of pi/2 quantum logic gate operation satisfy:
f0(fd)＝|fq-fd| (2)
From the above, in combination with equation 2, we can get: the result of the Ramsey experiment, namely the oscillation frequency of the curve is equal to the difference between the carrier frequency of the quantum logic gate operation and the real frequency of the quantum bit, so that the Ramsey experiment can be used for obtaining the decoherence time of the quantum bit and can also accurately obtain the real frequency of the quantum bit.
The core idea of the application is that the phase of the oscillation curve in the experimental result of the Ramsey experiment is utilized, the current condition phase of the two-quantum bit logic gate can be directly obtained through the phase difference value of the oscillation curve in the experimental result of the Ramsey experiment, and whether the parameters of the two-quantum bit logic gate meet the requirements is further judged.
Referring to fig. 1, an embodiment of the present application provides a method for adjusting a two-qubit logic gate, including:
S100: executing two-quantum bit logic gates on a first quantum bit and a second quantum bit, and executing two-time Ramsey experiments on the second quantum bit, wherein the first quantum bit is respectively in a first selected eigenstate and a second selected eigenstate in the two-time Ramsey experiments, and the first quantum bit and the second quantum bit are two quantum bits directly coupled in a quantum chip;
s200: based on the results of the two Ramsey experiments, acquiring a first test value of the conditional phase of the two-quantum bit logic gate;
s300: and judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition.
The difference from the prior art is that the two-qubit logic gate adjustment method provided in this embodiment first executes two-qubit logic gates on a first qubit and a second qubit, and executes two-time Ramsey experiments on the second qubit, where the first qubit is in a first selected eigenstate and a second selected eigenstate respectively. And then based on the results of the two Ramsey experiments, acquiring a first test value of the conditional phase of the two-quantum bit logic gate. And finally, judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition. In the scheme of the embodiment, the result of the Ramsey experiment is utilized to obtain the test value of the conditional phase of the two-quantum bit logic gate, and the magnitude of the conditional phase can be effectively adjusted according to the test value to meet the requirement, so that the blank of the prior art is made up.
It will be appreciated by those skilled in the art that the first selected eigenstate and the second selected eigenstate may be either of the |1> state or the |0> state. The results of the two Ramsey experiments mentioned in step S200 actually refer to oscillation curves in the experimental results of the Ramsey experiments, and the current condition phase value of the two-qubit logic gate can be obtained through the phase difference value of the two oscillation curves.
Specifically, in this embodiment, the obtaining the first test value of the conditional phase of the two-qubit logic gate based on the results of the two Ramsey experiments, that is, the step S200 may specifically include:
respectively obtaining oscillation curves in experimental results of each Ramsey experiment;
and acquiring a first test value of the conditional phase based on the phase difference value of the oscillation curve in the two experimental results.
In this embodiment, the first test value is a phase difference value of an oscillation curve in the results of two experiments.
Specifically, in this embodiment, the determining whether the parameters of the two-qubit logic gate are adjusted based on whether the first test value meets a preset condition, that is, the step S300 may specifically include:
Judging whether the first test value is a first preset value or not;
if not, the parameters of the two-quantum bit logic gate are adjusted, the two-quantum bit logic gate is executed on the first quantum bit and the second quantum bit in a return mode, and the Ramsey experiment is executed on the second quantum bit twice;
if yes, the adjustment of the two-quantum bit logic gate is completed.
In this embodiment, the parameters of the two-qubit logic gate include an amplitude and a duration. The two-qubit logic gate includes, but is not limited to, a CNOT gate, a SWAP gate, and a CZ gate, and in this embodiment, the two-qubit logic gate is a CZ gate, and the first preset value is set to pi.
When two qubits on a quantum chip are used for making a two-qubit logic gate, any other adjacent qubit with a dispersion coupling effect with the two qubits can influence the resonance condition of the two-qubit logic gate to a certain extent, and the adjacent qubit and the dispersion coupling of the qubit used for executing the two-qubit logic gate cause energy level shift of the two qubits, so that the condition phase change of the CZ gate is indirectly influenced, and the fidelity is reduced, so that the fidelity of the two-qubit logic gate is reduced. In order to solve the problem, the embodiment further provides a scheme capable of acquiring the conditional phase difference, and the fidelity of the two-quantum logic gate can be effectively improved. Specifically, the quantum chip further comprises a third qubit, wherein the third qubit has a direct coupling relation with the first qubit but has no direct coupling relation with the second qubit;
the adjustment method further comprises the following steps:
executing the two-qubit logic gate on the first qubit and the second qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate, and executing the Ramsey experiment on the second qubit twice;
Respectively obtaining first test values of the conditional phases of the two-qubit logic gates corresponding to the third qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate;
And acquiring the conditional phase difference of the two-qubit logic gate based on the acquired difference value of the two first test values.
By respectively acquiring the conditional phases of the two-qubit logic gate when the third qubit is in the |1> state and the |0> state, the energy level shift influence of the third qubit in the |1> state on the first qubit and the second qubit can be acquired, and further the influence on the conditional phases of the CZ gate can be acquired. After the conditional phase difference is obtained, the value of the conditional phase of the qubit logic gate under the influence of the third qubit interference can be adjusted by using the conditional phase difference feedback, so that the assurance of executing two qubit logic gates in a quantum chip is improved.
Specifically, in this embodiment, the adjustment method further includes:
and adjusting the conditional phase of the two-qubit logic gate by using the acquired conditional phase difference.
Alternatively, in practical applications, the number of the third qubits may be more than one, and there may be two, three or even more, that is, the number of the third qubits is plural;
the adjustment method further comprises the following steps:
respectively obtaining a conditional phase difference corresponding to each third quantum bit;
and adjusting the conditional phase of the qubit logic gate by using the acquired plurality of conditional phase differences.
In fact the bits on a chip are far more complex than we have exemplified, one quantum chip will have more than one third quantum bit when performing a two-quantum bit logic gate. In practice, therefore, we need to consider a greater number of third qubits, but the total phase difference corresponds to the sum of all the individual resulting errors. Specifically, the adjusting the conditional phase of the qubit logic gate by using the acquired plurality of conditional phase differences includes:
acquiring a sum of the plurality of conditional phase differences;
And adjusting the conditional phase of the qubit logic gate by using the sum value.
Based on the same inventive concept, please refer to fig. 2, an embodiment of the present application further provides an adjusting device for a two-qubit logic gate, which includes:
An experiment execution unit 100 configured to perform a two-qubit logic gate on a first qubit and a second qubit, and perform a two-time Ramsey experiment on the second qubit in which the first qubit is in a first selected eigenstate and a second selected eigenstate, respectively, wherein the first qubit and the second qubit are two qubits directly coupled in a quantum chip;
A conditional phase acquisition unit 200 configured to acquire a first test value of a conditional phase of the two-qubit logic gate based on a result of two Ramsey experiments;
And an adjusting unit 300 configured to determine whether the parameters of the two-qubit logic gate are adjusted based on whether the first test value satisfies a preset condition.
It is understood that the experiment performing unit 100, the condition phase acquiring unit 200 and the adjusting unit 300 may be combined in one device to be implemented, or any one of the modules may be split into a plurality of sub-modules, or at least part of the functions of one or more of the experiment performing unit 100, the condition phase acquiring unit 200 and the adjusting unit 300 may be combined with at least part of the functions of the other modules and implemented in one functional module. According to an embodiment of the present invention, at least one of the experiment execution unit 100, the condition phase acquisition unit 200, and the adjustment unit 300 may be implemented at least partially as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or any other reasonable way of integrating or packaging a circuit, or as hardware or firmware, or as a suitable combination of three implementations of software, hardware, and firmware. Or at least one of the experiment execution unit 100, the condition phase acquisition unit 200, and the adjustment unit 300 may be at least partially implemented as computer program modules, which may perform the functions of the respective modules when the program is run by a computer.
Based on the same inventive concept, the embodiment of the application also provides a quantum control system, which utilizes the adjusting method of the two-quantum bit logic gate described in any one of the above feature descriptions to adjust the two-quantum bit logic gate, or comprises the adjusting device of the two-quantum bit logic gate described in the above feature descriptions.
Based on the same inventive concept, the embodiment of the application also provides a quantum computer, which comprises the quantum control system described in the above characteristic description.
Based on the same inventive concept, the embodiment of the present application further provides a readable storage medium, on which a computer program is stored, where the computer program can implement the method for adjusting the two-qubit logic gate according to any one of the above feature descriptions when executed by a processor.
The readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the preceding. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer program described herein may be downloaded from a readable storage medium to a respective computing/processing device or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives the computer program from the network and forwards the computer program for storage in a readable storage medium in the respective computing/processing device. The computer program used to perform the operations of the present invention may be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as SMALLTALK, C ++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer program may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present invention are implemented by personalizing electronic circuitry, such as programmable logic circuits, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information for a computer program, which can execute computer-readable program instructions.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer programs. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the programs, when executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer programs may also be stored in a readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the readable storage medium storing the computer program includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the computer program which is executed on the computer, other programmable apparatus or other devices implements the functions/acts specified in the flowchart and/or block diagram block or blocks.
In the description of the present specification, a description of the terms "one embodiment," "some embodiments," "examples," or "particular examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (14)
1. A method for adjusting a two-qubit logic gate, comprising:
executing two-quantum bit logic gates on a first quantum bit and a second quantum bit, and executing two-time Ramsey experiments on the second quantum bit, wherein the first quantum bit is respectively in a first selected eigenstate and a second selected eigenstate in the two-time Ramsey experiments, and the first quantum bit and the second quantum bit are two quantum bits directly coupled in a quantum chip;
Based on the results of the two Ramsey experiments, acquiring a first test value of the conditional phase of the two-quantum bit logic gate;
and judging whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition.
2. The adjustment method of claim 1, wherein the obtaining a first test value of the conditional phase of the two-qubit logic gate based on the results of two Ramsey experiments comprises:
respectively obtaining oscillation curves in experimental results of each Ramsey experiment;
and acquiring a first test value of the conditional phase based on the phase difference value of the oscillation curve in the two experimental results.
3. The method of claim 2, wherein the first test value is a phase difference value of an oscillation curve in the results of two experiments.
4. The adjustment method of claim 1, wherein the determining whether the parameters of the two-qubit logic gate are adjusted based on whether the first test value satisfies a preset condition comprises:
Judging whether the first test value is a first preset value or not;
if not, the parameters of the two-quantum bit logic gate are adjusted, the two-quantum bit logic gate is executed on the first quantum bit and the second quantum bit in a return mode, and the Ramsey experiment is executed on the second quantum bit twice;
if yes, the adjustment of the two-quantum bit logic gate is completed.
5. The tuning method of claim 4, wherein the parameters of the two-qubit logic gate include an amplitude and a duration.
6. The method of claim 4, wherein the first predetermined value is pi.
7. The tuning method of claim 1, wherein the quantum chip further comprises a third qubit in direct coupling relation with the first qubit but not in direct coupling relation with the second qubit;
the adjustment method further comprises the following steps:
executing the two-qubit logic gate on the first qubit and the second qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate, and executing the Ramsey experiment on the second qubit twice;
Respectively obtaining first test values of the conditional phases of the two-qubit logic gates corresponding to the third qubit when the third qubit is in the first selected eigenstate and the second selected eigenstate;
And acquiring the conditional phase difference of the two-qubit logic gate based on the acquired difference value of the two first test values.
8. The adjustment method of claim 7, wherein the adjustment method further comprises:
and adjusting the conditional phase of the two-qubit logic gate by using the acquired conditional phase difference.
9. The tuning method of claim 7, wherein the number of third qubits is a plurality;
the adjustment method further comprises the following steps:
respectively obtaining a conditional phase difference corresponding to each third quantum bit;
and adjusting the conditional phase of the qubit logic gate by using the acquired plurality of conditional phase differences.
10. The adjustment method of claim 9, wherein adjusting the conditional phase of the qubit logic gate using the obtained plurality of conditional phase differences comprises:
acquiring a sum of the plurality of conditional phase differences;
And adjusting the conditional phase of the qubit logic gate by using the sum value.
11. An apparatus for adjusting a two-qubit logic gate, comprising:
an experiment execution unit configured to execute a two-qubit logic gate on a first qubit and a second qubit, and execute a two-time Ramsey experiment on the second qubit, in which the first qubit is in a first selected eigenstate and a second selected eigenstate, respectively, wherein the first qubit and the second qubit are two qubits directly coupled in a quantum chip;
A conditional phase acquisition unit configured to acquire a first test value of a conditional phase of the two-qubit logic gate based on a result of two Ramsey experiments;
and the adjusting unit is configured to judge whether the parameters of the two-quantum bit logic gate are adjusted based on whether the first test value meets a preset condition.
12. A quantum control system, characterized in that the two-qubit logic gate is adjusted by means of the adjustment method of the two-qubit logic gate according to any one of claims 1-10, or the adjustment device of the two-qubit logic gate according to claim 11 is included.
13. A quantum computer comprising the quantum control system of claim 12.
14. A readable storage medium having stored thereon a computer program, which when executed by a processor is capable of implementing the method of adjusting a two-qubit logic gate according to any one of claims 1 to 10.
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