CN118033367A - Chip test system - Google Patents
Chip test system Download PDFInfo
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- CN118033367A CN118033367A CN202410014780.9A CN202410014780A CN118033367A CN 118033367 A CN118033367 A CN 118033367A CN 202410014780 A CN202410014780 A CN 202410014780A CN 118033367 A CN118033367 A CN 118033367A
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- 238000012360 testing method Methods 0.000 title claims abstract description 227
- 239000000523 sample Substances 0.000 claims abstract description 33
- 238000010998 test method Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The chip test system is used for testing a wafer integrated with a gate drive resistor and an IGBT, wherein a grid test pad, a first resistance test pad and a second resistance test pad are formed on the wafer, the grid test pad is connected with a grid of the IGBT, the first resistance test pad is connected with the first gate drive resistor, and the second resistance test pad is connected with the second gate drive resistor; the system comprises a first test channel, a second test channel, a third test channel and a probe card, wherein when the system works, a probe on the probe card is respectively connected with a grid test pad, a first resistance test pad and a second resistance test pad; when the first gate electrode driving resistor is required to be tested, a passage is formed among the first test channel, the gate electrode test pad, the first resistor test pad and the second test channel; when the second gate driving resistor is required to be tested, a passage is formed among the first test channel, the gate test pad, the second resistance test pad and the third test channel.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a chip testing system.
Background
The insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT) is a composite full-control-voltage-driven-power semiconductor device which is formed by equivalently compounding a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar transistor (bipolar junction transistor, BJT), integrates the advantages of the BJT and the MOSFET, has the characteristics of small driving power, reduced saturation voltage, high input impedance, strong processing capability for high voltage and high current and the like, and is widely applied to the fields of new energy automobiles, photovoltaics and the like at present.
In a driving circuit of the IGBT, a gate electrode driving resistor plays an important role, and can eliminate gate oscillation generated in a gate circuit under the excitation of a driver driving pulse by controlling the charge and discharge speed of a gate electrode capacitor; in addition, the power loss in the driver can be transferred, and the on-off speed of the IGBT can be adjusted. With the continuous improvement of IGBT product design technology and process capability, the gate drive resistor and the IGBT can be integrated on the same chip.
Generally, a wafer integrated with an IGBT and a gate driving resistor is provided with a test area, and a test pad (pad) is formed on the test area, and a probe card of a test device can be connected to the test pad to be connected to a corresponding test channel for testing. For a wafer with a test area containing only a single resistive test pad (hereinafter referred to as "RG test pad"), the probe card may be connected to the corresponding test pad in the manner described above, such that the RG test pad and gate (gate) test pad access the corresponding test channel for testing.
However, to achieve better driving effect, different driving speeds can be used for switching on and switching off the IGBT, and such IGBT products are usually provided with one gate test pad and two RG test pads (RG 1 test pad and RG2 test pad, respectively), and two probe cards need to be designed for testing the IGBT products, and the two probe cards are tested in two steps. For example, the gate test pad of the gate driving resistor needs to be connected to the a test channel, the RG1 test pad and the RG2 test pad need to be connected to the C test channel but cannot be connected to the C test channel simultaneously, so that two steps of testing are needed, and the resistance values of the two gate driving resistors are measured respectively through two probe cards.
Disclosure of Invention
The application provides a chip test system which can solve the problem of low efficiency caused by the fact that two types of probe cards are needed to measure gate drive resistance in two steps in the chip test system provided in the related art.
The testing system is used for testing a wafer integrated with a gate driving resistor and an IGBT, a grid testing pad, a first resistance testing pad and a second resistance testing pad are formed on the wafer, the grid testing pad is connected with a grid of the IGBT, the first resistance testing pad is connected with the first gate driving resistor, and the second resistance testing pad is connected with the second gate driving resistor;
the system comprises a first test channel, a second test channel, a third test channel and a probe card, wherein when the system works, probes on the probe card are respectively connected with the grid test pad, the first resistance test pad and the second resistance test pad;
when the first resistance test pad is required to be tested, a passage is formed among the first test channel, the grid test pad, the first resistance test pad and the second test channel;
When the test is required to be performed through the second resistance test pad, a passage is formed among the first test channel, the grid test pad, the second resistance test pad and the third test channel.
In some embodiments, the system further comprises a control circuit;
The first test channel is respectively connected with the drain electrode of the control circuit and the first power supply hardware, and when the system works, the drain electrode of the control circuit is electrically connected with the grid test pad through a probe;
the second test channel is respectively connected with the grid electrode of the control circuit and the second power supply hardware, and when the system works, the grid electrode of the control circuit is electrically connected with the first resistance test pad through a probe;
The third test channel is respectively connected with the source electrode of the control circuit and third power supply hardware, and when the system works, the drain electrode of the control circuit is electrically connected with the second resistance test pad through a probe.
In some embodiments, when the first gate driving resistor needs to be tested, current is introduced into the first test channel through the first power supply hardware, the third test channel is shorted, current is introduced into the second test channel through the third power supply hardware, and the resistance value of the first gate driving resistor is measured by measuring a path voltage.
In some embodiments, the resistance of the first gate drive resistor is measured by the pass voltage using a Kelvin test method.
In some embodiments, when the second gate resistor needs to be tested, current is supplied to the first test channel through the first power supply hardware, current is supplied to the third test channel through the third power supply hardware, current is not supplied to the second test channel, and the resistance value of the second gate driving resistor is measured by measuring a measurement path voltage.
In some embodiments, the resistance of the second gate drive resistor is measured by the pass voltage using a Kelvin test method.
The technical scheme of the application at least comprises the following advantages:
Through providing a chip test system, when its during operation, insert grid test pad, first resistance test pad and second resistance test pad once only with the probe on the probe card, when needs carry out the test to first gate drive resistance, constitute the passageway and test between control first test channel, grid test pad, first resistance test pad and the second test channel, when needs carry out the test to second gate resistance drive resistance, constitute the passageway and test between control first test channel, grid test pad, second resistance test pad and the third test channel, thereby realized only needs a probe card, design a set of test system can realize measuring the IGBT integrated circuit that contains two gate drive resistances, improved test efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip test system according to an exemplary embodiment of the present application when testing through a first resistive test pad;
fig. 2 is a schematic diagram of a chip testing system according to an exemplary embodiment of the present application when testing through a second resistive test pad.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1 and 2, which illustrate schematic diagrams of a chip test system according to an exemplary embodiment of the present application, as shown in fig. 1, the system includes a first test channel (referred to as "a channel" in fig. 1 as a first test channel), a second test channel (referred to as "B channel" in fig. 1 as a second test channel), 120, a third test channel (referred to as "C channel" in fig. 1 as a third test channel), and a probe card (not shown in fig. 1).
The system is used for testing a wafer 200, wherein an IGBT and a gate driving resistor (two gate driving resistors are corresponding to each IGBT, respectively, a first gate driving resistor and a second gate driving resistor) are integrated on the wafer 200, a test area 210 is included on the wafer (a plurality of test areas are formed on the wafer 200, one test area 210 is exemplified in fig. 1 and 2), a gate test pad G, a first resistor test pad RG1 and a second resistor test pad RG2 are formed in the test area 210, the gate test pad G is connected with the gate of the IGBT, the first resistor test pad RG1 is connected with the first gate driving resistor, the second resistor test pad RG2 is connected with the second gate driving resistor, and the first resistor test pad RG1 and the second resistor test pad RG2 are electrically connected with the gate test pad G inside the integrated circuit.
When the system works, the probes on the probe card are respectively connected with the grid test pad G, the first resistance test pad RG1 and the second resistance test pad RG 2. When the first gate driving resistor needs to be tested, a control device (not shown in fig. 1) on the test machine can enable a first test channel 110, a gate test pad G, a first resistor test pad RG1 and a second test channel 120 to form a passage; when the second gate driving is required to be tested, a path is formed among the first test channel 110, the gate test pad G, the second resistance test pad RG2 and the third test channel 130 by the control device.
The system comprises a control circuit 140, wherein a first test channel 110 is respectively connected with a drain electrode of the control circuit 140 and first power supply hardware (power supply hardware 1), and when the system works, the drain electrode of the control circuit 140 is electrically connected with a grid test pad G through a probe; the second test channel 120 is connected to the gate of the control circuit 140 and the second power supply hardware (power supply hardware 2), and when the system works, the gate of the control circuit 140 is electrically connected to the first resistance test pad RG1 through the probe; the third test channel 130 is connected to the source of the control circuit 140 and the third power supply hardware (power supply hardware 3), respectively, and when the system is in operation, the source of the control circuit 140 is electrically connected to the second resistance test pad RG2 through the probe.
In the embodiment of the application, the two gate driving resistances can be respectively tested in the following manner: when the first gate driving resistor needs to be tested, current is introduced into the first test channel 110 through the first power supply hardware connected with the first gate driving resistor, the third test channel 130 is in short circuit, current is introduced into the second test channel 120 through the third power supply hardware connected with the third test channel 130, and the resistance value of the gate driving resistor is measured by measuring the voltage of a channel and adopting a Kelvin test method; when the second gate driving resistor needs to be tested, current is fed to the first test channel 110 through the first power supply hardware connected with the second gate driving resistor, current is fed to the second test channel through the third power supply hardware connected with the third test channel 130, current is not fed to the second power supply hardware connected with the second test channel 120, and the resistance of the gate driving resistor is measured by measuring the channel voltage and adopting the Kelvin test method.
In some embodiments, each test channel further includes a fast test channel (shown in solid lines in fig. 1 and 2) and a slow test channel (shown in dashed lines in fig. 1 and 2), the fast test channel is used for testing the gate driving resistance during fast driving, the slow test channel is used for testing the gate driving resistance during slow driving (the driving speed of the gate driving resistance to the IGBT during slow driving is slower than the driving speed of the gate driving resistance to the IGBT during fast driving), and the fast test channel and the slow test channel in each test channel can be switched by the control device.
In summary, in the embodiment of the present application, by providing a chip test system, when the chip test system works, a probe on a probe card is connected to a gate test pad, a first resistor test pad and a second resistor test pad at a time, when a first gate driving resistor needs to be tested, a path is controlled to be formed between the first test channel, the gate test pad, the first resistor test pad and the second test channel for testing, and when a second gate driving resistor needs to be tested, a path is controlled to be formed between the first test channel, the gate test pad, the second resistor test pad and the third test channel for testing, so that only one probe card is needed, and a set of test system is designed to realize measurement of an IGBT integrated circuit including two gate driving resistors, thereby improving test efficiency.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (6)
1. The chip test system is characterized in that the test system is used for testing a wafer integrated with a gate drive resistor and an IGBT, a gate test pad, a first resistance test pad and a second resistance test pad are formed on the wafer, the gate test pad is connected with a gate of the IGBT, the first resistance test pad is connected with the first gate drive resistor, and the second resistance test pad is connected with the second gate drive resistor;
the system comprises a first test channel, a second test channel, a third test channel and a probe card, wherein when the system works, probes on the probe card are respectively connected with the grid test pad, the first resistance test pad and the second resistance test pad;
when the first resistance test pad is required to be tested, a passage is formed among the first test channel, the grid test pad, the first resistance test pad and the second test channel;
When the test is required to be performed through the second resistance test pad, a passage is formed among the first test channel, the grid test pad, the second resistance test pad and the third test channel.
2. The system of claim 1, further comprising a control circuit;
The first test channel is respectively connected with the drain electrode of the control circuit and the first power supply hardware, and when the system works, the drain electrode of the control circuit is electrically connected with the grid test pad through a probe;
the second test channel is respectively connected with the grid electrode of the control circuit and the second power supply hardware, and when the system works, the grid electrode of the control circuit is electrically connected with the first resistance test pad through a probe;
The third test channel is respectively connected with the source electrode of the control circuit and third power supply hardware, and when the system works, the drain electrode of the control circuit is electrically connected with the second resistance test pad through a probe.
3. The system of claim 2, wherein when the first gate drive resistor is required to be tested, current is passed through the first power supply hardware to the first test channel, the third test channel is shorted, current is passed through the third power supply hardware to the second test channel, and a resistance of the first gate drive resistor is measured by measuring a path voltage.
4. The system of claim 3, wherein the resistance of the first gate drive resistor is measured by a kelvin test method through the pass voltage.
5. The system of claim 2, wherein when the second gate resistance is to be tested, current is passed through the first power supply hardware to the first test channel, current is passed through the third power supply hardware to the third test channel, current is not passed through the second test channel, and a resistance value of the second gate drive resistance is measured by measuring a measurement path voltage.
6. The system of claim 5, wherein the resistance of the second gate drive resistor is measured by the path voltage using a kelvin test method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410014780.9A CN118033367A (en) | 2024-01-04 | 2024-01-04 | Chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410014780.9A CN118033367A (en) | 2024-01-04 | 2024-01-04 | Chip test system |
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| Publication Number | Publication Date |
|---|---|
| CN118033367A true CN118033367A (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410014780.9A Pending CN118033367A (en) | 2024-01-04 | 2024-01-04 | Chip test system |
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| CN (1) | CN118033367A (en) |
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- 2024-01-04 CN CN202410014780.9A patent/CN118033367A/en active Pending
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