CN118033209A - Dual-channel broadband Hall current sensor and implementation method - Google Patents
Dual-channel broadband Hall current sensor and implementation method Download PDFInfo
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Abstract
The invention provides a double-channel bandwidth Hall current sensor and an implementation method thereof, and belongs to the technical field of magnetic sensors. The dual-channel bandwidth Hall current sensor comprises 1 low-frequency channel, 1 high-frequency channel, 1 matching network, 1 clock generation circuit and 1 on-chip S-shaped copper rail. The invention has novel structure and simple realization, the low-frequency channel adopts the current mode dynamic offset elimination and weak Hall current amplification technology, thus not only realizing extremely low residual offset and noise, but also obtaining extremely high linearity; the amplifying and offset calibration circuit not only solves the problem that the circuit does not work because of overlarge direct current offset of a high-frequency channel, but also obtains high gain and bandwidth, and the whole circuit has low residual offset; the dual-channel circuit design scheme of the pure Hall device probe is adopted, a large-size Rogowski coil and a coupling capacitor are not needed, the sensor integration level is improved, the power consumption is reduced, and the bandwidth above the MHz level is also obtained.
Description
Technical Field
The invention provides a dual-channel Hall current sensor with bandwidth above MHz and an implementation method thereof, which realize sub-microsecond rapid current detection and belong to the technical field of magnetic sensors.
Background
In recent years, CMOS hall sensors are widely used in fields of automotive electronics, industrial control, power management, aerospace, military and the like by virtue of their high accuracy, high reliability, small volume, easy integration and the like. However, the common CMOS hall sensor has the problems of low bandwidth, slow response speed and the like, and cannot accurately measure the current with the frequency above MHz and provide subtle-level fast current to realize overcurrent protection. The reasons for the bandwidth limitation of the CMOS Hall sensor are from the parasitic capacitance of the Hall device, the parasitic capacitance influence of the MOS transistor switch in the dynamic rotating current circuit and the limitation of the cut-off frequency of the low-pass filter of the output stage. Currently, the mainstream design scheme for implementing MHz-level broadband hall sensors generally employs improved rotating current modulation and demodulation circuits, single-channel amplification circuits with pure hall probes without rotating circuits, and hybrid dual-channel amplification circuits based on hall devices and induction coils. However, the bandwidth of the sensor based on the rotating current modulation and demodulation circuit is hardly limited by the parasitic capacitance in the dynamic rotating current circuit and the 3dB bandwidth of the output low-pass filter to reach 1MHz. In addition, the single-channel amplification scheme adopting the pure Hall probe non-rotating circuit can solve the limitation of parasitic capacitance in the dynamic rotating current circuit on bandwidth, but the residual imbalance of the sensor is overlarge when the dynamic rotating current circuit senses low-frequency current signals because the Hall probe imbalance is effectively eliminated, so that the minimum resolution of the current sensor is influenced. Although the mixed type double-channel amplifying circuit scheme can solve the problem of residual mismatch of a low-frequency channel, a high-frequency circuit adopts a large-size coil to expand bandwidth, and a direct-current offset eliminating circuit is lacked, so that the working point of the amplifier is easily offset greatly, and a Hall sensor cannot work normally; and because of adopting the chopping technology in the low-frequency path, larger ripple exists, a complex ripple cancellation loop is needed, and the chip area is increased. Aiming at the problems of low bandwidth, large residual mismatch and the like in the current mainstream fully-integrated Hall sensor circuit scheme, the invention provides a double-channel broadband Hall current sensor.
Disclosure of Invention
The invention provides a double-channel broadband Hall current sensor which comprises 1 low-frequency channel, 1 high-frequency channel, 1 matching network, 1 clock generating circuit and 1 on-chip S-shaped copper rail. The low-frequency channel output ports are vo_cds1 and vo_cds2, and the output ports vo_cds1 and vo_cds2 are respectively connected with the input ports vi_l1 and vi_l2 of the matching network circuit. The further high-frequency channel output ports are vo_lo1 and vo_lo2, the output ports are vo_lo1 and vo_lo2 and are respectively connected with the matching network input ports vi_h1 and vi_h2, the matching network output ports are vout_p and vout_n, the further clock generation circuit output ports T1-T4, T5, T6 and T7-T9 are connected with the low-frequency channel clock input ports clk 1-clk 4, clk5, clk6 and clk 7-clk 9, the clock generation circuit output ports T10 and T11 are connected with the high-frequency channel clock input ports clk10 and clk11.
The low-frequency path further comprises a dynamic rotating current circuit, a current integration amplifying circuit and a correlated double sampling circuit, wherein the output port Vo1 of the dynamic rotating current circuit is connected with the input port vi_1 of the current integration amplifying circuit, the output port Vo4 of the dynamic rotating current circuit is connected with the input port vi_1 of the current integration amplifying circuit, the output port Vo2 of the dynamic rotating current circuit is connected with the input port vi_2 of the current integration amplifying circuit, the output ports vo_i1 and vo_i2 of the dynamic rotating current circuit are respectively connected with the input ports vi_cds1 and vi_cds2 of the correlated double sampling circuit, and the output ports vo_cds1 and vo_cds2 of the correlated double sampling circuit are respectively connected with the input ports vi_l1 and vi_l2 of the matched network circuit.
The dynamic rotating current circuit comprises two rotating current circuits (CS 1 and CS 2) with the same structure and two identical transconductance amplifying circuits (GM 1 and GM 2). Further, the rotating current circuit CS1 includes 16 NMOS transistors M1 to M16, a hall probe X1, and a bias current source Ibias. Taking the circuit connection relation of the rotating current circuit CS1 as an example, the drains of NMOS tubes M1-M4 are commonly connected to the output end of an input bias current source Ibias, the input end of the bias current source Ibias is connected with a voltage source VDD, the grids of the NMOS tubes M1-M4 are respectively and sequentially connected to clock signal input ports clk 1-clk 4, and the sources of the NMOS tubes M1-M4 are respectively and sequentially connected with an a port, a b port, a d port and a c port of a Hall probe X1; the sources of the NMOS tubes M5-M8 are commonly connected to GND, the grids of the NMOS tubes M5-M8 are respectively connected to the clock signal input ports clk 1-clk 4in sequence, and the drains of the NMOS tubes M5-M8 are respectively connected to the port a, the port b, the port d and the port c of the Hall probe X1 in sequence; the sources of the NMOS tubes M9-M12 are commonly connected to an external port Vs1, the grids of the NMOS tubes M9-M12 are respectively connected to clock signals clk 1-clk 4in sequence, and the drains of the NMOS tubes M9-M12 are respectively connected to the c port, the a port, the d port and the b port of the Hall probe in sequence; the sources of the NMOS tubes M13-M16 are commonly connected to an external port Vs2, the grids of the NMOS tubes M13-M16 are respectively and sequentially connected to clock signal input ports clk 1-clk 4, and the drains of the NMOS tubes M13-M16 are respectively and sequentially connected to a d port, a b port, a c port and an a port of the Hall probe X1; all the substrates of the 16 NMOS transistors are grounded. Further, the rotating current circuit CS2 includes 16 NMOS transistors M1 to M16, one hall probe X2, clock signal input ports clk1 to clk4, a bias current source Ibias, and external output ports Vs3, vs4, and the circuit structure of the rotating current circuit CS2 is identical to that of the rotating current circuit CS 1. Further, the output ports Vs1 and Vs2 of the rotating current circuit CS1 are connected to the input ports V1 and V2 of the transconductance amplifying circuit GM1, and the output ports Vs3 and Vs4 of the rotating current circuit CS2 are connected to the input ports V3 and V4 of the transconductance amplifying circuit GM 2.
The current integration amplifying circuit comprises an amplifier OPA, a capacitor C1, a capacitor C2, a switch K1 and a switch K4. Further, the switches K1 and K2 are connected to the clock signal clk5, the switches K3 and K4 are connected to the clock signal clk6, the output ports Vo1 and Vo2 of the transconductance amplifying circuit GM1 are respectively connected to the input ports vi_1 and vi_2 of the current integrating amplifying circuit, the output ports Vo3 and Vo4 of the transconductance amplifying circuit GM2 are respectively connected to the input ports vi_2 and vi_1 of the current integrating amplifying circuit, the input port vi_1 is connected to the in-phase input port of the amplifier OPA through the switch K1, the other port of the switch K1 is respectively connected to the one port of the switch K3 and the one port of the capacitor C1, the other port of the switch K3 and the other port of the capacitor C1 are commonly connected to the inverting output port vo_i1 of the amplifier OPA, the other port vi_2 is connected to the inverting input port of the amplifier OPA through the switch K2, and the other port of the switch K2 is respectively connected to the one port of the switch K4 and the one port of the capacitor C2, and the other port of the switch K4 and the other port of the capacitor C2 are commonly connected to the in-phase output port vo_i2 of the amplifier OPA.
The correlated double sampling circuit comprises an amplifier OPA1, capacitors C3-C8 and switches K5-K12. The switches K5, K6, K9 and K10 are commonly connected with the clock signal clk7, the switches K7 and K11 are commonly connected with the clock signal clk8, and the switches K8 and K12 are commonly connected with the clock signal clk9. The input port vi_cds1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with the output port Vn of the amplifier OPA1 through a switch K5, and is also connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with the ground through a switch K6, and is also connected with the output port Vn of the amplifier OPA1 through a switch K7, and the output port Vn of the amplifier OPA1 is connected with one end of the capacitor C5 through a switch K8 and serves as an output port vo_cds1, and the other end of the capacitor C5 is connected with the ground. The input port vi_cds2 is connected to one end of a capacitor C6, the other end of the capacitor C6 is connected to the output port Vp of the amplifier OPA1 through a switch K9, and is also connected to one end of a capacitor C7, the other end of the capacitor C7 is connected to the ground through a switch K11, and is also connected to the output port Vp of the amplifier OPA1 through a switch K10, the output port Vp of the amplifier OPA1 is connected to one end of a capacitor C8 through a switch K12 and serves as an output port vo_cds2, and the other end of the capacitor C8 is connected to the ground.
The high-frequency path comprises two bias circuits (N_CS 1 and N_CS 2) with the same structure, a voltage amplifying circuit and an amplifying and offset calibrating circuit. The bias circuit output ports Vno1, vno2, vno3 and Vno4 are connected with the voltage amplifying circuit input ports vi_ns1, vi_ns2, vi_ns3 and vi_ns4, the voltage amplifying circuit output ports vo_ns1 and vo_ns2 are respectively connected with the amplifying and offset calibration circuit input ports vi_lo1 and vi_lo 2, and the amplifying and offset calibration circuit output ports vo_lo1 and vo_lo2 are connected with the matching network input ports vi_h1 and vi_h2.
The bias circuit N_CS1 comprises a Hall probe X3 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X3, a port d of the Hall probe X3 is grounded, a port c of the Hall probe X3 is an output port Vno1 and a port c of the Hall probe X2, the output ports Vno1 and Vno2 are respectively connected with the input ports Vi_ns1 and Vi_ns2 of the voltage amplifying circuit, the bias circuit N_CS2 comprises a Hall probe X4 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X4, a port d of the Hall probe X3 is grounded, a port c of the Hall probe X4 is an output port Vno3 and a port v no4, and the output ports Vno3 and Vno4 are respectively connected with the input ports Vi_ns3 and Vi_ns4 of the voltage amplifying circuit.
The voltage amplifying circuit comprises a transconductance amplifying circuit GM3 and a transconductance amplifying circuit GM4, a resistor R1 and a resistor R2, wherein an in-phase output port of the transconductance amplifying circuit GM3 and an anti-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns1, an anti-phase output port of the transconductance amplifying circuit GM3 and the in-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns2, the output ports vo_ns1 and vo_ns2 are respectively connected with one port of the resistor R1 and one port of the resistor R2, and the other port of the resistor R1 and the other port of the resistor R2 are respectively grounded.
The amplifying and offset calibration circuit comprises an amplifier OPA2, an analog-to-digital converter ADC, a current mode DAC, fixed current sources I1 and I4, adjustable current sources I2 and I3 and a switch K13, wherein an input port Vi_lo1 is connected with an input port VIP of the amplifier OPA2, the input port Vi_lo2 is connected with an adjustable current source I2 and a fixed current source I1 in series respectively, the input port Vi_lo2 is connected with an input port VIN of the amplifier OPA2, the input port VIN of the amplifier OPA2 is connected with an adjustable current source I3 and a fixed current source I4 in series respectively, an output port Vo of the amplifier OPA2 is connected with the ADC through a switch K13, the switch K13 is connected with a clock signal clk11, the further current mode DAC comprises 17 PMOS tubes M1-M17, 9 PMOS tubes M24-M32, 9 clock signal input ports S0-S8 (clock signals connected with the input port S0 is clk10, clock signals connected with the input ports S1-S8 are 8 digital signals output by the ADC), the further adjustable current source I2 comprises 6 NMOS tubes M33-M38, the adjustable current source I3 comprises 4 PMOS tubes M18-M21, the further bandgap reference output port Ierf is connected with the source electrode of the M22 tube, the M0 tube, the M9 tube, the M22 tube and the M23 tube to form a common source common grid structure, the grid electrodes of the M22 tube and the M0 tube are connected with the drain electrode of the M22 tube together, the drain electrode of the M22 tube is connected with the source electrode of the M23 tube, the grid electrodes of the M23 tube and the M9 tube are connected with the drain electrode of the M23 tube together, the drain electrodes of the M0-M8 tube are connected with the source electrode of the power supply voltage VDD together, the grid electrodes of the M0-M8 tube are connected with the grid electrode of the M22 tube together, the source electrodes of the PMOS tubes M9-M17 are connected with the grid electrode of the M23 tube together, the source electrodes of the PMOS tubes M24-M32 are connected with the drain electrodes of the PMOS tubes M9-M17 respectively, the grid electrodes of the PMOS tubes M24-M32 are connected with the clock signals S0-S8 respectively, the drain electrodes of the PMOS tubes M24-M32 are connected with the drain electrodes of the M34 together, the M33-M35 tube forms a common source common grid structure, the M34 tube and the M35 tube grid are connected with the M34 tube drain electrode jointly, the M34 tube and the M35 tube source electrode are connected with the M33 tube and the M36 tube drain electrode respectively, the M34 tube and the M35 tube grid are connected with the M34 tube drain electrode jointly, the M33 tube and the M36 tube source electrode are connected with the GND, the M33 tube and the M36 tube grid are connected with the M33 tube drain electrode jointly, the M37 tube grid is connected with the M34 tube grid electrode, the M37 tube drain electrode is an adjustable current source I2 output port, the M38 tube grid electrode is connected with the M33 tube grid electrode, the M38 tube source electrode is grounded, the M35 tube drain electrode is connected with the M19 tube drain electrode, the NMOS tubes M18-M20 form a common source common grid structure, the M19 tube grid electrode is connected with the M21 tube grid electrode jointly, the M19 tube source electrode is connected with the M18 tube drain electrode respectively, the M18 tube source electrode is connected with the M20 tube drain electrode jointly, the grid electrode of the M18 tube and the M20 tube grid electrode jointly is connected with the M18 tube drain electrode, the source electrode jointly with the M18 tube drain electrode of the M18 tube, the M18 tube grid electrode is connected with the M20 tube source electrode jointly with the source electrode of the M18 tube grid electrode is connected with the source electrode, the output voltage of the M21 tube is connected with the PMOS tube drain electrode, the M32, the output voltage of the M32 is connected with the PMOS tube is connected with the M32, the M32 to the PMOS tube is only 3-32, and the two drain electrode is connected with the PMOS tube is connected with the substrate to the PMOS 3, and the substrate to the ground.
The matching network comprises capacitors C10-C13, resistors R3-R6 and an amplifier OPA3, input ports Vi_h1 and Vi_h2 are respectively connected with one port of the capacitors C10 and C11, input ports Vi_l1 and Vi_l2 are respectively connected with one port of the resistors R3 and R4, the other ports of the capacitor C10 and the resistor R4 are jointly connected with the inverting input end of the amplifier OPA3, the other ports of the capacitor C11 and the resistor R3 are jointly connected with the non-inverting input end of the amplifier OPA3, the non-inverting end of the amplifier OPA3 is simultaneously connected with the resistor R5, one port of the capacitor C12 is jointly connected with the inverting output port Vout_p of the amplifier OPA3, the inverting end of the amplifier OPA3 is connected with one port of the resistor R6, one port of the capacitor C13 is jointly connected with the non-inverting output port Vout_n of the amplifier OPA 3.
The S-shaped copper rail on the chip is designed into an S-shaped current-carrying copper rail by adopting a top layer thick metal above the integrated Hall probe, one end of the S-shaped copper rail flows in current, the other end of the S-shaped copper rail is provided with a current outflow port, two pairs of differential Hall probes, namely Hall probes (X1 and X2) and Hall probes (X3 and X4), are respectively placed at the corners of the S-shaped copper rail, the two pairs of differential Hall probes are used as Hall probes of a high-frequency channel and a low-frequency channel of the current sensor, when the S-shaped copper rail flows in current, two pairs of identical differential magnetic fields (differential magnetic field 1 and differential magnetic field 2) are generated below the S-shaped copper rail, the differential magnetic field 1 is detected by the Hall probes (X1 and X2) in the same size and opposite directions, and the differential magnetic field 2 is detected by the Hall probes (X3 and X4).
Further, in the two-channel broadband hall current sensor circuit, the low-frequency channel output ports vo_cds1 and vo_cds2 are connected with the input ports vi_l1 and vi_l2 of the matching network, because the input ports vi_l1 and vi_l2 are connected with the subsequent circuit by resistors, the matching network functions as a low-pass filter from the input ports vi_l1 and vi_l2 of the matching network to the output ports vout_p and vout_n of the matching network, the matching network is a low-pass filter for the low-frequency channel, the cut-off frequency is fx=1/(2pi R 5C12), wherein Fx is the cut-off frequency of the matching network, R 5 is the resistance of the resistor R5, C 12 is the capacitance of the capacitor C12, the high-frequency channel output ports vo_lo1 and vo_l2 are connected with the input ports vi_h1 and vi_h2 of the matching network, because the input ports vi_h1 and vi_h2 are connected with the subsequent circuit by the capacitors, the matching network from the input ports Vi_h1 and Vi_h2 to the output ports Vout_p and Vout_n of the matching network shows the function of a high-pass filter, so that the matching network is a high-pass filter for a high-frequency path, the cutoff frequency is fx=1/(2pi R 5C12), wherein Fx is the cutoff frequency of the matching network, R 5 is the resistance of a resistor R5, C 12 is the capacitance of a capacitor C12, so that when the frequency of an input signal is lower than the cutoff frequency Fx, the low-frequency path can normally amplify the input signal, the high-frequency path does not amplify the input signal, when the frequency of the input signal is higher than the cutoff frequency Fx, the high-frequency path can normally amplify the input signal, the low-frequency path does not amplify the input signal, the gain of the low-frequency path is designed to be the same as the gain of the high-frequency path, the matching network can combine the overall gains of the low-frequency path and the high-frequency path, thereby effectively increasing the overall circuit bandwidth.
The specific working method for the circuit applied to the double-channel broadband Hall current sensor is as follows:
s1: the frequency of the current flowing in the S-shaped copper rail is smaller than the cut-off frequency Fx
S1.1: four-phase rotation modulation operation of hall signal polarity and offset signal polarity
When the frequency of the S-shaped copper rail inflow current is smaller than the cutoff frequency Fx, two pairs of differential magnetic fields are generated below the S-shaped copper rail and detected by differential Hall probes (X1 and X2) of a low-frequency path and differential Hall probes (X3 and X4) of a high-frequency path respectively, but because the frequency of the S-shaped copper rail inflow current is smaller than the cutoff frequency Fx, the low-frequency path can normally amplify an input signal, the high-frequency path does not amplify the input signal, at the moment, when the first phase operation of a dynamic rotating current circuit is carried out, the clock input clk1 of the dynamic rotating current circuit is high level, other clock inputs are all low level, the differential magnetic field signals detected by the Hall probe X1 in the rotating current circuit CS1 and the Hall probe X2 in the rotating current circuit CS2 are equal in size, the directions are opposite, the voltage output by the rotating current circuit CS1 is Vh+V os11 +Vc (Vh is Hall voltage, vc is interference voltage brought by a common-mode magnetic field, V os11-Vos14 is offset voltage output by the Hall probe X1 first phase to a fourth phase rotating current circuit), and the rotating current CS2 is output by the fourth phase rotating circuit is offset voltage os21+Vc(Vos21-Vos24; when the second phase operation of the dynamic rotating current circuit is carried out, the clock input clk2 of the dynamic rotating current circuit is high level, all other clock inputs are low level, the voltage output by the rotating current circuit CS1 is Vh-V os12 +Vc, and the voltage output by the rotating current circuit CS2 is-Vh-V os22 +Vc; when the third phase operation of the dynamic rotating current circuit is performed, the clock input clk3 of the dynamic rotating current circuit is at a high level, all other clock inputs are at a low level, the voltage output by the rotating current circuit CS1 is-Vh+V os13 +Vc, and the voltage output by the rotating current circuit CS2 is Vh+V os23 +Vc; when the fourth phase operation of the dynamic rotating current circuit is performed, the clock input clk4 of the dynamic rotating current circuit is at a high level, all other clock inputs are at a low level, the voltage output by the rotating current circuit CS1 is Vh-V os14 +Vc, and the voltage output by the rotating current circuit CS2 is Vh-V os24 +Vc; the four-phase Hall voltage and offset voltage output by CS1 are converted into currents of Ih+I os11+Ic、Ih-Ios12+Ic、-Ih+Ios13+Ic、-Ih-Ios14 +ic (the currents Ih, I os11-Ios14 and Ic are voltages Vh, V os11-Vos14 and Vc are converted into currents through a transconductance amplifying circuit GM 1) through a transconductance amplifying circuit GM1, the aliasing signal of the four-phase Hall voltage and offset voltage output by CS2 is converted into currents of-Ih+I os21+Ic、-Ih-Ios22+Ic、Ih+Ios23+Ic、Ih-Ios24 +ic (the currents Ih, I os21-Ios24 and Ic are voltages Vh, V os21-Vos24 and Vc are converted into currents through the transconductance amplifying circuit GM 1) through a transconductance amplifying circuit GM1, and then each phase Hall current and offset current output by the transconductance amplifying circuit GM1 and each phase Hall current and offset current output by the transconductance amplifying circuit GM1 are subtracted to obtain new four-phase Hall current and offset current 2Ih+Ios11-Ios21、2Ih-Ios12+Ios22、-2Ih+Ios13-Ios23、-2Ih-Ios14+Ios24.
S1.2: operation of integrating and amplifying Hall current into Hall voltage
When the clock signal clk1, clk2 is effective at high level, the current outputted by the transconductance amplifying circuits GM1 and GM2 is subtracted to obtain the hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22 of the first phase and the second phase, when the clock signal clk5 is effective at high level, the hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22 of the first phase and the second phase are sent to the current integrating amplifying circuit to operate, because the polarities of the hall currents outputted by the first phase and the second phase rotating current circuits are positive, the polarities of offset currents are opposite, the offset currents after being sent to the current integrating amplifying circuit are offset, the hall currents are mutually overlapped, the obtained output hall voltage is V 1-2＝4Vh+Vos1-2, wherein 4Vh is the hall voltage outputted by integrating and amplifying the hall current Ih, vos 1-2 is the residual voltage after integrating and amplifying the first phase and the second phase offset current, and then when the clock signal clk6 is effective at high level, the voltage on the integrating capacitors C1 and C2 is cleared.
When the clock signal clk3 and clk4 are effective in high level, the currents outputted by the transconductance amplifying circuits GM1 and GM2 are subtracted to obtain hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 in the third phase and the fourth phase, when the clock signal clk5 is effective in high level, the hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 in the third phase and the fourth phase are subjected to current integration operation, as the polarities of the hall currents outputted by the third phase and the fourth phase are both negative, the polarities of offset currents are changed in opposite directions, the offset currents are offset after being fed into the current integration amplifying circuits, the hall currents are mutually overlapped, the obtained output hall voltage is V 3-4＝-4Vh+Vos3-4, wherein-4 Vh is the hall voltage outputted after the hall currents Ih are integrated and amplified, vos 3-4 is the residual offset voltage after the third phase and the fourth phase offset currents are integrated and amplified, and then when the clock signal clk6 is effective in high level, the voltages on the integrating capacitors C1 and C2 are cleared.
S1.3: hall voltage sample-and-hold operation
When the clock control signal clk7 of the related double sampling circuit is valid in a high level, the related double sampling circuit performs first sampling and holding on the output Hall voltage of the current integrating amplifying circuit as V 1-2＝4Vh+Vos1-2; when the clock control signal clk8 of the correlated double sampling circuit is valid at a high level, the correlated double sampling circuit performs a second sample hold on the output hall voltage V 3-4＝-4Vh+Vos3-4 of the current integration amplifying circuit, and when the clock signal clk9 is valid at a high level, the correlated double sampling circuit subtracts the voltage value V 3-4 of the second sample hold from the voltage value V 1-2 of the first sample hold to obtain the output hall voltage signal vout=v 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4.
S1.4: filtering high-frequency harmonic operation:
the Hall voltage obtained by subtracting the two samples passes through input ports Vi_l1 and Vi_l2 of the matching network, and because the input ports Vi_l1 and Vi_l2 are respectively connected with resistors, a low-pass filter is formed with a subsequent connecting circuit, the low-pass filter in the matching network filters high-frequency harmonic components, finally, a Hall voltage signal is output, and offset signals are effectively eliminated, so that an output Hall voltage signal Vout=V 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4 is obtained.
S2: the frequency of the current flowing into the S-shaped copper rail is larger than the cut-off frequency Fx
S2.1: high frequency path DC offset calibration operation
Because the high-frequency channel does not adopt a signal polarity modulation method to eliminate direct current offset in order to realize high bandwidth, the direct current offset of the high-frequency channel is larger, and the high-frequency channel possibly cannot work normally, so before detecting a high-frequency magnetic field signal, the direct current offset calibration of the high-frequency channel is carried out, at the moment, an S-shaped copper rail does not flow in current, a magnetic field is not generated around the S-shaped copper rail, no magnetic field signal is input, a clock input port clk10 is high level, clk11 is low level, clock input ports S1-S8 are low level, at the moment, a band gap reference generates current I, the current I is copied into adjustable current sources I2 and I3 respectively through a common-source common-gate current mirror in the same proportion, the current sizes of the adjustable current sources I2 and I3 are I, the current sizes of fixed current sources I1 and I4 are I f, the current difference between the adjustable current source I2 and the fixed current source I1 generates a direct current voltage V1= (I f -I) x R1 on a resistor R1, the current difference between the adjustable current source I3 and the fixed current source I4 generates a direct current voltage V2= (I-I f) x R2 on a resistor R2, the resistance of the resistor R1 and the resistance of the resistor R2 are equal, at this time, the differential direct current voltage of the input ends VIP and VIN of the amplifier OPA2 is V1-V2, the direct current voltage vo=A x (V1-V2) +V3 of the output end of the amplifier OPA2, wherein A is the gain size of the amplifier OPA2, A x (V1-V2) is the direct current voltage amplified by the amplifier OPA2, V3 is the direct current voltage output by the amplifier OPA2 when the differential direct current voltage is not input by the amplifier OPA2, when the clock input port clk10 is low and clk11 is high, the dc offset calibration operation is started, and the dc offset calibration principle is as follows: if the dc voltage Vo at the output end of the amplifier OPA2 is greater than VDD/2 (VDD/2 is the dc voltage at the output end of the amplifier OPA2 during normal operation), the ADC quantizes the voltage at the output end Vo of the amplifier OPA2 and outputs an 8-bit digital signal, which sequentially controls the on and off of the clock input ports S1-S8 respectively, and further controls the current mode DAC to generate a current I DAC1 larger than I/2 (the current I/2 is the current generated by the current mode DAC after the ADC quantized voltage vo=VDD/2), the current I DAC1 generated by the DAC is copied into the adjustable current sources I2 and I3 in the same proportion through the cascode current mirror, so that the current sizes of the adjustable current sources I2 and I3 are increased, A× (V1-V2) is reduced, the direct current voltage Vo at the output end of the amplifier OPA2 is reduced, if the output end direct current voltage Vo of the amplifier OPA2 is smaller than VDD/2, the ADC quantizes the output end Vo of the amplifier OPA2 and outputs 8-bit digital signals, the 8-bit digital signals control the clock input ports S1-S8 to be turned on and off in sequence respectively, and further control the current mode DAC to generate current I DAC2 smaller than I/2, the current I DAC2 generated by the DAC is copied into adjustable current sources I2 and I3 in the same proportion through a cascode current mirror, so that the current sizes of the adjustable current sources I2 and I3 are reduced, A× (V1-V2) is increased, the direct current voltage Vo of the output end of the amplifier OPA2 is increased, then the operation is repeated, so that the output direct current voltage Vo of the amplifier OPA2 is close to VDD/2, after a period of calibration time, the clock clk11 is low, the switch K13 is turned off, the offset calibration operation is finished, the circuit works normally.
S2.2: high frequency hall signal amplifying operation
After the high-frequency path direct current offset calibration operation is finished, the high-frequency circuit can work normally, the frequency of the current flowing in the S-shaped copper rail is larger than the cutoff frequency Fx, two pairs of differential magnetic fields are generated below the S-shaped copper rail and are respectively detected by the differential Hall probes (X1 and X2) of the low-frequency path and the differential Hall probes (X3 and X4) of the high-frequency path, but the high-frequency path normally amplifies the input magnetic field signal because the frequency of the current flowing in the S-shaped copper rail is larger than Fx, the low-frequency path does not amplify the input magnetic field signal, at the moment, the magnitudes of the magnetic field signals detected by the Hall probes (X3 and X4) in the bias circuits N_CS1 and N_CS2 are equal, the directions are opposite, the voltage output by the bias circuit N_CS1 is Vh+V os1 +Vc (Vh is the Hall voltage, vc is an interference voltage caused by a common-mode magnetic field, V os1 is an offset voltage output by a Hall probe X3), the voltage output by a bias circuit N_CS2 is-Vh+V os2+Vc,(Vos2 and is an offset voltage output by a Hall probe X4, the Hall voltage and the offset voltage output by the bias circuit N_CS1 are converted into currents respectively into Ih+I os1+Ic(Ih、Ios1 through a transconductance amplifying circuit GM3, ic is the voltages Vh, V os1 and Vc are converted into the magnitudes of the currents through the transconductance amplifying circuit GM 3), and the Hall voltage and the offset voltage output by the bias circuit N_CS2 are converted into currents respectively into-Ih+I os2+Ic(Ih、Ios2 through a transconductance amplifying circuit GM4, ic is the voltages Vh, V os2 and Vc are converted into the magnitudes of the currents through the transconductance amplifying circuit GM 4; the current output by the transconductance amplifying circuits GM3 and GM4 is 2ih+I os1-Ios2 after being subtracted, the current output by the GM3 and GM4 flows through the resistors R1 and R2 to be converted into the voltage V N_CS＝R1×(2Ih+Ios1-Ios2 after being subtracted, and the resistance values of the resistors R1 and R2 are equal; the Hall voltage V N_CS output by the voltage amplifying circuit is amplified again by the amplifying and offset calibrating circuit for the second time to output the Hall voltage V=A×R1× (2ih+I os1-Ios2); a is the gain of an amplifier OPA2 in the amplifying and offset calibration circuit.
S2.3: matching network circuit operation
The Hall voltage signal V is output by the amplifying and offset calibration circuit through the input ports Vi_h1 and Vi_h2 of the matching network, the input ports Vi_h1 and Vi_h2 are connected with subsequent circuits through input capacitors, so that the effect of a high-pass filter is shown from the input ports Vi_h1 and Vi_h2 of the matching network to the output ports Vout_p and Vout_n of the matching network, the matching network is a high-pass filter for a high-frequency path, the cut-off frequency is Fx=1/(2pi R 5C12), wherein Fx is the cut-off frequency of the matching network, R 5 is the resistance of a resistor R5, C 12 is the capacitance of a capacitor C12, the amplifying and offset calibration circuit outputs a signal V with the frequency larger than Fx, the Hall voltage can be output through the high-pass filter normally, the low-frequency path is connected with the input ports Vi_l1 and Vi_l2 of the matching network, the input ports Vi_l1 and Vi_l2 of the matching network are connected with the subsequent circuits through resistors, the cut-off frequency is Fx=1 and Vout_l2 of the matching network output port of the high-frequency filter, the Fx=1 and Vout_l2 is the cut-off frequency is the filter for the low-frequency filter, the Fx is the same as the low-frequency filter, the whole frequency filter can be the low-frequency filter, the same as the high-frequency filter, the high-frequency filter can be the high frequency filter and the same as the low frequency filter, and the whole gain circuit can be combined with the low frequency filter circuit, the low frequency filter circuit can be the frequency filter circuit, and the high frequency filter circuit can be the frequency filter circuit, and the frequency filter circuit can be the high frequency filter circuit.
The beneficial effects are that:
1. The invention has novel structure and simple realization, the low-frequency channel adopts the current mode dynamic offset elimination and weak Hall current amplification technology, and not only can realize extremely low residual offset and noise, but also can obtain extremely high linearity.
2. The amplifying and offset calibration circuit provided by the invention not only solves the problem that the circuit is not working because of overlarge direct current offset of a high-frequency channel, but also obtains high gain and bandwidth, and the whole circuit has low residual offset.
3. The invention provides a double-channel circuit design scheme adopting a pure Hall device probe, a large-size Rogowski coil and a coupling capacitor are not needed, the integration level of a sensor is improved, the power consumption is reduced, and the bandwidth above the MHz level is obtained.
Drawings
Fig. 1 is a diagram showing the overall circuit configuration of the present invention.
Fig. 2 is a schematic diagram of an on-chip S-shaped copper track layout according to the present invention.
FIG. 3 is a schematic diagram of the operation sequence of the present invention.
Fig. 4 is a schematic diagram of the bandwidth matching principle of the present invention.
Fig. 5 is a schematic diagram of a dynamic rotation circuit according to the present invention. Identification description: a-represents a port of a Hall probe; b-represents the hall probe b port; c-represents the hall probe c port; d-denotes the hall probe d port.
Fig. 6 is a schematic diagram of a current integrating amplifying circuit according to the present invention.
Fig. 7 is a schematic diagram of a related double sampling circuit according to the present invention.
Fig. 8 is a schematic diagram of a voltage amplifying circuit according to the present invention.
Fig. 9 is a schematic diagram of an amplifying and offset calibration circuit according to the present invention. Identification description: (a) represents an amplifying and detuning calibration circuit structure; (b) The circuit structure of the adjustable current source in the amplifying and offset calibration circuit is shown.
Fig. 10 is a schematic diagram of a matching network circuit according to the present invention.
Fig. 11 is a schematic diagram of the overall system bandwidth simulation result of the present invention.
FIG. 12 is a diagram of the overall system step response simulation results of the present invention.
Detailed Description
The following examples will provide those skilled in the art with a more complete understanding of the invention, but are not intended to limit the invention in any way.
Referring to fig. 1, the whole circuit structure diagram of the dual-channel broadband hall current sensor provided by the invention is shown. The invention provides a double-channel broadband Hall current sensor which comprises 1 low-frequency channel, 1 high-frequency channel, 1 matching network, 1 clock generating circuit and 1 on-chip S-shaped copper rail. The low-frequency channel output ports are vo_cds1 and vo_cds2, and the output ports vo_cds1 and vo_cds2 are respectively connected with the input ports vi_l1 and vi_l2 of the matching network circuit. The further high-frequency channel output ports are vo_lo1 and vo_lo2, the output ports are vo_lo1 and vo_lo2 and are respectively connected with the matching network input ports vi_h1 and vi_h2, the matching network output ports are vout_p and vout_n, the further clock generation circuit output ports T1-T4, T5, T6 and T7-T9 are connected with the low-frequency channel clock input ports clk 1-clk 4, clk5, clk6 and clk 7-clk 9, the clock generation circuit output ports T10 and T11 are connected with the high-frequency channel clock input ports clk10 and clk11.
The low-frequency path further comprises a dynamic rotating current circuit, a current integration amplifying circuit and a correlated double sampling circuit, wherein the output port Vo1 of the dynamic rotating current circuit is connected with the input port vi_1 of the current integration amplifying circuit, the output port Vo4 of the dynamic rotating current circuit is connected with the input port vi_1 of the current integration amplifying circuit, the output port Vo2 of the dynamic rotating current circuit is connected with the input port vi_2 of the current integration amplifying circuit, the output ports vo_i1 and vo_i2 of the dynamic rotating current circuit are respectively connected with the input ports vi_cds1 and vi_cds2 of the correlated double sampling circuit, and the output ports vo_cds1 and vo_cds2 of the correlated double sampling circuit are respectively connected with the input ports vi_l1 and vi_l2 of the matched network circuit.
Referring to fig. 5, a schematic diagram of a dynamic rotation circuit in the dual-channel hall current sensor according to the present invention is shown. The dynamic rotating current circuit comprises two rotating current circuits (CS 1 and CS 2) with the same structure and two identical transconductance amplifying circuits (GM 1 and GM 2). Further, the rotating current circuit CS1 includes 16 NMOS tubes M1 to M16, a hall probe X1, and a bias current source Ibias, taking a connection relationship between the rotating current circuit CS1 and the hall probe X1 as an example, drains of the NMOS tubes M1 to M4 are commonly connected to an output end of the input bias current source Ibias, an input end of the bias current source Ibias is connected to a voltage source VDD, gates of the NMOS tubes M1 to M4 are sequentially connected to clock signals clk1 to clk4, and sources of the NMOS tubes M1 to M4 are sequentially connected to an a port, a b port, a d port, and a c port of the hall probe X1, respectively; the sources of the NMOS tubes M5-M8 are commonly connected to GND, the grids of the NMOS tubes M5-M8 are respectively connected to clock signals clk 1-clk 4 in sequence, and the drains of the NMOS tubes M5-M8 are respectively connected to the port a, the port b, the port d and the port c of the Hall probe X1 in sequence; the sources of the NMOS tubes M9-M12 are commonly connected to an external port Vs1, the grids of the NMOS tubes M9-M12 are respectively connected to clock signals clk 1-clk 4 in sequence, and the drains of the NMOS tubes M9-M12 are respectively connected to the c port, the a port, the d port and the b port of the Hall probe in sequence; the sources of the NMOS tubes M13-M16 are commonly connected to an external port Vs2, the grids of the NMOS tubes M13-M16 are respectively connected to clock signals clk 1-clk 4 in sequence, and the drains of the NMOS tubes M13-M16 are respectively connected to the d port, the b port, the c port and the a port of the Hall probe X1 in sequence; all the substrates of the 16 NMOS transistors are grounded. Further, the rotating current circuit CS2 includes 16 NMOS transistors M1 to M16, one hall probe X2, clock signal input ports clk1 to clk4, a bias current source Ibias, and external output ports Vs3, vs4, and the circuit structure of the rotating current circuit CS2 is identical to that of the rotating current circuit CS 1. Further, the output ports Vs1 and Vs2 of the rotating current circuit CS1 are connected to the input ports V1 and V2 of the transconductance amplifying circuit GM1, and the output ports Vs3 and Vs4 of the rotating current circuit CS2 are connected to the input ports V3 and V4 of the transconductance amplifying circuit GM 2.
Referring to fig. 6, a schematic diagram of a current integration amplifying circuit in a dual-channel hall current sensor circuit according to the present invention is shown. The current integration amplifying circuit comprises an amplifier OPA, a capacitor C1, a capacitor C2 and switches K1-K4. Further, the switches K1 and K2 are connected to the clock signal clk5, the switches K3 and K4 are connected to the clock signal clk6, the output ports Vo1 and Vo2 of the transconductance amplifying circuit GM1 are respectively connected to the input ports vi_1 and vi_2 of the current integrating amplifying circuit, the output ports Vo3 and Vo4 of the transconductance amplifying circuit GM2 are respectively connected to the input ports vi_2 and vi_1 of the current integrating amplifying circuit, the input port vi_1 is connected to the in-phase input port of the amplifier OPA through the switch K1, the other port of the switch K1 is respectively connected to the one port of the switch K3 and the one port of the capacitor C1, the other port of the switch K3 and the other port of the capacitor C1 are commonly connected to the inverting output port vo_i1 of the amplifier OPA, the other port vi_2 is connected to the inverting input port of the amplifier OPA through the switch K2, and the other port of the switch K2 is respectively connected to the one port of the switch K4 and the one port of the capacitor C2, and the other port of the switch K4 and the other port of the capacitor C2 are commonly connected to the in-phase output port vo_i2 of the amplifier OPA.
Referring to fig. 7, a schematic diagram of a related double sampling circuit in a dual-channel hall current sensor according to the present invention is shown. The correlated double sampling circuit comprises an amplifier OPA1, capacitors C3-C8 and switches K5-K12. The switches K5, K6, K9 and K10 are commonly connected with the clock signal clk7, the switches K7 and K11 are commonly connected with the clock signal clk8, and the switches K8 and K12 are commonly connected with the clock signal clk9. The input port vi_cds1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with the operational amplifier output port Vn of the amplifier OPA1 through a switch K5, and is also connected with one end of a capacitor C4, the other end of the capacitor C4 is not only connected with the ground through a switch K6, but also connected with the operational amplifier output port Vn of the amplifier OPA1 through a switch K7, the operational amplifier output port Vn of the amplifier OPA1 is connected with one end of the capacitor C5 through a switch K8 and serves as an output port vo_cds1, and the other end of the capacitor C5 is connected with the ground. The input port vi_cds2 is connected with one end of a capacitor C6, the other end of the capacitor C6 is connected with the output port Vp of the amplifier OPA1 through a switch K9, and is also connected with one end of a capacitor C7, the other end of the capacitor C7 is not only connected with the ground through a switch K11, but also connected with the output port Vp of the amplifier OPA1 through a switch K10, the output port Vp of the amplifier OPA1 is connected with one end of a capacitor C8 through a switch K12 and serves as an output port vo_cds2, and the other end of the capacitor C8 is connected with the ground.
Referring to fig. 1, the whole circuit structure diagram of the dual-channel broadband hall current sensor provided by the invention is shown. The high-frequency path comprises two bias circuits (N_CS 1 and N_CS 2) with the same structure, a voltage amplifying circuit and an amplifying and offset calibrating circuit. The bias circuit output ports Vno1, vno2, vno3 and Vno4 are connected with the voltage amplifying circuit input ports vi_ns1, vi_ns2, vi_ns3 and vi_ns4, the voltage amplifying circuit output ports vo_ns1 and vo_ns2 are respectively connected with the amplifying and offset calibration circuit input ports vi_lo1 and vi_lo2, and the amplifying and offset calibration circuit output ports vo_lo1 and vo_lo2 are connected with the matching network input ports vi_h1 and vi_h2. The bias circuit N_CS1 comprises a Hall probe X3 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X3, a port d of the Hall probe X3 is grounded, a port c of the Hall probe X3 is an output port Vno1 and a port c of the Hall probe X2, the output ports Vno1 and Vno2 are respectively connected with the input ports Vi_ns1 and Vi_ns2 of the voltage amplifying circuit, the bias circuit N_CS2 comprises a Hall probe X4 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X4, a port d of the Hall probe X3 is grounded, a port c of the Hall probe X4 is an output port Vno3 and a port v no4, and the output ports Vno3 and Vno4 are respectively connected with the input ports Vi_ns3 and Vi_ns4 of the voltage amplifying circuit.
Referring to fig. 8, a schematic diagram of a voltage amplifying circuit in a dual-channel hall current sensor according to the present invention is shown. The voltage amplifying circuit comprises transconductance amplifying circuits GM3 and GM4, a resistor R1 and a resistor R2. The in-phase output port of the transconductance amplifying circuit GM3 and the anti-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns1, the anti-phase output port of the transconductance amplifying circuit GM3 and the in-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns2, the output ports vo_ns1 and vo_ns2 are respectively connected with one port of the resistor R1 and one port of the resistor R2, and the other ports of the resistor R1 and the resistor R2 are respectively grounded.
Referring to fig. 9, a schematic diagram of an amplifying and offset calibration circuit in a dual-channel hall current sensor according to the present invention is shown. The amplifying and offset calibrating circuit comprises an amplifier OPA2, an analog-to-digital converter ADC, a current mode DAC, fixed current sources I1 and I4, adjustable current sources I2 and I3 and a switch K13. The input port Vi_lo1 is connected with the input port VIP of the amplifier OPA2, the input port VIP of the amplifier OPA2 is respectively connected with a regulatable current source I2 and a fixed current source I1 in series, the input port Vi_lo2 is connected with the input port VIN of the amplifier OPA2, the input port VIN of the amplifier OPA2 is respectively connected with a regulatable current source I3 and a fixed current source I4 in series, the output port Vo of the amplifier OPA2 is connected with the ADC through a switch K13, the switch K13 is connected with a clock signal clk11, the further current mode DAC comprises 17 PMOS tubes M1-M17, 9 PMOS tubes M24-M32, 9 clock signal input ports S0-S8 (the clock signal connected with the input port S0 is clk10, the clock signal connected with the input port S1-S8 is an 8-bit digital signal output by the ADC), the further regulatable current source I2 comprises 6 NMOS tubes M33-M38, the regulatable current source I3 comprises 4 PMOS tubes M18-M21, the further band gap reference output port Ierf is connected with the source of M22, the M0 tube, the M9 tube, the M22 tube and the M23 tube form a common source common grid structure, the grid electrodes of the M22 tube and the M0 tube are commonly connected with the drain electrode of the M22 tube, the drain electrode of the M22 tube is connected with the source electrode of the M23 tube, the grid electrodes of the M23 tube and the M9 tube are commonly connected with the drain electrode of the M23 tube, the drain electrode of the M23 tube is connected with GND, the source electrodes of the PMOS tubes M0-M8 tube are commonly connected with the grid electrodes of the M22 tube, the source electrodes of the PMOS tubes M9-M17 are respectively connected with the drain electrodes of the PMOS tubes M0-M8, the source electrodes of the PMOS tubes M24-M32 are respectively connected with the drain electrodes of the PMOS tubes M9-M17, the drain electrodes of the PMOS tubes M24-M32 are respectively connected with the clock signals S0-S8, the M33-M35 tube forms a common source common grid structure, the grid electrodes of the M34 tube and the M35 tube are commonly connected with the drain electrode of the M34 tube, the M34 tube and the M35 tube are respectively connected with the drain electrode of the M33-M36 tube, the M34 tube and the M35 tube are connected with the M34 tube drain electrode together, the M33 tube and the M36 tube source electrode are connected with the GND together, the M33 tube and the M36 tube gate electrode are connected with the M33 tube drain electrode together, the M37 tube gate electrode is connected with the M34 tube gate electrode, the M37 tube drain electrode is an output port of the adjustable current source I2, the M38 tube gate electrode is connected with the M33 tube gate electrode, the M38 tube source electrode is grounded, the M35 tube drain electrode is connected with the M19 tube drain electrode, the NMOS tubes M18-M20 form a common source common gate structure, the M19 tube and the M21 tube gate electrode are connected with the M19 tube drain electrode together, the M19 tube source electrode and the M21 tube source electrode are connected with the M18 tube drain electrode and the M20 tube drain electrode respectively, the M18 tube source electrode and the M20 tube source electrode are connected with the power supply voltage VDD together, the M21 tube drain electrode outputs the adjustable current source I3, and the substrates of the 32 PMOS tubes M1-M32 and the 6 NMOS tubes M33-M37 are grounded.
Referring to fig. 10, a schematic diagram of a matching circuit in a dual-channel hall current sensor according to the present invention is shown. The matching network comprises capacitors C10-C13, resistors R3-R6 and an amplifier OPA3. The input ports vi_h1 and vi_h2 are respectively connected with one port of the capacitors C10 and C11, the input ports vi_l1 and vi_l2 are respectively connected with one port of the resistors R3 and R4, the other ports of the capacitor C10 and the resistor R4 are commonly connected with the inverting input end of the amplifier OPA3, the other ports of the capacitor C11 and the resistor R3 are commonly connected with the non-inverting input end of the amplifier OPA3, the non-inverting end of the amplifier OPA3 is commonly connected with the resistor R5, one port of the capacitor C12, the resistor R5 and the other port of the capacitor C12 are commonly connected with the inverting output port vout_p of the amplifier OPA3, the inverting end of the amplifier OPA3 is simultaneously connected with the resistor R6, one port of the capacitor C13, and the other port of the capacitor C13 is commonly connected with the non-inverting output port vout_n of the amplifier OPA3.
Referring to fig. 2, an on-chip S-shaped copper track layout of the dual-channel hall current sensor according to the present invention is shown. The S-shaped copper rail on the chip is designed into an S-shaped current-carrying copper rail by adopting a top layer thick metal above the integrated Hall probe, one end of the S-shaped copper rail flows in current, the other end of the S-shaped copper rail is provided with a current outflow port, two pairs of differential Hall probes, namely Hall probes (X1 and X2) and Hall probes (X3 and X4), are respectively placed at the corners of the S-shaped copper rail, the two pairs of differential Hall probes are used as Hall probes of a high-frequency channel and a low-frequency channel of the current sensor, when the S-shaped copper rail flows in current, two pairs of identical differential magnetic fields (differential magnetic field 1 and differential magnetic field 2) are generated below the S-shaped copper rail, the differential magnetic field 1 is detected by the Hall probes (X1 and X2) in the same size and opposite directions, and the differential magnetic field 2 is detected by the Hall probes (X3 and X4).
Referring to fig. 4, a schematic diagram of a bandwidth matching principle in a dual-channel hall current sensor according to the present invention is shown. In the further two-channel broadband hall current sensor circuit, the low-frequency channel output ports vo_cds1 and vo_cds2 are connected with the input ports vi_l1 and vi_l2 of the matching network, and the input ports vi_l1 and vi_l2 are connected with the subsequent circuit by resistors, so that the matching network is a low-pass filter for the low-frequency channel, the cut-off frequency is fx=1/(2pi R 5C12), fx is the cut-off frequency of the matching network, R 5 is the resistor of the resistor R5, C 12 is the capacitor of the capacitor C12, the high-frequency channel output ports vo_l1 and vo_l2 are connected with the input ports vi_h1 and vi_h2 of the matching network, and the input ports vi_h1 and vi_h2 are connected with the subsequent circuit by capacitors, and therefore the matching network is a high-pass filter for the high-frequency channel, the cut-off frequency is fx=1/(2pi R 5C12), wherein Fx is the cut-off frequency of the matching network, R 5 is the resistor of the resistor R5, C 12 is the capacitor C12, the low-frequency signal and the low-frequency signal can be combined with the low-frequency gain circuit, and the gain circuit can be increased together.
Referring to fig. 3, a working time sequence diagram of the two-channel hall current sensor circuit provided by the invention is combined with the working time sequence diagram, and the working method applied to the two-channel broadband hall current sensor circuit is as follows:
s1: the frequency of the current flowing in the S-shaped copper rail is smaller than the cut-off frequency Fx
S1.1: four-phase rotation modulation operation of hall signal polarity and offset signal polarity
When the frequency of the S-shaped copper rail inflow current is smaller than the cutoff frequency Fx, two pairs of differential magnetic fields are generated below the S-shaped copper rail and detected by differential Hall probes (X1 and X2) of a low-frequency path and differential Hall probes (X3 and X4) of a high-frequency path respectively, but because the frequency of the S-shaped copper rail inflow current is smaller than the cutoff frequency Fx, the low-frequency path can normally amplify an input signal, the high-frequency path does not amplify the input signal, at the moment, when the first phase operation of a dynamic rotating current circuit is carried out, the clock input clk1 of the dynamic rotating current circuit is high level, other clock inputs are all low level, the differential magnetic field signals detected by the Hall probe X1 in the rotating current circuit CS1 and the Hall probe X2 in the rotating current circuit CS2 are equal in size, the directions are opposite, the voltage output by the rotating current circuit CS1 is Vh+V os11 +Vc (Vh is Hall voltage, vc is interference voltage brought by a common-mode magnetic field, V os11-Vos14 is offset voltage output by the Hall probe X1 first phase to a fourth phase rotating current circuit), and the rotating current CS2 is output by the fourth phase rotating circuit is offset voltage os21+Vc(Vos21-Vos24; when the second phase operation of the dynamic rotating current circuit is carried out, the clock input clk2 of the dynamic rotating current circuit is high level, all other clock inputs are low level, the voltage output by the rotating current circuit CS1 is Vh-V os12 +Vc, and the voltage output by the rotating current circuit CS2 is-Vh-V os22 +Vc; when the third phase operation of the dynamic rotating current circuit is performed, the clock input clk3 of the dynamic rotating current circuit is at a high level, all other clock inputs are at a low level, the voltage output by the rotating current circuit CS1 is-Vh+V os13 +Vc, and the voltage output by the rotating current circuit CS2 is Vh+V os23 +Vc; when the fourth phase operation of the dynamic rotating current circuit is performed, the clock input clk4 of the dynamic rotating current circuit is at a high level, all other clock inputs are at a low level, the voltage output by the rotating current circuit CS1 is Vh-V os14 +Vc, and the voltage output by the rotating current circuit CS2 is Vh-V os24 +Vc; the four-phase Hall voltage and offset voltage output by CS1 are converted into currents of Ih+I os11+Ic、Ih-Ios12+Ic、-Ih+Ios13+Ic、-Ih-Ios14 +ic (the currents Ih, I os11-Ios14 and Ic are voltages Vh, V os11-Vos14 and Vc are converted into currents through a transconductance amplifying circuit GM 1) through a transconductance amplifying circuit GM1, the aliasing signal of the four-phase Hall voltage and offset voltage output by CS2 is converted into currents of-Ih+I os21+Ic、-Ih-Ios22+Ic、Ih+Ios23+Ic、Ih-Ios24 +ic (the currents Ih, I os21-Ios24 and Ic are voltages Vh, V os21-Vos24 and Vc are converted into currents through the transconductance amplifying circuit GM 1) through a transconductance amplifying circuit GM1, and then each phase Hall current and offset current output by the transconductance amplifying circuit GM1 and each phase Hall current and offset current output by the transconductance amplifying circuit GM1 are subtracted to obtain new four-phase Hall current and offset current 2Ih+Ios11-Ios21、2Ih-Ios12+Ios22、-2Ih+Ios13-Ios23、-2Ih-Ios14+Ios24.
S1.2: operation of integrating and amplifying Hall current into Hall voltage
When the clock signal clk1, clk2 is effective at high level, the current outputted by the transconductance amplifying circuits GM1 and GM2 is subtracted to obtain the hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22 of the first phase and the second phase, when the clock signal clk5 is effective at high level, the hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22 of the first phase and the second phase are sent to the current integrating amplifying circuit to operate, because the polarities of the hall currents outputted by the first phase and the second phase rotating current circuits are positive, the polarities of offset currents are opposite, the offset currents after being sent to the current integrating amplifying circuit are offset, the hall currents are mutually overlapped, the obtained output hall voltage is V 1-2＝4Vh+Vos1-2, wherein 4Vh is the hall voltage outputted by integrating and amplifying the hall current Ih, vos 1-2 is the residual voltage after integrating and amplifying the first phase and the second phase offset current, and then when the clock signal clk6 is effective at high level, the voltage on the integrating capacitors C1 and C2 is cleared.
When the clock signal clk3 and clk4 are effective in high level, the currents outputted by the transconductance amplifying circuits GM1 and GM2 are subtracted to obtain hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 in the third phase and the fourth phase, when the clock signal clk5 is effective in high level, the hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 in the third phase and the fourth phase are subjected to current integration operation, as the polarities of the hall currents outputted by the third phase and the fourth phase are both negative, the polarities of offset currents are changed in opposite directions, the offset currents are offset after being fed into the current integration amplifying circuits, the hall currents are mutually overlapped, the obtained output hall voltage is V 3-4＝-4Vh+Vos3-4, wherein-4 Vh is the hall voltage outputted after the hall currents Ih are integrated and amplified, vos 3-4 is the residual offset voltage after the third phase and the fourth phase offset currents are integrated and amplified, and then when the clock signal clk6 is effective in high level, the voltages on the integrating capacitors C1 and C2 are cleared.
S1.3: hall voltage sample-and-hold operation
When the clock control signal clk7 of the related double sampling circuit is valid in a high level, the related double sampling circuit performs first sampling and holding on the output Hall voltage of the current integrating amplifying circuit as V 1-2＝4Vh+Vos1-2; when the clock control signal clk8 of the correlated double sampling circuit is valid at a high level, the correlated double sampling circuit performs a second sample hold on the output hall voltage V 3-4＝-4Vh+Vos3-4 of the current integration amplifying circuit, and when the clock signal clk9 is valid at a high level, the correlated double sampling circuit subtracts the voltage value V 3-4 of the second sample hold from the voltage value V 1-2 of the first sample hold to obtain the output hall voltage signal vout=v 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4.
S1.4: filtering high-frequency harmonic operation:
the Hall voltage obtained by subtracting the two samples passes through input ports Vi_l1 and Vi_l2 of the matching network, and because the input ports Vi_l1 and Vi_l2 are respectively connected with resistors, a low-pass filter is formed with a subsequent connecting circuit, the low-pass filter in the matching network filters high-frequency harmonic components, finally, a Hall voltage signal is output, and offset signals are effectively eliminated, so that an output Hall voltage signal Vout=V 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4 is obtained.
S2: the frequency of the current flowing into the S-shaped copper rail is larger than the cut-off frequency Fx
S2.1: high frequency path DC offset calibration operation
Because the high-frequency channel does not adopt a signal polarity modulation method to eliminate direct current offset in order to realize high bandwidth, the direct current offset of the high-frequency channel is larger, and the high-frequency channel possibly cannot work normally, so before detecting a high-frequency magnetic field signal, the direct current offset calibration of the high-frequency channel is carried out, at the moment, an S-shaped copper rail does not flow in current, a magnetic field is not generated around the S-shaped copper rail, no magnetic field signal is input, a clock input port clk10 is high level, clk11 is low level, clock input ports S1-S8 are low level, at the moment, a band gap reference generates current I, the current I is copied into adjustable current sources I2 and I3 respectively through a common-source common-gate current mirror in the same proportion, the current sizes of the adjustable current sources I2 and I3 are I, the current sizes of fixed current sources I1 and I4 are I f, the current difference between the adjustable current source I2 and the fixed current source I1 generates a direct current voltage V1= (I f -I) x R1 on a resistor R1, the current difference between the adjustable current source I3 and the fixed current source I4 generates a direct current voltage V2= (I-I f) x R2 on a resistor R2, the resistance of the resistor R1 and the resistance of the resistor R2 are equal, at this time, the differential direct current voltage of the input ends VIP and VIN of the amplifier OPA2 is V1-V2, the direct current voltage vo=A x (V1-V2) +V3 of the output end of the amplifier OPA2, wherein A is the gain size of the amplifier OPA2, A x (V1-V2) is the direct current voltage amplified by the amplifier OPA2, V3 is the direct current voltage output by the amplifier OPA2 when the differential direct current voltage is not input by the amplifier OPA2, when the clock input port clk10 is low and clk11 is high, the dc offset calibration operation is started, and the dc offset calibration principle is as follows: if the dc voltage Vo at the output end of the amplifier OPA2 is greater than VDD/2 (VDD/2 is the dc voltage at the output end of the amplifier OPA2 during normal operation), the ADC quantizes the voltage at the output end Vo of the amplifier OPA2 and outputs an 8-bit digital signal, which sequentially controls the on and off of the clock input ports S1-S8 respectively, and further controls the current mode DAC to generate a current I DAC1 larger than I/2 (the current I/2 is the current generated by the current mode DAC after the ADC quantized voltage vo=VDD/2), the current I DAC1 generated by the DAC is copied into the adjustable current sources I2 and I3 in the same proportion through the cascode current mirror, so that the current sizes of the adjustable current sources I2 and I3 are increased, A× (V1-V2) is reduced, the direct current voltage Vo at the output end of the amplifier OPA2 is reduced, if the output end direct current voltage Vo of the amplifier OPA2 is smaller than VDD/2, the ADC quantizes the output end Vo of the amplifier OPA2 and outputs 8-bit digital signals, the 8-bit digital signals control the clock input ports S1-S8 to be turned on and off in sequence respectively, and further control the current mode DAC to generate current I DAC2 smaller than I/2, the current I DAC2 generated by the DAC is copied into adjustable current sources I2 and I3 in the same proportion through a cascode current mirror, so that the current sizes of the adjustable current sources I2 and I3 are reduced, A× (V1-V2) is increased, the direct current voltage Vo of the output end of the amplifier OPA2 is increased, then the operation is repeated, so that the output direct current voltage Vo of the amplifier OPA2 is close to VDD/2, after a period of calibration time, the clock clk11 is low, the switch K13 is turned off, the offset calibration operation is finished, the circuit works normally.
S2.2: high frequency hall signal amplifying operation
After the high-frequency path direct current offset calibration operation is finished, the high-frequency circuit can work normally, the frequency of the current flowing in the S-shaped copper rail is larger than the cutoff frequency Fx, two pairs of differential magnetic fields are generated below the S-shaped copper rail and are respectively detected by differential Hall probes (X1 and X2) of the low-frequency path and differential Hall probes (X3 and X4) of the high-frequency path, but the high-frequency path normally amplifies an input magnetic field signal and the low-frequency path does not amplify the input magnetic field signal because the frequency of the current flowing in the S-shaped copper rail is larger than Fx, at the moment, the magnetic field signals detected by the Hall probes (X3 and X4) in the bias circuits N_CS1 and N_CS2 are equal in size and opposite in direction, the voltage output by the bias circuit N_CS1 is Vh+V os1 +Vc (Vh is Hall voltage), vc is an interference voltage caused by a common-mode magnetic field, V os1 is an offset voltage output by a Hall probe X3), the voltage output by a bias circuit N_CS2 is-Vh+V os2+Vc,(Vos2 and is an offset voltage output by a Hall probe X4, the Hall voltage and the offset voltage output by the bias circuit N_CS1 are converted into currents respectively into Ih+I os1+Ic(Ih、Ios1 through a transconductance amplifying circuit GM3, ic is the voltages Vh, V os1 and Vc are converted into the magnitudes of the currents through the transconductance amplifying circuit GM 3), and the Hall voltage and the offset voltage output by the bias circuit N_CS2 are converted into currents respectively into-Ih+I os2+Ic(Ih、Ios2 through a transconductance amplifying circuit GM4, ic is the voltages Vh, V os2 and Vc are converted into the magnitudes of the currents through the transconductance amplifying circuit GM 4; the current output by the transconductance amplifying circuits GM3 and GM4 is 2ih+I os1-Ios2 after being subtracted, the current output by the GM3 and GM4 flows through the resistors R1 and R2 to be converted into the voltage V N_CS＝R1×(2Ih+Ios1-Ios2 after being subtracted, and the resistance values of the resistors R1 and R2 are equal; the Hall voltage V N_CS output by the voltage amplifying circuit is amplified again by the amplifying and offset calibrating circuit for the second time to output the Hall voltage V=A×R1× (2ih+I os1-Ios2); a is the gain of an amplifier OPA2 in the amplifying and offset calibration circuit.
S2.3: matching network circuit operation
The Hall voltage signal V is output by the amplifying and offset calibration circuit through the input ports Vi_h1 and Vi_h2 of the matching network, the input ports Vi_h1 and Vi_h2 are connected with subsequent circuits through input capacitors, so that the effect of a high-pass filter is shown from the input ports Vi_h1 and Vi_h2 of the matching network to the output ports Vout_p and Vout_n of the matching network, the matching network is a high-pass filter for a high-frequency path, the cut-off frequency is Fx=1/(2pi R 5C12), wherein Fx is the cut-off frequency of the matching network, R 5 is the resistance of a resistor R5, C 12 is the capacitance of a capacitor C12, the amplifying and offset calibration circuit outputs a signal V with the frequency larger than Fx, the Hall voltage can be output through the high-pass filter normally, the low-frequency path is connected with the input ports Vi_l1 and Vi_l2 of the matching network, the input ports Vi_l1 and Vi_l2 of the matching network are connected with the subsequent circuits through resistors, the cut-off frequency is Fx=1 and Vout_l2 of the matching network output port of the high-frequency filter, the Fx=1 and Vout_l2 is the cut-off frequency is the filter for the low-frequency filter, the Fx is the same as the low-frequency filter, the whole frequency filter can be the low-frequency filter, the same as the high-frequency filter, the high-frequency filter can be the high frequency filter and the same as the low frequency filter, and the whole gain circuit can be combined with the low frequency filter circuit, the low frequency filter circuit can be the frequency filter circuit, and the high frequency filter circuit can be the frequency filter circuit, and the frequency filter circuit can be the high frequency filter circuit.
Examples: according to the technical scheme shown in fig. 1, a signal conditioning circuit (comprising a dynamic rotating current circuit, a current integration amplifying circuit, a related double sampling circuit, a bias circuit, an amplifying and offset calibrating circuit and a matching network and a clock generating circuit) of a dual-channel hall current sensor is preliminarily designed by adopting a SMIC 0.18 mu m standard CMOS process, a hall probe model is designed by adopting Verilog-A, then the signal conditioning circuit of the dual-channel hall current sensor is simulated, the amplitude-frequency characteristic curve obtained by simulating the signal conditioning circuit is shown in fig. 11, the bandwidth reaches 3MHz, the high bandwidth requirement is met, when a high-frequency current signal is detected, a 40mT magnetic field signal is input into a signal input port of the hall probe model, the rising time is 100ps, the abrupt magnetic field generated by the high-frequency current signal is simulated, the step response time of the output hall voltage of the signal conditioning circuit is 450ns, and the purpose of rapid overcurrent detection can be seen from fig. 12.
The above technical process is only a preferred embodiment of the present invention, but not represents all the details of the present invention. Any modification, equivalent replacement, and improvement made by those skilled in the art within the scope of the present disclosure, which is within the spirit and principles of the present invention, should be included in the scope of the present invention.
Claims (6)
1. The double-channel broadband Hall current sensor is characterized by comprising 1 low-frequency channel, 1 high-frequency channel, 1 matching network, 1 clock generation circuit and 1 on-chip S-shaped copper rail; the low-frequency channel output ports are vo_cds1 and vo_cds2, and are respectively connected with the matching network input ports Vi_l1 and Vi_l2; the high-frequency channel output ports are vo_l1 and vo_l2, are respectively connected with the matching network input ports Vi_h1 and Vi_h2, the matching network input ports are Vi_l1, vi_l2, vi_h1 and Vi_h2, and the output ports are Vout_p and Vout_n; the output ports T1-T4, T5, T6 and T7-T9 of the clock generation circuit are connected with the low-frequency channel clock input ports clk 1-clk 4, clk5, clk6 and clk 7-clk 9, and the output ports T10 and T11 of the clock generation circuit are connected with the high-frequency channel clock input ports clk10 and clk11;
The low-frequency path comprises a dynamic rotating current circuit, a current integration amplifying circuit and a correlated double sampling circuit; the dynamic rotation current circuit output ports Vo1 and Vo4 are commonly connected with the current integration amplifying circuit input port vi_1, the dynamic rotation current circuit output ports Vo2 and Vo3 are commonly connected with the current integration amplifying circuit input port vi_2, the current integration amplifying circuit output ports vo_i1 and vo_i2 are respectively connected with the correlated double sampling circuit input ports vi_cds1 and vi_cds2, and the correlated double sampling circuit output ports vo_cds1 and vo_cds2 are respectively connected with the matching network circuit input ports vi_l1 and vi_l2;
The dynamic rotating current circuit comprises two rotating current circuits (CS 1 and CS 2) with the same structure and two identical transconductance amplifying circuits (GM 1 and GM 2); the rotating current circuit CS1 comprises 16 NMOS tubes M1-M16, a Hall probe X1 and a bias current source Ibias, wherein the drains of the NMOS tubes M1-M4 are commonly connected to the output end of the input bias current source Ibias, the input end of the bias current source Ibias is connected with a voltage source VDD, the grids of the NMOS tubes M1-M4 are respectively connected to clock signal input ports clk 1-clk 4in sequence, and the sources of the NMOS tubes M1-M4 are respectively connected with an a port, a b port, a d port and a c port of the Hall probe X1 in sequence; the sources of the NMOS tubes M5-M8 are commonly connected to GND, the grids of the NMOS tubes M5-M8 are respectively connected to the clock signal input ports clk 1-clk 4in sequence, and the drains of the NMOS tubes M5-M8 are respectively connected to the port a, the port b, the port d and the port c of the Hall probe X1 in sequence; the sources of the NMOS tubes M9-M12 are commonly connected to an external port Vs1, the grids of the NMOS tubes M9-M12 are respectively connected to clock signals clk 1-clk 4in sequence, and the drains of the NMOS tubes M9-M12 are respectively connected to the c port, the a port, the d port and the b port of the Hall probe in sequence; the sources of the NMOS tubes M13-M16 are commonly connected to an external port Vs2, the grids of the NMOS tubes M13-M16 are respectively and sequentially connected to clock signal input ports clk 1-clk 4, and the drains of the NMOS tubes M13-M16 are respectively and sequentially connected to a d port, a b port, a c port and an a port of the Hall probe X1; the substrates of the NMOS tubes M1-M16 are grounded; the rotating current circuit CS2 comprises 16 NMOS tubes M1-M16, a Hall probe X2, clock signal input ports clk 1-clk 4, a bias current source Ibias and external output ports Vs3 and Vs4, and the circuit structure of the rotating current circuit CS2 is consistent with that of the rotating current circuit CS 1; output ports Vs1 and Vs2 of the rotating current circuit CS1 are connected with input ports V1 and V2 of the transconductance amplifying circuit GM1, and output ports Vs3 and Vs4 of the rotating current circuit CS2 are connected with input ports V3 and V4 of the transconductance amplifying circuit GM 2;
The current integration amplifying circuit comprises an amplifier OPA, a capacitor C1, a capacitor C2, a switch K1-switch K4; the switches K1 and K2 are connected with a clock signal clk5, the switches K3 and K4 are connected with a clock signal clk6, the output ports Vo1 and Vo2 of the transconductance amplifying circuit GM1 are respectively connected with the input ports vi_1 and vi_2 of the current integrating amplifying circuit, the output ports Vo3 and Vo4 of the transconductance amplifying circuit GM2 are respectively connected with the input ports vi_2 and vi_1 of the current integrating amplifying circuit, the input port vi_1 is connected with the in-phase input port of the amplifier OPA through the switch K1, the other port of the switch K1 is respectively connected with one port of the switch K3 and one port of the capacitor C1, the other port of the switch K3 and the other port of the capacitor C1 are commonly connected with the inverting output port vo_i1 of the amplifier OPA, the other port of the switch K2 is respectively connected with one port of the switch K4 and one port of the capacitor C2, and the other port of the switch K4 and the other port of the capacitor C2 are commonly connected with the in-phase output port vo_i2 of the amplifier OPA;
The related double sampling circuit comprises an amplifier OPA1, capacitors C3-C8 and switches K5-K12; the switches K5, K6, K9 and K10 are commonly connected with the clock signal clk7, the switches K7 and K11 are commonly connected with the clock signal clk8, and the switches K8 and K12 are commonly connected with the clock signal clk9; the input port Vi_cds1 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with an output port Vn of an amplifier OPA1 through a switch K5 and one end of a capacitor C4, the other end of the capacitor C4 is connected with the ground through a switch K6 and the output port Vn of the amplifier OPA1 through a switch K7, the output port Vn of the amplifier OPA1 is connected with one end of the capacitor C5 through a switch K8 and serves as an output port vo_cds1, and the other end of the capacitor C5 is connected with the ground; the input port Vi_cds2 is connected with one end of a capacitor C6, the other end of the capacitor C6 is connected with an output port Vp of an amplifier OPA1 through a switch K9 and one end of a capacitor C7, the other end of the capacitor C7 is connected with the ground through a switch K11 and the output port Vp of the amplifier OPA1 through a switch K10, the output port Vp of the amplifier OPA1 is connected with one end of a capacitor C8 through a switch K12 and serves as an output port vo_cds2, and the other end of the capacitor C8 is connected with the ground;
The high-frequency path comprises two bias circuits (N_CS 1 and N_CS 2) with the same structure, a voltage amplifying circuit and an amplifying and offset calibrating circuit; the bias circuit output ports Vno1, vno2, vno3 and Vno4 are connected with the voltage amplification circuit input ports vi_ns1, vi_ns2, vi_ns3 and vi_ns4, the voltage amplification circuit output ports vo_ns1 and vo_ns2 are respectively connected with the amplification and offset calibration circuit input ports vi_lo1 and vi_lo2, and the amplification and offset calibration circuit output ports vo_lo1 and vo_lo2 are connected with the matching network input ports vi_h1 and vi_h2;
The bias circuit N_CS1 comprises a Hall probe X3 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X3, a port d of the Hall probe X3 is grounded, a port c of the Hall probe X3 is an output port Vno1 and a port c of the Hall probe X2, the output ports Vno1 and Vno2 are respectively connected with input ports Vi_ns1 and Vi_ns2 of the voltage amplifying circuit, the bias circuit N_CS2 comprises a Hall probe X4 and a bias current Ibias end, the bias current Ibias flows in from a port b of the Hall probe X4, a port d of the Hall probe X3 is grounded, a port c port a of the Hall probe X4 is an output port Vno3 and a port v no4, and the output ports Vno3 and Vno4 are respectively connected with input ports Vi_ns3 and Vi_ns4 of the voltage amplifying circuit; the voltage amplifying circuit comprises transconductance amplifying circuits GM3 and GM4, a resistor R1 and a resistor R2; the in-phase output port of the transconductance amplifying circuit GM3 and the anti-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns1, the anti-phase output port of the transconductance amplifying circuit GM3 and the in-phase output port of the transconductance amplifying circuit GM4 are connected together to form an output port vo_ns2, the output ports vo_ns1 and vo_ns2 are respectively connected with one port of the resistor R1 and one port of the resistor R2, and the other ports of the resistor R1 and the resistor R2 are respectively grounded;
The amplifying and offset calibration circuit comprises an amplifier OPA2, an analog-to-digital converter ADC, a current mode DAC, fixed current sources I1 and I4, adjustable current sources I2 and I3 and a switch K13; the input port Vi_lo1 is connected with the input port VIP of the amplifier OPA2, the input port VIP of the amplifier OPA2 is respectively connected with a regulatable current source I2 and a fixed current source I1 in series, the input port Vi_lo2 is connected with the input port VIN of the amplifier OPA2, the input port VIN of the amplifier OPA2 is respectively connected with a regulatable current source I3 and a fixed current source I4 in series, the output port Vo of the amplifier OPA2 is connected with the ADC through a switch K13, the switch K13 is connected with a clock signal clk11, the current mode DAC comprises 17 PMOS tubes M1-M17, 9 PMOS tubes M24-M32, 9 clock signal input ports S0-S8 (the clock signal connected with the input port S0 is clk10, the clock signal connected with the input port S1-S8 is an 8-bit digital signal output by the ADC), the regulatable current source I2 comprises 6 NMOS tubes M33-M38, the regulatable current source I3 comprises 4 PMOS tubes M18-M21, the band gap reference output port Ierf is connected with the source of M22, the M0 tube, the M9 tube, the M22 tube and the M23 tube form a common source common grid structure, the grid electrodes of the M22 tube and the M0 tube are commonly connected with the drain electrode of the M22 tube, the drain electrode of the M22 tube is connected with the source electrode of the M23 tube, the grid electrodes of the M23 tube and the M9 tube are commonly connected with the drain electrode of the M23 tube, the drain electrode of the M23 tube is connected with GND, the source electrodes of the PMOS tubes M0-M8 tube are commonly connected with the grid electrodes of the M22 tube, the source electrodes of the PMOS tubes M9-M17 are respectively connected with the drain electrodes of the PMOS tubes M0-M8, the source electrodes of the PMOS tubes M24-M32 are respectively connected with the drain electrodes of the PMOS tubes M9-M17, the drain electrodes of the PMOS tubes M24-M32 are respectively connected with the clock signals S0-S8, the M33-M35 tube forms a common source common grid structure, the grid electrodes of the M34 tube and the M35 tube are commonly connected with the drain electrode of the M34 tube, the M34 tube and the M35 tube are respectively connected with the drain electrode of the M33-M36 tube and the drain electrode of the M35 tube, the M33 tube and the M36 tube source are jointly connected with GND, the M33 tube and the M36 tube grid are jointly connected with the M33 tube drain, the M37 tube grid is connected with the M34 tube grid, the M37 tube source is connected with the M38 tube drain, the M37 tube drain is an output port of the adjustable current source I2, the M38 tube grid is connected with the M33 tube grid, the M38 tube source is grounded, the M35 tube drain is connected with the M19 tube drain, NMOS tubes M18-M20 form a common source common grid structure, the M19 tube and the M21 tube grid are jointly connected with the M19 tube drain, the M19 tube and the M21 tube source are respectively connected with the M18 tube and the M20 tube drain, the grid of the M18 tube and the M20 tube is jointly connected with the M18 tube drain, the source of the M18 tube and the M20 tube source is jointly connected with the power voltage VDD, the M21 tube drain outputs the adjustable current source I3, and the substrates of 32 PMOS tubes M1-M32 and 6 NMOS tubes M33-M37 are grounded.
2. The dual-channel broadband hall current sensor according to claim 1, wherein the matching network comprises capacitors C10 to C13, resistors R3 to R6, and an amplifier OPA3, input ports vi_h1, vi_h2, vi_l1, vi_l2 are respectively connected with one port of the capacitors C10, C11, and the resistors R3, R4 in sequence, the other ports of the capacitors C10 and R4 are commonly connected with an inverting input terminal of the amplifier OPA3, the other ports of the capacitors C11 and R3 are commonly connected with an inverting input terminal of the amplifier OPA3, the same-phase terminal of the amplifier OPA3 is commonly connected with one port of the resistor R5 and the capacitor C12, the other ports of the resistors R5 and the capacitor C12 are commonly connected with an inverting output port vout_p of the amplifier OPA3, the inverting terminal of the amplifier OPA3 is simultaneously connected with one port of the resistor R6 and one port of the capacitor C13, and the other ports of the resistor R6 and the capacitor C13 are commonly connected with an inverting output port of the amplifier OPA 3.
3. The dual-channel broadband Hall current sensor according to claim 1, wherein the S-shaped copper rail on the chip is an S-shaped current-carrying copper rail designed by adopting a top layer thick metal above the integrated Hall probes, one end of the S-shaped copper rail flows in current, the other end of the S-shaped copper rail is a current outflow port, two pairs of differential Hall probes, namely a Hall probe (X1 and X2) and a Hall probe (X3 and X4), are respectively placed at the corners of the S-shaped copper rail, and the two pairs of differential Hall probes are used as Hall probes of a high-frequency path and a low-frequency path of the current sensor.
4. The dual-channel broadband hall current sensor of claim 1 wherein the matching network is a low-pass filter for the low-frequency path, and has a cutoff frequency Fx = 1/(2rr 5C12), wherein Fx is the cutoff frequency of the matching network, R 5 is the resistance of resistor R5, and C 12 is the capacitance of capacitor C12; the matching network is a high-pass filter for a high-frequency channel, and the cutoff frequency is fx=1/(2pi R 5C12), wherein Fx is the cutoff frequency of the matching network, R 5 is the resistance of the resistor R5, and C 12 is the capacitance of the capacitor C12.
5. The implementation method of the double-channel broadband Hall current sensor is characterized by comprising the following steps of:
S1: if the frequency of the current flowing in the S-shaped copper rail is smaller than the cut-off frequency Fx, steps S1.1 to S1.4 are performed:
s1.1: performing four-phase rotation modulation operation of the Hall signal polarity and the offset signal polarity;
s1.2: performing Hall current integration and amplification to obtain Hall voltage operation;
S1.3: executing Hall voltage sampling and holding operation;
s1.4: performing an operation of filtering high-frequency harmonics;
S2: if the frequency of the current flowing in the S-shaped copper rail is greater than the cut-off frequency Fx, executing steps S2.1 to S2.3:
S2.1: performing a high frequency path dc offset calibration operation;
S2.2: performing high-frequency hall signal amplification operation;
s2.3: and performing matching network circuit operation.
6. The method for implementing a dual-channel broadband Hall current sensor as defined in claim 5, wherein,
The four-phase rotation modulation operation of the Hall signal polarity and the offset signal polarity in the S1.1 is specifically as follows:
When the first phase operation of the dynamic rotating current circuit is performed, the clock input clk1 of the dynamic rotating current circuit is at a high level, all other clock inputs are at a low level, the voltage output by the rotating current circuit CS1 is vh+v os11 +vc (Vh is a hall voltage, vc is an interference voltage caused by a common-mode magnetic field), V os11-Vos14 is an offset voltage output by the first phase to the fourth phase rotating current circuit of the hall probe X1, and the voltage output by the rotating current circuit CS2 is-vh+v os21+Vc(Vos21-Vos24 and is an offset voltage output by the first phase to the fourth phase rotating current circuit of the hall probe X2);
When the second phase operation of the dynamic rotating current circuit is carried out, the clock input clk2 of the dynamic rotating current circuit is high level, all other clock inputs are low level, the voltage output by the rotating current circuit CS1 is Vh-V os12 +Vc, and the voltage output by the rotating current circuit CS2 is-Vh-V os22 +Vc;
When the third phase operation of the dynamic rotating current circuit is carried out, the clock input clk3 of the dynamic rotating current circuit is high level, all other clock inputs are low level, the voltage output by the rotating current circuit CS1 is-vh+V os13 +Vc, and the voltage output by the rotating current circuit CS2 is vh+V os23 +Vc;
When the fourth phase operation of the dynamic rotating current circuit is carried out, the clock input clk4 of the dynamic rotating current circuit is high level, all other clock inputs are low level, the voltage output by the rotating current circuit CS1 is Vh-V os14 +Vc, and the voltage output by the rotating current circuit CS2 is Vh-V os24 +Vc;
The four-phase Hall voltage and offset voltage output by the rotating current circuit CS1 are converted into currents of Ih+I os11+Ic、Ih-Ios12+Ic、-Ih+Ios13+Ic、-Ih-Ios14 +ic (the currents Ih, I os11-Ios14 and Ic are voltages Vh, V os11-Vos14 and Vc are converted into currents through the transconductance amplifying circuit GM 1) through the transconductance amplifying circuit GM1, the aliasing signal of the four-phase Hall voltage and offset voltage output by the CS2 is converted into currents of-Ih+I os21+Ic、-Ih-Ios22+Ic、Ih+Ios23+Ic、Ih-Ios24 +ic (the currents Ih, I os21-Ios24 and Ic are voltages Vh, V os21-Vos24 and Vc are converted into currents through the transconductance amplifying circuit GM 1) through the transconductance amplifying circuit GM1, and then each phase Hall current and offset current output by the transconductance amplifying circuit GM1 and each phase Hall current and offset current output by the transconductance amplifying circuit GM1 are subtracted to obtain new four-phase Hall current and offset current 2Ih+Ios11-Ios21、2Ih-Ios12+Ios22、-2Ih+Ios13-Ios23、-2Ih-Ios14+Ios24;
The operation of integrating and amplifying the Hall current into the Hall voltage in the S1.2 is specifically as follows:
When the clock signal clk1 and clk2 are effective in high level, the current outputted by the transconductance amplifying circuits GM1 and GM2 is subtracted to obtain first-phase and second-phase hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22, when the clock signal clk5 is effective in high level, the first-phase and second-phase hall currents 2ih+i os11-Ios21、2Ih-Ios12+Ios22 are fed into the current integrating amplifying circuit to operate, the obtained output hall voltage is V 1-2＝4Vh+Vos1-2, 4Vh is the hall voltage outputted after integrating and amplifying the hall current Ih, vos 1-2 is the residual offset voltage after integrating and amplifying the first-phase and second-phase offset currents, and then when the clock signal clk6 is effective in high level, the voltages on the integrating capacitors C1 and C2 are cleared;
When the clock signal clk3 and clk4 are valid at a high level, the currents outputted by the transconductance amplifying circuits GM1 and GM2 are subtracted to obtain hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 of a third phase and a fourth phase, when the clock signal clk5 is valid at a high level, the hall currents-2ih+i os13-Ios23、-2Ih-Ios14+Ios24 of the third phase and the fourth phase are subjected to current integration operation, the obtained output hall voltage is V 3-4＝-4Vh+Vos3-4, wherein-4 Vh is the hall voltage outputted after the hall current Ih is integrated and amplified, vos 3-4 is the residual offset voltage after the third phase offset current and the fourth phase offset current are integrated and amplified, and then when the clock signal clk6 is valid at a high level, the voltages on the integrating capacitors C1 and C2 are cleared;
the hall voltage sample-and-hold operation in S1.3 is specifically as follows:
When the clock control signal clk7 of the related double sampling circuit is valid in a high level, the related double sampling circuit performs first sampling and holding on the output Hall voltage of the current integrating amplifying circuit as V 1-2＝4Vh+Vos1-2; when the clock control signal clk8 of the related double sampling circuit is effective in high level, the related double sampling circuit performs a second sampling and holding on the output hall voltage of the current integration amplifying circuit as V 3-4＝-4Vh+Vos3-4, when the clock signal clk9 is effective in high level, the related double sampling circuit subtracts the voltage value V 3-4 of the second sampling and holding from the voltage value V 1-2 of the first sampling and holding to obtain a voltage signal as Vout=V 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4, and outputs a hall voltage signal;
the operation of filtering high-frequency harmonic waves in the S1.4 is specifically as follows:
The Hall voltage obtained by subtracting the two samples passes through the input ports Vi_l1 and Vi_l2 of the matching network to obtain an output Hall voltage signal Vout=V 1-2-V3-4＝8Vh+(Vos1-2-Vos3-4);
the high-frequency channel direct current offset calibration operation in the S2.1 is specifically as follows:
When the clock input port clk10 is at high level, clk11 is at low level, the clock input ports S1-S8 are at low level, the band gap reference generates current I, the current I is copied into adjustable current sources I2 and I3 respectively through a cascode current mirror in the same proportion, the current sizes of the adjustable current sources I2 and I3 are I, the current sizes of the fixed current sources I1 and I4 are I f, the current difference value of the adjustable current source I2 and the fixed current source I1 generates direct current voltage v1= (I f -I) x R1 on the resistor R1, the current difference value of the adjustable current source I3 and the fixed current source I4 generates direct current voltage v2= (I-I f) x R2 on the resistor R2, the resistance of the resistor R1 is equal to the resistance of the resistor R2, at this time, the differential dc voltage of VIP and VIN at the input end of the amplifier OPA2 is V1-V2, the dc voltage vo=axx (V1-V2) +v3 at the output end of the amplifier OPA2, wherein a is the gain of the amplifier OPA2, axx (V1-V2) is the dc voltage of the input differential dc voltage (V1-V2) of the amplifier OPA2 amplified by the amplifier OPA2, and V3 is the dc voltage output by the amplifier OPA2 itself when the differential dc voltage is not input to the amplifier OPA2, and when the clock input port clk10 is low level and clk11 is high level, the dc offset calibration operation is started, which is specifically as follows:
When the direct current voltage Vo at the output end of the amplifier OPA2 is larger than VDD/2 (VDD/2 is the direct current voltage at the output end of the amplifier OPA2 when the amplifier OPA2 works normally), the ADC quantizes the voltage of the output end Vo of the amplifier OPA2 and outputs 8-bit digital signals, and the 8-bit digital signals respectively control the on and off of the clock input ports S1-S8 in sequence, so as to control the current mode DAC to generate a current I DAC1 (the current I/2 is the current generated by the current mode DAC after the ADC quantized voltage vo=VDD/2), and the current I DAC1 generated by the current mode DAC is copied into adjustable current sources I2 and I3 through a common-source common-gate current mirror in the same proportion, so that the current sizes of the adjustable current sources I2 and I3 are increased, and A× (V1-V2) are reduced, and the direct current voltage Vo at the output end of the amplifier OPA2 is reduced;
When the direct current voltage Vo at the output end of the amplifier OPA2 is smaller than VDD/2, the ADC quantizes the voltage of the output end Vo of the amplifier OPA2 and outputs 8-bit digital signals, the 8-bit digital signals respectively control the on and off of clock input ports S1-S8 in sequence, and further control a current mode DAC to generate current I DAC2 smaller than I/2, current I DAC2 generated by the DAC is copied into adjustable current sources I2 and I3 in the same proportion through a cascode current mirror, so that the current sizes of the adjustable current sources I2 and I3 are reduced, A x (V1-V2) is increased, the direct current voltage Vo at the output end of the amplifier OPA2 is increased, then the operation is repeated, so that the direct current voltage Vo of the output end of the amplifier OPA2 is gradually close to VDD/2, after a period of calibration time, a clock clk11 is low level, a switch K13 is disconnected, the offset calibration operation is finished, and the circuit normally works;
the high-frequency Hall signal amplifying operation in S2.2 is specifically as follows:
After the high-frequency channel direct current offset calibration operation is finished, the voltage output by the bias circuit N_CS1 is Vh+V os1 +Vc (Vh is a Hall voltage, vc is an interference voltage caused by a common-mode magnetic field, V os1 is an offset voltage output by the Hall probe X3), the voltage output by the bias circuit N_CS2 is-Vh+V os2+Vc,(Vos2 and is an offset voltage output by the Hall probe X4), the Hall voltage and the offset voltage output by the bias circuit N_CS1 are converted into currents respectively into ih+I os1+Ic(Ih、Ios1 through the transconductance amplifier circuit GM3, ic are voltages Vh, V os1 and Vc are converted into currents through the transconductance amplifier circuit GM3, and the Hall voltage and the offset voltage output by the bias circuit N_CS2 are converted into currents respectively into-Ih+I os2+Ic(Ih、Ios2, ic are voltages V os2 and Vc through the transconductance amplifier circuit GM 4; the current output by the transconductance amplifying circuits GM3 and GM4 is 2ih+I os1-Ios2 after being subtracted, the current output by the GM3 and GM4 flows through the resistors R1 and R2 to be converted into the voltage V N_CS＝R1×(2Ih+Ios1-Ios2 after being subtracted, and the resistance values of the resistors R1 and R2 are equal; the Hall voltage V N_CS output by the voltage amplifying circuit is amplified again by the amplifying and offset calibrating circuit for the second time to output the Hall voltage V=A×R1× (2ih+I os1-Ios2); wherein A is the gain of an amplifier OPA2 in the amplifying and offset calibration circuit;
The matching network circuit in S2.3 specifically operates as follows:
The amplifying and offset calibration circuit outputs a Hall voltage signal V through input ports Vi_h1 and Vi_h2 of a matching network, the matching network is a high-pass filter for a high-frequency channel, the cut-off frequency is Fx=1/(2pi R 5C12), fx is the cut-off frequency of the matching network, R 5 is the resistance of a resistor R5, C 12 is the capacitance of a capacitor C12, the amplifying and offset calibration circuit outputs a signal with the frequency larger than Fx, the Hall voltage can be normally output through the high-pass filter, the low-frequency channel is connected with input ports Vi_l1 and Vi_l2 of the matching network, the matching network is a low-pass filter for the low-frequency channel, the cut-off frequency is Fx=1/(2pi R 5C12), fx is the cut-off frequency of the matching network, R 5 is the resistance of the resistor R5, C 12 is the capacitance of the capacitor C12, and the low-frequency signal is the signal with the frequency smaller than Fx, and the Hall voltage can be normally output through the low-pass filter.
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