CN118019336A - Non-volatile memory element and manufacturing method thereof - Google Patents

Abstract

The invention discloses a nonvolatile memory element and a manufacturing method thereof, wherein the nonvolatile memory element comprises at least one memory unit, and the memory unit comprises: a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes lateral tips that are laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate and includes a second thickness (T2). The erase gate covers the erase gate dielectric and the lateral tip of the planar floating gate. The first thickness and the second thickness conform to the following relationship: (T2) < (T1) <2 (T2).

Description

Non-volatile memory element and manufacturing method thereof

Technical Field

The invention relates to a semiconductor element. More particularly, the present invention relates to a nonvolatile memory device and a method of fabricating the same.

Background

Since a nonvolatile memory (nonvolatile memory) can repeatedly perform operations such as storing, reading and erasing data, and the stored data is not lost after the nonvolatile memory is turned off, the nonvolatile memory has been widely used in personal computers and electronic devices.

The structure of the conventional nonvolatile memory has a stacked gate structure including a tunnel oxide layer (tunneling oxide layer), a floating gate (floating gate), a coupling dielectric layer (coupling DIELECTRIC LAYER) and a control gate (control gate) sequentially disposed on a substrate. When programming or erasing such a flash memory device, appropriate voltages are applied to the source region, the drain region and the control gate, respectively, so that electrons are injected into the floating gate or so that electrons are pulled out from the floating gate.

In the programming and erasing operations of the nonvolatile memory, a larger gate-to-coupling ratio (GCR) between the floating gate and the control gate generally represents a lower operation voltage required during the operation, thereby significantly improving the operation speed and efficiency of the flash memory. However, during a program or erase operation, electrons must flow through the tunnel oxide layer disposed under the floating gate to be injected into or extracted from the floating gate, which often damages the structure of the tunnel oxide layer, thereby reducing the reliability of the memory device.

To improve the reliability of the memory device, an erase gate ERASE GATE may be used and integrated into the memory device. By applying a positive voltage to the erase gate, the erase gate is able to pull electrons out of the floating gate. Therefore, since electrons in the floating gate are pulled out through the tunnel oxide layer disposed on the floating gate, not through the tunnel oxide layer disposed under the floating gate, the reliability of the memory device is further improved.

With the increasing demand for efficient memory devices that can efficiently erase stored data, there remains a need to provide improved memory devices and methods of manufacturing the same.

Disclosure of Invention

The invention aims to provide a nonvolatile memory element and a method for manufacturing the nonvolatile memory element. The nonvolatile memory element can efficiently erase stored data.

According to some embodiments, the present invention provides a non-volatile memory device. The non-volatile memory element comprises at least one memory cell, and the memory cell comprises: a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate is disposed on the substrate. The control gate is disposed on the substrate and laterally spaced apart from the select gate, and the control gate includes a non-vertical surface. The planar floating gate is disposed between the substrate and the control gate and includes a lateral tip laterally spaced from the control gate. The coupling dielectric layer is disposed between the control gate and the planar floating gate, and the coupling dielectric layer includes a first thickness (T1). The erase gate dielectric covers the non-vertical surface of the control gate and covers the lateral tip of the planar floating gate, and the erase gate dielectric includes a second thickness (T2). The erase gate covers the erase gate dielectric and covers the lateral tip of the planar floating gate. In order to create a more advantageous electric field to enable the electron tunnel to penetrate out of the planar floating gate during the erase process, the first thickness and the second thickness satisfy the following relationship: (T2) < (T1) <2 (T2). T1 represents a first thickness of the coupling dielectric layer, and T2 represents a second thickness of the erase gate dielectric layer.

According to some embodiments, the present invention also provides a method of manufacturing a non-volatile memory element, comprising: providing a substrate; forming a floating gate layer on a substrate; forming a select gate layer on the substrate, wherein the select gate layer is laterally spaced apart from the floating gate layer; forming a control gate covering the sidewall of the select gate layer and the floating gate layer, wherein the control gate includes a non-vertical surface; etching the floating gate layer using the control gate as an etch mask to form a planar floating gate, wherein the planar floating gate includes lateral tips laterally spaced apart from the control gate; and forming an erase gate overlying the non-vertical surface of the control gate and overlying the lateral tip of the planar floating gate.

Drawings

The following drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic top view of a nonvolatile memory device according to some embodiments of the invention.

FIG. 2 is a schematic cross-sectional view of a nonvolatile memory element taken along section line A-A' shown in FIG. 1 in accordance with some embodiments of the present invention.

FIG. 3 is a schematic cross-sectional view of an area of the non-volatile memory device of FIG. 2 according to some embodiments of the invention.

FIG. 4 is a schematic cross-sectional view of a nonvolatile memory element taken along lines B-B 'and C-C' of FIG. 1 in accordance with some embodiments of the present invention.

Fig. 5 is a schematic cross-sectional view of a nonvolatile memory element according to other embodiments of the present invention, corresponding to the section line A-A' in fig. 1.

Fig. 6A-6E are schematic cross-sectional views of a method of manufacturing the nonvolatile memory device of fig. 1-4 at different stages according to some embodiments of the invention.

Fig. 7A-7C are schematic cross-sectional views of a method of manufacturing the non-volatile memory device of fig. 1 and 5 at different stages in accordance with some embodiments of the invention.

Reference numerals illustrate: 100_1, 100_2-nonvolatile memory elements; 102-isolation structures; 103-an active region; 110-a first memory cell region; 112-a second memory cell region; 114-a third memory cell region; 116-a fourth memory cell region; 200-substrate; 202-a select gate dielectric layer; 204-select gates; 212-dielectric spacers; 213-arcuate top surface; 218-a floating gate dielectric layer; 222-source region; 224-planar floating gate; 226 a-lateral tip; 230_1-a first sidewall; 230_2-a second sidewall; 232, 250-projections; 234-erasing the gate dielectric; 236-erasing the gate; 238, 248, 258-coupling dielectric layer; 238_1-vertical section; 238_2-horizontal section; 239_2-non-vertical side walls, curved side walls; 240-a control gate; 242-terminal portion; 244-drain region; 246-non-vertical surfaces; 254-a floating gate layer; 256-an etch mask; 260-a control gate layer; 264-a select gate layer; 266-erasing the gate layer; r1-region; t1-a first thickness; t2-a second thickness; x-a first direction; y-second direction.

Detailed Description

The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of "a first feature being formed on or over a second feature" may refer to "the first feature being in direct contact with the second feature" or "there may be other features between the first feature and the second feature" such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for the spatially related narrative terms mentioned in the present invention, for example: "under," "low," "under," "above," "over," "lower," "top," "bottom," and the like, when used in reference to a number of drawings, are intended to describe one element or feature's relative relationship to another element(s) or feature(s) in the drawings. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.

While the invention is described below with respect to the specific embodiments, the inventive principles of this patent are defined by the claims and may be applied to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such omitted details are within the knowledge of one of ordinary skill in the art.

FIG. 1 is a schematic top view of a nonvolatile memory element according to some embodiments of the invention. Referring to fig. 1, the nonvolatile memory element 100_1 may be a NOR flash memory element including at least one memory cell, for example, four memory cells respectively accommodated in a first memory cell region 110, a second memory cell region 112, a third memory cell region 114, and a fourth memory cell region 116. The structures in the first memory cell region 110 and the second memory cell region 112 are mirror images of each other, and the structures in the third memory cell region 114 and the fourth memory cell region 116 are mirror images of each other. According to an embodiment of the present invention, the nonvolatile memory element 100_1 includes more than four memory cells, and the memory cells may be arranged in an array having many rows and columns.

Referring to fig. 1, the nonvolatile memory element includes a substrate 200 and an isolation structure 102. The substrate 200 may be a semiconductor substrate such as a silicon substrate, a silicon-on-insulator Substrate (SOI), but is not limited thereto. The isolation structure 102 may be made of an insulating material and is used to define the active region 103 of the memory cell.

Each memory cell includes a source region 222 and a drain region 244 disposed in an active region 103 defined by the isolation structure 102. The source region 222 and the drain region 244 may be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 244 is different from that of the substrate 200 or from that of a doped well (not shown) for accommodating the source region 222 and the drain region 244. A source region 222 may be disposed in one end of the active region 103 of each memory cell, and a drain region 244 may be disposed in the other end of the active region 103 of each memory cell. According to some embodiments of the present invention, the source region 222 is a continuous region extending in the Y direction and is a common source shared by memory cells arranged in the same row.

Each memory cell may further include a select gate 204 disposed on the substrate 200 and adjacent to the drain region 244. The select gates 204 may extend in the Y-direction and be shared by memory cells arranged in the same column. The select gate 204 may be made of a conductive material such as polysilicon or metal, and the select gate 204 may serve as a word line configured to turn on/off channel regions of a plurality of memory cells located under the word line. Thus, the channel regions of memory cells in the same row may be turned on or off simultaneously.

Dielectric spacers 212 may be provided on sidewalls of the select gate 204 to insulate the select gate 204 from other conductive portions. Dielectric spacers 212 may be single-layer, double-layer, or multi-layer spacers disposed on each sidewall of select gate 204, but are not limited thereto.

Each memory cell also includes a planar floating gate 224 disposed on the substrate 200 and adjacent to the source region 222. Thus, the planar floating gate 224 is disposed on one side of the select gate 204, and the drain 244 is disposed on the other side of the select gate 204. The planar floating gate 224 is made of a conductive material such as polysilicon or other conductive semiconductor. The planar floating gates 224 are spaced apart from each other such that current stored in the planar floating gates 224 is not directly transferred between the planar floating gates 224. Because the planar floating gates 224 are spaced apart from each other, each planar floating gate 224 can be programmed or erased independently to determine the state of each memory cell, such as state "1" or state "0". As shown in the cross-sectional views below, such as fig. 2 and 3, each planar floating gate 224 is a planar floating gate having a substantially planar top surface. In the description corresponding to fig. 2 and 3, the detailed structure of the planar floating gate 224 is described.

Each memory cell also includes a control gate 240 disposed on the substrate 200 and adjacent to the source region 222. The control gates 240 may extend in the Y-direction and be shared by memory cells arranged in the same column. Thus, the floating gate 224 may be covered by the control gate 240 in the same column. In addition, the planar floating gate 224 may be partially protruded from the control gate 240 toward the boundary between adjacent memory cell regions in the same row. The control gate 240 is made of a conductive material, such as polysilicon or metal. The control gate 240 is configured such that hot carriers (e.g., electrons) are injected from the channel region into the corresponding planar floating gate 224.

The nonvolatile memory device 100_1 further includes an erase gate 236 extending in the Y direction. In addition, the erase gate 236 may be a continuous layer that fills the gap at the boundary between adjacent memory cell regions in the same row (e.g., the gap between adjacent two planar floating gates 224 in the same row). Therefore, the erase gate 236 may cover at least the two planar floating gates 224 and the two control gates 240 in the first memory cell region 110 and the second memory cell region 112. In an erase operation of the nonvolatile memory element 100_1, the erase gate 236 is biased, causing electrons stored in the planar floating gate 224 to be pulled out primarily through the lateral tip (not shown) of the planar floating gate 224. The location and configuration of the lateral tips of the planar floating gate 224 will be described in detail below.

FIG. 2 is a schematic cross-sectional view of a nonvolatile memory element taken along section line A-A' shown in FIG. 1 according to some embodiments of the present invention. Referring to fig. 2, the planar floating gate 224 is a planar floating gate between the substrate 200 and the control gate 240. The planar floating gate 224 includes a protrusion 232 exposed from the control gate 240. The planar floating gate 224 also includes a lateral tip 226a corresponding to the upper corner of the protrusion 232 and laterally spaced from the control gate 240. During an erase operation, electrons stored in the planar floating gate 224 are pulled out mainly through the lateral tip 226a of the planar floating gate 224. In addition, the planar floating gate 224 further includes two opposite first sidewalls 230_1. The first sidewalls 230_1 are opposite to each other and are arranged along a first direction, e.g., the X-direction, wherein one of the first sidewalls 230_1 is connected to the lateral tip 226a of the planar floating gate 224.

The control gate 240 is located on the substrate 200 and laterally spaced from the select gate 204. The control gate 240 includes a non-vertical surface 246, such as an inclined surface or an arcuate surface. The non-perpendicular surface 246 may be, for example, a convex surface.

The erase gate 236 is a continuous layer extending from the first memory cell region 110 to the second memory cell region 112. The erase gate 236 covers the non-vertical surface 246 of the control gate 240 and portions of the lateral tips 226a of the planar floating gate 224. Since a portion of the erase gate 236 covers the non-vertical surface 246 of the control gate 240, the bottom surface of the opposite portion of the erase gate 236 is an arcuate surface.

The erase gate 236 is filled in the gap at the boundary between the first memory cell region 110 and the second memory cell region 112. Because non-vertical sidewall 239_2 of end portion 242 of coupling dielectric layer 238 has a concave surface, a corresponding portion of erase gate 236 may include protrusion 250 extending toward non-vertical sidewall 239_2 (e.g., a concave sidewall) of end portion 242 of coupling dielectric layer 238. The protrusion 250 of the erase gate 236 may cover the lateral tip 226a of the planar floating gate 224, resulting in the erase gate 236 partially wrapping (wrap around) the lateral tip 226a of the planar floating gate 224. Thus, electrons originally stored in the planar floating gate 224 can be more effectively pulled out through the lateral tip 226a of the planar floating gate 224.

The erase gate 236 also includes a planar top surface overlying the non-vertical surface 246 of the control gate 240, and the erase gate 236 is laterally spaced from the select gate 204. Since the erase gate 236 has a height that is at most 20% higher than the height of the select gate 204 (based on the height of the select gate 204), or even lower than the height of the select gate 204, the non-volatile memory device 110_1 can be easily integrated into other semiconductor devices in a digital circuit, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Therefore, the nonvolatile memory device 110_1 and other semiconductor devices in the digital circuit can be manufactured simultaneously without greatly adjusting the manufacturing process of the semiconductor device.

The nonvolatile memory device 100_1 further includes a coupling dielectric layer 238 disposed between the control gate 240 and the planar floating gate 224. The coupling dielectric layer 238 is a composite dielectric layer including, but not limited to, silicon oxide/silicon nitride/silicon oxide.

The coupling dielectric layer 238 is an L-shaped coupling dielectric layer and includes a vertical portion 238_1 and a horizontal portion 238_2. The vertical portion 238_1 of the coupling dielectric layer 238 is disposed between the control gate 240 and the select gate 204. The vertical portion 238_1 of the coupling dielectric layer 238 includes a top surface 239_1 having an arcuate profile, but is not limited thereto. The horizontal portion 238_2 is disposed between the control gate 240 and the planar floating gate 224, wherein an end portion 242 of the horizontal portion 238_2 of the coupling dielectric layer 238 extends from under the control gate 240 and is exposed from the control gate 240. The end portion 242 of the horizontal portion 238_2 of the coupling dielectric layer 238 includes a non-vertical sidewall 239_2 exposed outside the control gate 240. The non-vertical sidewall 239_2 is concave and directly contacts the erase gate dielectric 234.

The nonvolatile memory device 100_1 further includes an erase gate dielectric 234 disposed between the erase gate 236 and the planar floating gate 224 and between the erase gate 236 and the control gate 240. The erase gate dielectric 234 may be fabricated from a dielectric that allows electrons originally stored in the floating gate 224 to penetrate therethrough by Fowler-Nordheim (FN) tunneling. In some examples, erase gate dielectric 234 is a continuous layer extending from first memory cell region 110 to second memory cell region 112. In addition, the top surface of select gate 204 and the top tip of control gate 240 may be covered by erase gate dielectric 234. During a programming operation, hot electrons are allowed to pass through the floating gate dielectric 218 and accumulate in the planar floating gate 224.

Dielectric spacers 212 are disposed on sidewalls of the select gates 204. In some embodiments, dielectric spacer 212 includes an arcuate top surface 213.

The nonvolatile memory device 100_1 further includes a select gate dielectric layer 202 disposed between the substrate 200 and the select gate 204. The composition of the select gate dielectric 202 may be the same as or different from the composition of the floating gate dielectric 218, depending on the requirements.

FIG. 3 is a schematic cross-sectional view of an area of the non-volatile memory device of FIG. 2 according to some embodiments of the invention. The structure shown in fig. 3 corresponds to the region R1 in the structure shown in fig. 2. Referring to fig. 3, lateral tips 226a of planar floating gate 224 may be covered by a thin layer of coupling dielectric layer 238. For example, the thickness of the coupling dielectric layer 238 covering the lateral tip 226a of the planar floating gate 224 may be between 5 angstroms and 30 angstroms, but is not limited thereto. To more efficiently erase electrons stored in the planar floating gate 224, the lateral tip 226a may not be covered by any coupling dielectric layer 238. Thus, the lateral tip 226a is in direct contact with the erase gate dielectric 234.

The horizontal portion 238_2 of the coupling dielectric layer 238 includes curved sidewalls 239_2, such as recessed sidewalls. The profile of the curved sidewall 239_2 affects the profile of the corresponding portion of the erase gate 236. For example, as the curvature of the curved sidewall 239_2 increases, the protrusion 250 of the erase gate 236 protrudes further toward the curved sidewall 239_2 of the coupling dielectric layer 238. Therefore, not only the lateral tip 226a, but also the area of the planar floating gate 224 near the lateral tip 226a is covered by the protrusion 250 of the erase gate 236. In this way, the erasing efficiency can be further improved.

The erase gate dielectric 234 substantially conformally covers the control gate 240, the curved sidewall 239_2 of the coupling dielectric 238, and the first sidewall 230_1 of the planar floating gate 224. Since some portion of the curved sidewall 239_2 of the coupling dielectric layer 238 is covered by the control gate 240, the portion of the erase gate dielectric layer 234 that is in direct contact with the coupling dielectric layer 238 may be located between the control gate 240 and the planar floating gate 224.

To create a more advantageous electric field to tunnel the electron tunnel out of the planar floating gate 224 during the erase process, the curvature and profile of the protrusion 250 of the erase gate 236 can be properly controlled. The thickness (also referred to as a first thickness) T1 of the coupling dielectric layer 238 and the thickness (also referred to as a second thickness) T2 of the erase gate dielectric layer 234 satisfy the following formula:

(T2)<(T1)<2(T2)

Wherein T1 represents the average thickness of the coupling dielectric layer 238 covered by the control gate 240, and T2 represents the average thickness of the erase gate dielectric layer 234 on the first sidewall 230_1 of the planar floating gate 224.

When the first thickness T1 of the coupling dielectric layer 238 is smaller than the second thickness T2 of the erase gate dielectric layer 234, the corresponding erase gate dielectric layer 234 is less able to fill the space between the control gate 240 and the planar floating gate 224. Therefore, the protrusion 250 of the erase gate 236 protrudes less, such that the lateral tip 226a of the planar floating gate 224 is no longer covered by the protrusion 250. Thus, the erase efficiency is reduced.

Conversely, when the first thickness T1 of the coupling dielectric layer 238 is greater than twice the second thickness T2 of the erase gate dielectric layer 234, the corresponding erase gate dielectric layer 234 is more filled into the space between the control gate 240 and the planar floating gate 224. As a result, the end of the protrusion 250 of the erase gate 236 becomes pointed. During operation of the nonvolatile memory element 100_1, electrons may be emitted from the tips of the protrusions 250, causing positive charges to accumulate in the protrusions 250, thereby negatively affecting the electronic characteristics of the nonvolatile memory element 100_1.

FIG. 4 is a schematic cross-sectional view of a nonvolatile memory element taken along lines B-B 'and C-C' of FIG. 1 in accordance with some embodiments of the present invention. Referring to section BB' of FIG. 4, the control gate 240 and the erase gate 236 may be disposed on the isolation structure 102, and the control gate 240 may be disposed between the erase gate 236 and the isolation structure 102. In addition, the isolation structure 102 shown in fig. 4 is not covered by the planar floating gate 224. The coupling dielectric layer 238 is an L-shaped layer located on the isolation structure 102.

Referring to section CC' of fig. 4, the planar floating gate 224 includes two second sidewalls 230_2 opposite to each other and arranged along a second direction different from the first direction, such as the Y direction. The control gate 240 extends along the second direction and covers the second sidewall 230_2 of the planar floating gate 224. In addition, the second sidewall 230_2 may also be covered by the coupling dielectric layer 238. The control gate 240, as shown in section CC', is not covered by any erase gate (not shown).

Fig. 5 is a schematic cross-sectional view of a nonvolatile memory element according to other embodiments of the present invention, corresponding to the section line A-A' in fig. 1. Referring to fig. 5, the nonvolatile memory element 100_2 shown in fig. 5 is similar to the nonvolatile memory element 100_1 shown in fig. 2, and the main difference between the two is that the coupling dielectric layer 238 has only the horizontal portion 238_2, and the vertical portion shown in fig. 2 is omitted. Thus, the entire top surface of the coupling dielectric layer 238 may be covered by the control gate 240. In addition, the end portion 242 of the coupling dielectric layer 238 still includes the curved sidewall 239_2, and a portion of the curved sidewall 239_2 protrudes out of the control gate 240.

Fig. 6A-6E are schematic cross-sectional views of a method of manufacturing the nonvolatile memory device of fig. 1-4 at different stages according to some embodiments of the invention.

Referring to fig. 6A, in step 602, a substrate 200 is provided. Next, a floating gate dielectric layer 218, a floating gate layer 254, and an etching mask 256, which are sequentially stacked, are disposed on the substrate 200. The floating gate dielectric layer 218 and the floating gate layer 254 may be formed by deposition and etching processes. During etching, the pattern of the etch mask 256 may be transferred to the floating gate dielectric layer 218 and the floating gate layer 254. In addition, after the etching process, the floating gate dielectric layer 218 and the floating gate layer 254 may extend in the Y direction (also referred to as a second direction) in a top view.

Dielectric spacers 212 are formed on sidewalls of the floating gate layer 254, the floating gate dielectric layer 218 and the etch mask 256. A select gate dielectric 202 is formed on the substrate 200 on either side of a floating gate dielectric 218.

Next, in step 604, a select gate layer 264 is formed on the substrate 200, on both sides of the floating gate dielectric layer 218. Select gate layer 264 is laterally spaced apart from floating gate layer 254. The select gate layer 264 may be further patterned or modified to serve as a select gate for the non-volatile memory device in a subsequent process. The method of forming the select gate layer 264 may include the following steps. For example, a conductive layer (not shown) is deposited over the substrate 200 to cover the etch mask 256. A planarization process is then performed on the conductive layer to planarize the top surface of the conductive layer until the top surface of the etch mask 256 is exposed. After the formation of the select gate layer 264, the etch mask 256 is removed to expose the top surface of the floating gate layer 254.

Then, photolithography and etching processes are performed to etch the floating gate layer 254 and the floating gate dielectric layer 218. In this manner, the etched floating gate layer 254 and the floating gate dielectric layer 218 may be patterned to form a plurality of stripe structures (stripe-shaped structures) (not shown), and the stripe structures are disposed along the Y direction and separated from each other in a top view. Each of the stripe structures may extend in the X direction and simultaneously extend in the first memory cell region 110 and the second memory cell region 112.

Referring to fig. 6B, in step 606, a coupling dielectric layer 248 is formed over the substrate 200 to conformally cover the select gate layer 264 and the floating gate layer 254. Since the floating gate layer 254 is stripe-shaped from a top-down view, the coupling dielectric layer 248 covers not only the top surface of the floating gate layer 254 but also the sidewalls (not shown) of the floating gate layer 254. The coupling dielectric layer 248 may be a composite dielectric layer including, but not limited to, silicon oxide/silicon nitride/silicon oxide.

Next, a control gate layer 260 is disposed on the coupling dielectric layer 248. The thickness of the control gate layer 260 may be appropriately controlled such that the control gate layer 260 may conform to the underlying structure. The control gate layer 260 may be made of a conductive material such as polysilicon or metal, but is not limited thereto.

Then, in step 608, an anisotropic etching process is performed to etch the control gate layer 240 to form the control gate 240 on the sidewall of the select gate layer 264 and on the top surface of the floating gate layer 254. The control gate 240 is a self-aligned structure with a non-vertical surface 246, thus eliminating the need for photolithography. After the formation of the control gate 240, the control gates 240 in the first memory cell region 110 and the second memory cell region 112, respectively, may be laterally spaced apart from each other in the X-direction. In addition, after the control gate 240 is formed, a portion of the coupling dielectric layer 248 above the select gate layer 264 may be exposed from the control gate 240.

Referring to fig. 6C, in step 610, the coupling dielectric layer 248 is anisotropically etched by using the control gate layer 260 as an etching mask to form a coupling dielectric layer 238 of an L-shaped structure having a vertical portion 238_1 and a horizontal portion 238_2. The vertical portion 238_1 is located between the control gate 240 and the select gate layer 264. The horizontal portion 238_2 is located between the control gate 240 and the substrate 200. By properly controlling the type or ratio of etching recipe and etchant, the top surface 239_1 of the vertical portion 238_1 can be a flat or concave surface that is lower than the top tip of the control gate 240. In addition, the horizontal portion 238_2 of the coupling dielectric layer 238 includes an end portion 242 extending from under the control gate 240 and partially exposed from the control gate 240. The end portion 242 of the horizontal portion 238_2 of the coupling dielectric layer 238 includes an arc-shaped sidewall 239_2 extending and exposed outside the control gate 240. After forming the coupling dielectric layer 238 including the vertical portion 238_1 and the horizontal portion 238_2, the portion of the floating gate layer 254 located at the boundary between the first memory cell region 110 and the second memory cell region 112 may be exposed.

Referring to fig. 6D, in step 612, an etch of the floating gate layer 254 is performed using the control gate 240 and the coupling dielectric layer 238 as an etch mask to form the planar floating gate 224. The planar floating gate 224 is a planar structure including lateral tips 226a laterally and vertically spaced apart from the control gate 240. By using the control gate 240 and the coupling dielectric layer 238 as an etch mask, no additional photolithography process is required to define the shape of the planar floating gate 224. In addition, in the process of forming the planar floating gate 224, a portion of the control gate 240 may be etched at the same time, and the height of the control gate 240 may be slightly lowered. Even if the control gate 240 is reduced in size during the etching process, the coupling dielectric layer 238 is not significantly reduced in size because the composition of the coupling dielectric layer 238 is different from that of the planar floating gate 224. After forming the floating gate 224, the floating gate dielectric layer 218 may also be etched to expose the substrate 200 at the boundary between the first memory cell region 110 and the second memory cell region 112.

Referring to fig. 6E, the select gate layer 264 may be patterned to form the select gate 204 in step 614. At least one drain region 244, such as two drain regions 244, may be formed on both sides of the select gate 204. Two drain regions 244 are disposed in the first memory cell region 110 and the second memory cell region 112, respectively, which may be electrically coupled to each other through a via (via) or a contact (contact) in a subsequent process. In addition, source regions 222 may be formed in the substrate 200 at the same time and between the control gates 240.

The formation of drain region 244 and source region 222 may include, for example, ion implantation. The implanted dopants may be n-type or p-type dopants depending on the device design. The dopants and doping concentrations of the source region 222 and the drain region 244 may be the same or different.

An erase gate dielectric 234 is then conformally formed over the select gate 204, the planar floating gate 224, and the control gate 240. A portion of the erase gate dielectric 234 may fill in the gap between the control gate 240 and the planar floating gate 224.

Then, an erase gate layer 266 is deposited over the control gate 240 and fills the gap between the control gate 240 and the planar floating gate 224. The erase gate layer 266 covers not only the non-vertical surface 246 of the control gate 240, but also the lateral tip 226a of the planar floating gate 224.

Thereafter, a planarization process may be performed on the erase gate layer 266 to form the erase gate shown in FIG. 2. In addition, other components may be fabricated by performing appropriate processes to obtain a nonvolatile memory element similar to the structure shown in fig. 1 to 4.

Fig. 7A-7C are schematic cross-sectional views of a method of manufacturing the non-volatile memory device of fig. 1 and 5 at different stages in accordance with some embodiments of the invention. In fig. 7A to 7C, the structure corresponds to that shown by the sectional line A-A' in fig. 1. In addition, since the processes of the embodiments shown in fig. 7A to 7C are similar to those of the embodiments shown in fig. 6A to 6E, only major differences between the embodiments will be described for brevity.

Referring to fig. 7A, in step 702, a floating gate dielectric layer 218, a floating gate layer 254, a coupling dielectric layer 258, and an etch mask 256 are sequentially stacked on a substrate 200. The floating gate dielectric 218, the floating gate 254 and the coupling dielectric 258 may be formed by deposition and etching processes. During etching, the pattern of the etch mask 256 may be transferred to the floating gate dielectric 218, the floating gate 254, and the coupling dielectric 258. The floating gate dielectric 218, the floating gate 254, and the coupling dielectric 258 may extend in the Y direction (also referred to as a second direction) in a top view. Dielectric spacers 212 are formed on sidewalls of the floating gate layer 254, the floating gate dielectric layer 218 and the etch mask 256. A select gate dielectric 202 is disposed on the substrate 200 on both sides of the floating gate dielectric 218.

Next, in step 704, a select gate layer 264 is formed on the substrate 200, on both sides of the floating gate dielectric layer 218. Select gate layer 264 is laterally spaced apart from floating gate layer 254 and coupling dielectric layer 258. After forming the select gate layer 264, the etch mask 256 may be removed to expose the top surface of the coupling dielectric layer 258.

Then, after step 704, photolithography and etching processes are performed to etch the floating gate layer 254, the floating gate dielectric layer 218 and the coupling dielectric layer 258. In this manner, the etched floating gate layer 254, the floating gate dielectric layer 218 and the coupling dielectric layer 258 may be patterned by an etching process to form a plurality of stripe structures (not shown) spaced apart from each other from the top to the bottom. Each of the stripe structures may extend in the X-direction and be located at least in the first memory cell region 110 and the second memory cell region 112.

Referring to fig. 7B, in step 706, a control gate 240 is disposed on the coupling dielectric layer 258. The thickness of the control gate 240 may be suitably controlled such that the control gate layer 260 may conform to the underlying structure. Since the floating gate layer 254 is stripe-shaped when viewed from the top-down view, the control gate layer 240 covers not only the top surface of the floating gate layer 254 but also the sidewalls (not shown) of the floating gate layer 254.

Then, in step 708, the control gate layer 260 is etched by an anisotropic etching process to form the control gate 240 on the sidewall of the select gate layer 264 and on the top surface of the coupling dielectric layer 258. The control gate 240 is a self-aligned structure with a non-vertical surface 246, thus eliminating the need for photolithography. After the formation of the control gate 240, the control gates 240 in the first memory cell region 110 and the second memory cell region 112, respectively, may be laterally spaced apart from each other in the X-direction.

Referring to fig. 7C, in step 710, the coupling dielectric layer 258 is etched to form the coupling dielectric layer 238 having a planar structure by using the control gate layer 260 as an etching mask. The coupling dielectric layer 238 includes an end portion 242 that extends from under the control gate 240 and is exposed from the control gate 240. The end portion 242 of the coupling dielectric layer 238 includes an arcuate sidewall 239_2 extending and exposed beyond the control gate 240. After forming the coupling dielectric layer 238, the portion of the floating gate layer 254 at the boundary between the first memory cell region 110 and the second memory cell region 112 may be exposed.

Thereafter, processes similar to those of fig. 6D to 6E and other processes may be performed to obtain a nonvolatile memory device similar to the structure shown in fig. 1 and 5.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (23)

1. A non-volatile memory device comprising at least one memory cell, the at least one memory cell comprising:

A substrate;

A select gate disposed on the substrate;

a control gate disposed on the substrate and laterally spaced apart from the select gate, wherein the control gate includes a non-vertical surface;

a planar floating gate disposed between the substrate and the control gate, wherein the planar floating gate includes a lateral tip laterally spaced apart from the control gate;

A coupling dielectric layer disposed between the control gate and the planar floating gate, wherein the coupling dielectric layer comprises a first thickness;

An erase gate dielectric layer covering the non-vertical surface of the control gate and the lateral tip of the planar floating gate, wherein the erase gate dielectric layer comprises a second thickness; and

An erase gate covering the erase gate dielectric and the lateral tip of the planar floating gate,

Wherein the first thickness and the second thickness conform to the following relationship:

(T2)<(T1)<2(T2)

Wherein T1 represents the first thickness of the coupling dielectric layer, and T2 represents the second thickness of the erase gate dielectric layer.

2. The device of claim 1, wherein the non-vertical surface of the control gate comprises an inclined surface or an arcuate surface.

3. The device as claimed in claim 1, wherein the planar floating gate further comprises:

Two first side walls opposite to each other and arranged along a first direction, wherein one of the two first side walls is connected to the lateral tip; and

Two second side walls opposite to each other and disposed along a second direction different from the first direction,

The control gate extends along the second direction and covers the two second sidewalls of the planar floating gate.

4. The device as claimed in claim 3, wherein the coupling dielectric layer extends along the second direction and covers the two second sidewalls of the planar floating gate.

5. The non-volatile memory device of claim 1, wherein the coupling dielectric layer comprises:

A vertical portion disposed between the control gate and the select gate; and

A horizontal portion disposed between the control gate and the planar floating gate, wherein the horizontal portion of the coupling dielectric layer includes an arc sidewall.

6. The device of claim 5, wherein the vertical portion of the coupling dielectric layer comprises an arcuate top surface.

7. The device of claim 1, wherein the coupling dielectric layer includes a curved sidewall that is covered by the control gate.

8. The device of claim 7, wherein a portion of the erase gate is disposed between the control gate and the planar floating gate.

9. The device of claim 7, wherein the erase gate includes a protrusion extending toward the curved sidewall of the coupling dielectric layer.

10. The device of claim 1, wherein the erase gate includes a planar top surface overlying the non-vertical surface of the control gate.

11. The non-volatile memory device of claim 1, wherein the erase gate is laterally spaced apart from the select gate.

12. The device of claim 1, wherein the at least one memory cell comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell comprising the select gate, the planar floating gate, and the control gate, the device further comprising a source region shared by the first memory cell and the second memory cell, and the source region is covered by the erase gate.

13. The non-volatile memory device of claim 10, wherein the first memory cell and the second memory cell are mirror images of each other.

14. The device of claim 10, wherein the erase gate fills a gap between the control gates of the first memory cell and the second memory cell.

15. A method of manufacturing a non-volatile memory device, comprising:

Providing a substrate;

Forming a floating gate layer on the substrate;

Forming a select gate layer on the substrate, wherein the select gate layer is laterally spaced apart from the floating gate layer;

forming a control gate covering a sidewall of the select gate layer and the floating gate layer, wherein the control gate includes a non-vertical surface;

Etching the floating gate layer using the control gate as an etching mask to form a planar floating gate, wherein the planar floating gate includes a lateral tip laterally spaced apart from the control gate; and

An erase gate is formed overlying the non-vertical surface of the control gate and overlying the lateral tip of the planar floating gate.

16. The method of manufacturing a non-volatile memory element of claim 15, further comprising:

forming a coupling dielectric layer on the floating gate layer before forming the control gate; and

The coupling dielectric layer is etched using the control gate as the etch mask.

17. The method of fabricating a non-volatile memory device of claim 16, further comprising, after etching the coupling dielectric layer:

The floating gate layer is etched using the coupling dielectric layer as another etching mask.

18. The method of fabricating a non-volatile memory device according to claim 17, further comprising, after etching the floating gate layer:

a sidewall of the coupling dielectric layer is etched to form an arc sidewall covered by the control gate.

19. The method of claim 18, further comprising, after etching the sidewall of the coupling dielectric layer:

An erase electrode dielectric layer is formed on the planar floating gate, wherein a portion of the erase electrode dielectric layer is covered by the control gate.

20. The method of claim 16, wherein the coupling dielectric layer further covers a top surface of the select gate layer prior to forming the control gate.

21. The method of claim 20, wherein the coupling dielectric layer further comprises, in forming the planar floating gate:

a vertical portion disposed between the control gate and the select gate layer; and

A horizontal portion disposed between the control gate and the substrate, wherein a portion of the horizontal portion of the coupling dielectric layer extends from under the control gate and is exposed from the control gate.

22. The method of claim 21, wherein the horizontal portion of the coupling dielectric layer includes a non-vertical sidewall exposed from the control gate when forming the planar floating gate.

23. The method of claim 16, wherein forming the coupling dielectric layer is performed prior to forming the select gate layer.