CN118016685A - CMOS image sensor and method for manufacturing vertical gate thereof - Google Patents
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Abstract
The invention discloses a CMOS image sensor and a method for manufacturing a vertical gate thereof, which belong to the technical field of semiconductors, and the method for manufacturing the vertical gate of the CMOS image sensor comprises the following steps: providing a substrate, forming a photodiode in the substrate, and a floating diffusion region adjacent to the photodiode; forming a trench between the photodiode and the floating diffusion region, and performing ion implantation at a predetermined depth of the trench, wherein one side of the trench, which is close to the photodiode, is denoted as a first side, the other side is denoted as a second side, and the ion concentration at the first side is lower than the ion concentration at the second side; and filling polycrystalline silicon in the groove, depositing polycrystalline silicon on the substrate to form a polycrystalline silicon layer, and etching the polycrystalline silicon layer to form a vertical gate. By carrying out ion doping on the vertical grid, a cross section with the ion concentration transverse difference is formed on the vertical grid, so that the transverse electric field is improved, and the transfer process of photoelectrons is accelerated.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a CMOS image sensor and a manufacturing method of a vertical gate thereof.
Background
With the rapid development of automatic driving, new requirements are put forward for car-gauge cameras. High-level autopilot initiates new semiconductor demands: the automobile running at high speed requires a higher frame rate and makes a judgment on the obtained image by rapid transmission analysis. The method has great potential for realizing the application of the CMOS image sensor in the vehicle camera by modifying the vertical gate between the photodiode and the suspension diffusion region. The current designs for vertical gates are mainly: 1. the uniformity of doping is improved through multiple doping and multiple grid electrodes; 2. many VTG structures are designed for improving electron transfer efficiency: concave-convex surface, fin-shaped surface, inclined surface transfer and other structures; 3. heteroatom doping and the like are performed to reduce impurities and defects in the VTG. These methods generally have problems that the preparation process is complicated and difficult to control or metal pollution is easily caused.
In one 4T pixel structure, as shown in fig. 1, photo-generated carriers accumulated in the Photodiode (PD) 200 are transferred into the floating diffusion region (FD) 500, wherein charges are converted into a voltage value, and incomplete transfer of charges from the Photodiode (PD) 200 to the floating diffusion region (FD) 500 causes image lag. As shown in the potential schematic of fig. 2, VTG indicates where the vertical gate is located, and the main reason for incomplete charge transfer is the obstruction or pocket created by the transfer tube. A potential barrier exists at the vertical gate of the transfer tube, which is a low potential region and also a high electron potential region, so that electrons having energies lower than the potential barrier energy may not be transferred to the floating diffusion region (FD).
It should be noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a CMOS image sensor and a manufacturing method of a vertical gate thereof, which are used for solving the problem of incomplete charge transfer.
In order to solve the above technical problems, the present invention provides a method for manufacturing a vertical gate of a CMOS image sensor, comprising the steps of:
Providing a substrate, forming a photodiode in the substrate, and a floating diffusion region adjacent to the photodiode;
Forming a trench between the photodiode and the floating diffusion region, and performing ion implantation at a predetermined depth of the trench, wherein one side of the trench, which is close to the photodiode, is denoted as a first side, the other side is denoted as a second side, and the ion concentration at the first side is lower than the ion concentration at the second side;
And filling polycrystalline silicon in the groove, depositing polycrystalline silicon on the substrate to form a polycrystalline silicon layer, and etching the polycrystalline silicon layer to form a vertical gate.
Preferably, after forming the trench, before ion implantation is performed at a predetermined depth of the trench: an oxide layer is also formed on the surface of the substrate and the inner wall of the trench.
Preferably, ion implantation is performed at a predetermined depth of the trench: ion implanting the first side and the second side sequentially or ion implanting the second side only.
Preferably, the difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3.
Preferably, the difference between the ion concentration at the first side and the ion concentration at the second side is 1 x 10 10atoms/cm3.
Preferably, after the vertical gate is formed, side walls are also formed on two sides of the vertical gate.
A CMOS image sensor, comprising:
A substrate on which a trench is formed, both sides of the trench being provided with a photodiode and a floating diffusion region, respectively;
And a vertical gate extending into the substrate through the trench, wherein one side of the trench, which is close to the photodiode, is denoted as a first side, the other side is denoted as a second side, and at least one ion implantation region is formed at a side wall of the trench so that the ion concentration at the first side is lower than the ion concentration at the second side.
Preferably, an oxide layer is further arranged between the inner wall of the groove and the vertical gate.
Preferably, the first side and the second side have an ion implantation region or only the second side has an ion implantation region, respectively.
Preferably, the difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3.
Preferably, the difference between the ion concentration at the first side and the ion concentration at the second side is 1 x 10 10atoms/cm3.
Preferably, the top of the vertical gate extends out of the groove, and side walls are further arranged on two sides of the top of the vertical gate.
According to the manufacturing method of the vertical gate of the CMOS image sensor, provided by the invention, the ion concentration difference is formed at the groove, so that the transverse electric field is improved, the photoelectric transmission performance of the vertical gate is improved, photoelectrons in the deep part of the photodiode are read out, and the occurrence of image residues is avoided. Meanwhile, the pocket effect is reduced, so that the electron residual is minimized, the afterimage image lag of the CMOS image sensor is obviously improved, and the image refresh rate is obviously improved. Further, the method is suitable for various vertical gate structures, and is beneficial to improving the limitation of small size on pixel performance and improving image quality.
The CMOS image sensor provided by the present invention and the method for manufacturing the vertical gate of the CMOS image sensor provided by the present invention belong to the same inventive concept, so that the CMOS image sensor provided by the present invention has at least all advantages of the method for manufacturing the vertical gate of the CMOS image sensor provided by the present invention, and will not be described herein. A CMOS image sensor, comprising: and a substrate on which a trench is formed, wherein both sides of the trench are respectively provided with a photodiode and a floating diffusion region. And a vertical gate extending into the substrate through the trench, wherein a side of the trench adjacent to the photodiode is designated as a first side and the other side is designated as a second side, and at least one ion implantation region (not shown) is provided at a sidewall of the trench such that an ion concentration at the first side is lower than an ion concentration at the second side. The cross section of the ion concentration transverse difference is formed at the vertical grid, so that the transverse electric field is improved, the transfer process of photoelectrons is accelerated, and the method is suitable for various vertical grid structures.
Drawings
FIG. 1 is a schematic diagram of a partial structure of a pixel unit in the prior art;
FIG. 2 is a schematic diagram of the potential at a vertical gate in the prior art;
FIG. 3 is a flow chart of a method for fabricating a vertical gate of a CMOS image sensor according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a photodiode and floating diffusion according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view illustrating a trench formation in accordance with an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view illustrating an oxide layer formation according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view illustrating a polysilicon layer formed according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a vertical gate according to an embodiment of the present invention;
FIG. 9 is a top view of a vertical gate formed in accordance with one embodiment of the present invention;
fig. 10 is a schematic diagram of the potential at the vertical gate in accordance with an embodiment of the invention.
In the figures 1-2 of the drawings,
100. A substrate; 200. a photodiode; 300. a vertical gate; 400. a P-type isolation region; 500. and floating diffusion regions.
In the figures 3-10 of the drawings,
1. A substrate; 2. a photodiode; 3. a P-well; 4. a floating diffusion region; 5. a groove; 6. an oxide layer; 7. a polysilicon layer; 8. and (5) vertical gates.
Detailed Description
The CMOS image sensor and the method for manufacturing the vertical gate thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It should be understood that the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Specific design features of the invention disclosed herein, including for example, specific dimensions, orientations, positions, and configurations, will be determined in part by the specific intended application and use environment. In the embodiments described below, the same reference numerals are used in common between the drawings to denote the same parts or parts having the same functions, and the repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The inventors have found that photogenerated carriers generated at the photodiode 200 need to be transferred to the floating diffusion region 4 through the vertical gate 300 as shown in fig. 1, however, a problem of incomplete electron transfer may occur due to an obstacle at the vertical gate 300, resulting in image lag.
Based on the above, the solid core idea of the invention is that the ion doping is carried out on the vertical grid, so that the cross section of the ion concentration transverse difference is formed on the vertical grid, the transverse electric field is improved, the transfer process of photoelectrons is accelerated, and the method is suitable for various vertical grid structures.
Specifically, please refer to fig. 3-10, which are schematic diagrams of an embodiment of the present invention. As shown in fig. 3, a method for manufacturing a vertical gate of a CMOS image sensor includes the steps of:
First, a substrate 1 is provided, a photodiode 2 is formed in the substrate 1, and a floating diffusion region 4 adjacent to the photodiode 2.
Next, a trench 5 is formed between the photodiode 2 and the floating diffusion region 4, and ion implantation is performed to a predetermined depth of the trench 5, wherein one side of the trench 5 near the photodiode 2 is denoted as a first side, the other side is denoted as a second side, and the ion concentration at the first side is lower than the ion concentration at the second side.
Finally, filling polysilicon in the groove 5, depositing polysilicon on the substrate 1 to form a polysilicon layer 7, and etching the polysilicon layer 7 to form a vertical gate 8.
By the technical scheme, the ion concentration difference is formed at the groove 5, and the transverse concentration difference is formed from the photodiode 2 to the floating diffusion region 4, so that the transverse electric field is improved, and the transfer process of photoelectrons is accelerated; meanwhile, the pocket effect is reduced, so that the electron residual is minimized, the afterimage image lag of the CMOS image sensor is obviously improved, and the image refresh rate is obviously improved. Further, the method is suitable for various vertical gate structures, and is beneficial to improving the limitation of small size on pixel performance and improving image quality.
Forming the photodiode 2, and forming the floating diffusion region 4 adjacent to the photodiode 2 includes: the photodiode 2 is formed on the substrate 1, then a P-well is formed on one side of the photodiode 2, and two N-wells are further formed in the P-well at a lateral interval, wherein the N-well close to the photodiode 2 is a floating diffusion region 4.
As shown in fig. 6, after forming the trench 5, before ion implantation is performed to a predetermined depth of the trench 5: an oxide layer 6 is also formed on the surface of the substrate 1 and on the inner walls of the trenches 5. Specifically, the oxide layer 6 is silicon oxide.
In one embodiment, the substrate 1 may be a silicon substrate, a semiconductor substrate including an epitaxial layer (epi-layer), or a silicon-on-insulator (SOI) substrate. The substrate 1 may also comprise any combination of one or more of silicon carbide, gallium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide.
Ion implantation is performed to a predetermined depth of the trench 5: ion implanting the first side and the second side sequentially or ion implanting the second side only. It is understood that the ion type implanted herein may be either N-type ions or P-type ions. The ion concentration difference may be formed in the direction from the photodiode 2 to the floating diffusion region 4 by ion implantation of the first side and the second side separately or ion implantation of the second side only, with different doses of ions being implanted to form a side having a higher ion concentration near the floating diffusion region 4 than the photodiode 2. The potentials of the formed transverse sections with different ion concentrations are shown in fig. 10, so that photoelectrons are more easily transferred, and the probability of incomplete transfer is reduced.
In one embodiment, the trench 5 is ion doped multiple times, and the ion implantation angle can be used to gradually increase the concentration gradient of the vertical gate 8 along the photodiode 2 to the floating diffusion region 4, so as to improve the transfer efficiency of photoelectrons. The number of ion implantation times and implantation angle are not particularly limited here, and may be modified according to specific production and manufacturing conditions.
In one example, the difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3, more preferably the difference between the ion concentration at the first side and the ion concentration at the second side is 1 x 10 10atoms/cm3. The ion concentration difference between the first side and the second side satisfies the transfer efficiency of photoelectrons, the electron residual is minimized, the residual image lag of the CMOS image sensor is obviously improved, and the image refresh rate is obviously improved.
As shown in fig. 8, after the vertical gate 8 is formed, side walls (not labeled) are also formed on both sides of the vertical gate 8. The step of forming the side wall comprises the steps of forming a material layer on the substrate 1 and the vertical gate 8, defining a side wall region through photoetching, and etching to form the side wall.
Based on the same inventive concept, as shown in fig. 8, the present disclosure also provides a CMOS image sensor, including:
A substrate 1 has a trench 5 formed thereon, both sides of the trench 5 being provided with a photodiode 2 and a floating diffusion region 4, respectively.
A vertical gate 8 extends into the substrate 1 through the trench 5, wherein one side of the trench 5 adjacent to the photodiode 2 is denoted as a first side and the other side is denoted as a second side, and the sidewall of the trench 5 has at least one ion implantation region (not shown) such that the ion concentration at the first side is lower than the ion concentration at the second side.
By the technical scheme, the ion concentration difference is formed at the groove 5, and the transverse difference is formed from the photodiode 2 to the floating diffusion region 4, so that the transverse electric field is improved, and the transfer process of photoelectrons is accelerated; meanwhile, the pocket effect is reduced, so that the electron residual is minimized, the afterimage image lag of the CMOS image sensor is obviously improved, and the image refresh rate is obviously improved. Further, the method is suitable for various vertical gate structures, and is beneficial to improving the limitation of small size on pixel performance and improving image quality.
The pixel structure of the CMOS image sensor in the embodiment of the present invention may be a pixel structure (not shown) in which 4 pixels share a floating diffusion point. For a plurality of pixel structures distributed in a pixel area, one pixel structure is described in the embodiment of the present invention. It will be appreciated that some of the pixel structures in the pixel region may be designed differently from the structures described in the present invention.
Specifically, an oxide layer 6 is further provided between the inner wall of the trench 5 and the vertical gate 8. The oxide layer 6 is made of silicon oxide, and it should be noted that after the oxide layer 6 is formed, P-type ions or N-type ions are implanted, so that a difference in ion concentration is formed at the trench 5.
Specifically, the first side and the second side have an ion implantation region or only the second side has an ion implantation region, respectively. The ion concentration difference is formed on both sides by performing ion implantation at the first side and the second side respectively or performing ion implantation only on the second side, or the ion concentration is formed in a gradient in the direction from the photodiode 2 to the floating diffusion region 4 by performing ion implantation a plurality of times, changing the ion implantation angle and the implantation dose, and the like.
Wherein the difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3. More preferably, the difference between the ion concentration at the first side and the ion concentration at the second side is 1 x 10 10atoms/cm3.
In one embodiment, as shown in fig. 8, the top of the vertical gate 8 extends out of the trench 5, and two sides of the top of the vertical gate 8 are provided with side walls (not labeled). The step of forming the side wall comprises the steps of forming a material layer on the substrate 1 and the vertical gate 8, defining a side wall region through photoetching, and etching to form the side wall.
In summary, in the method for manufacturing the CMOS image sensor and the vertical gate thereof provided by the embodiments of the present invention, a method for doping vertical gate ions is designed by utilizing the difference of different ion concentrations in the vertical gate channel to transfer electrons, so that electrons are rapidly transferred to a floating diffusion region in a step manner, and a lateral difference is formed between the photodiode and the floating diffusion region, thereby improving a lateral electric field and accelerating the transfer process of photoelectrons; meanwhile, the pocket effect is reduced, so that the electron residual is minimized, the afterimage image lag of the CMOS image sensor is obviously improved, and the image refresh rate is obviously improved. Further, the method is suitable for various vertical gate structures, and is beneficial to improving the limitation of small size on pixel performance and improving image quality.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method for fabricating a vertical gate of a CMOS image sensor, comprising the steps of:
Providing a substrate, forming a photodiode in the substrate, and a floating diffusion region adjacent to the photodiode;
Forming a trench between the photodiode and the floating diffusion region, and performing ion implantation at a predetermined depth of the trench, wherein one side of the trench, which is close to the photodiode, is denoted as a first side, the other side is denoted as a second side, and the ion concentration at the first side is lower than the ion concentration at the second side;
And filling polycrystalline silicon in the groove, depositing polycrystalline silicon on the substrate to form a polycrystalline silicon layer, and etching the polycrystalline silicon layer to form a vertical gate.
2. The method of manufacturing a CMOS image sensor vertical gate according to claim 1, wherein after forming the trench, before ion implantation is performed at a predetermined depth of the trench: an oxide layer is also formed on the surface of the substrate and the inner wall of the trench.
3. The method of manufacturing a CMOS image sensor vertical gate according to claim 1, wherein ion implantation is performed to a predetermined depth of the trench: ion implanting the first side and the second side sequentially or ion implanting the second side only.
4. The method of fabricating a CMOS image sensor vertical gate according to claim 1, wherein a difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3.
5. The method of manufacturing a vertical gate of a CMOS image sensor according to claim 1, wherein after the vertical gate is formed, side walls are further formed on both sides of the vertical gate.
6. A CMOS image sensor, comprising:
A substrate on which a trench is formed, both sides of the trench being provided with a photodiode and a floating diffusion region, respectively;
And a vertical gate extending into the substrate through the trench, wherein one side of the trench, which is close to the photodiode, is denoted as a first side, the other side is denoted as a second side, and at least one ion implantation region is formed at a side wall of the trench so that the ion concentration at the first side is lower than the ion concentration at the second side.
7. The CMOS image sensor of claim 6, wherein an oxide layer is further provided between the inner walls of the trench and the vertical gate.
8. The CMOS image sensor of claim 6, wherein the first side and the second side each have an ion implantation region or only the second side has an ion implantation region.
9. The CMOS image sensor of claim 6, wherein a difference between the ion concentration at the first side and the ion concentration at the second side is greater than 1 x 10 5atoms/cm3.
10. The CMOS image sensor of claim 6, wherein the top of the vertical gate extends beyond the trench, and wherein the top sides of the vertical gate further have sidewalls.
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