CN118016669A

CN118016669A - Integrated circuit device and method of manufacturing the same

Info

Publication number: CN118016669A
Application number: CN202311779479.9A
Authority: CN
Inventors: 许嘉麟; 苏郁迪
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-01-18
Filing date: 2023-12-20
Publication date: 2024-05-10

Abstract

Embodiments of the present application provide an Integrated Circuit (IC) device and a method of manufacturing the same. The IC device includes a substrate, a first semiconductor device and a second semiconductor device respectively located in different first and second doped regions in the substrate. The gate of the first semiconductor device is electrically coupled to the source/drain of the second semiconductor device. The IC device further includes a first protection device configured as one of the first forward diode and the first reverse diode, and a second protection device configured as the other of the first forward diode and the first reverse diode. The first forward diode and the first reverse diode are electrically coupled in series between the substrate and the doped well. The doped well is located in the first doped region, and the source/drain of the first semiconductor device is located in the doped well. Or the doped well is located in the second doped region and the source/drain of the second semiconductor device is located in the doped well.

Description

Integrated circuit device and method of manufacturing the same

Technical Field

Embodiments of the application relate to an integrated circuit device and a method of manufacturing the same.

Background

Recent trends in the miniaturization of Integrated Circuit (IC) devices have resulted in smaller semiconductor devices that consume less power, but provide more functionality at higher speeds. The miniaturization process also increases the susceptibility of the semiconductor device to damage due to various factors such as thinner gate dielectric thickness, lower dielectric breakdown voltage, etc. Antenna effects are one of the causes of circuit damage in IC devices and are also a consideration in advanced semiconductor technology.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided an integrated circuit device including: a substrate; a first semiconductor device located in a first doped region in the substrate; and a second semiconductor device in a second doped region in the substrate, wherein the first doped region and the second doped region are different from each other, and a gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The integrated circuit device further includes: a first protection device configured as one of a first forward diode and a first reverse diode; and a second protection device configured as the other of the first forward diode and the first reverse diode, the first forward diode and the first reverse diode being electrically coupled in series between the substrate and the doped well, wherein the doped well is located in the first doped region and the source/drain of the first semiconductor device is located in the doped well, or the doped well is located in the second doped region and the source/drain of the second semiconductor device is located in the doped well.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit device including: a substrate; a first doped well over the substrate; a first diode located above the substrate; a second diode over the substrate; a first electrical connection electrically coupling an anode or a cathode of the first diode to the first doped well; and a second electrical connection electrically coupling an anode or a cathode of the second diode to the substrate, wherein the anode of the first diode and the anode of the second diode are electrically coupled to each other or the anode of the first diode and the cathode of the second diode are electrically coupled to each other.

According to yet another aspect of an embodiment of the present application, there is provided a method of manufacturing an integrated circuit device, the method comprising: performing a dopant implantation to form a first doped well, a second doped well, a first P-N junction, and a second P-N junction over the substrate, wherein the substrate includes another region outside of the first doped well and the second doped well; depositing and patterning a gate over the first doped well; and depositing and patterning an interconnect over the substrate to electrically couple the first P-N junction and the second P-N junction in series between the other region of the substrate and one of the first doped well and the second doped well, wherein the P-type region of the first P-N junction and the P-type region of the second P-N junction are electrically coupled to each other, or the N-type region of the first P-N junction and the N-type region of the second P-N junction are electrically coupled to each other, and then electrically coupling the gate over the first doped well to the second doped well.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A is a schematic cross-sectional view of an IC device according to some embodiments.

Fig. 1B is a schematic circuit diagram of an IC device according to some embodiments.

Fig. 2 includes a schematic circuit diagram of various protection devices according to some embodiments.

Fig. 3A-3E, 4A-4B, 5A-5B, 6A-6B are schematic cross-sectional views of various protection devices according to some embodiments.

Fig. 7A-7F include schematic circuit diagrams of various protection circuits according to some embodiments.

Fig. 8A-8B are flowcharts of various methods of manufacturing an IC device, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Depending on the context, source/drain may refer to source or drain individually or collectively.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

In a manufacturing process of an IC device, a transistor is formed over a substrate. Each transistor includes a gate electrode and a gate dielectric between the gate electrode and the substrate. The gate dielectric is an oxide or another gate dielectric material. In a fabrication operation after transistor formation, various dielectric and metal layers are deposited and patterned to obtain conductive vias and/or patterns that are electrically coupled to the gate electrode of the transistor. Deposition and/or patterning operations typically include plasma operations, such as plasma etching operations, plasma deposition operations, and the like. In plasma operation, it is possible to accumulate a sufficient amount of charge in the conductive patterns, vias and/or doped wells coupled to the gate electrodes and cause breakdown of the underlying gate dielectric and damage to the corresponding transistor. This problem is known as "plasma induced gate oxide damage" (PID) or "antenna effect" and may lead to yield and/or reliability problems during semiconductor fabrication. PID problems include metal PID problems and trap PID problems. The metal PID problem is a PID problem related to the charge accumulated on metal components such as conductive patterns and/or vias. The well PID problem is a PID problem associated with charges accumulated in a doped well on which a gate and a gate dielectric are formed or to which the gate is electrically coupled. PID protection circuits and/or PID protection devices are included in the IC device to protect other transistors and/or circuits from damage due to antenna effects or PID.

In some embodiments, the PID protection circuit in the IC device comprises at least a pair of PID protection devices, respectively configured to electrically couple in series a forward diode and a reverse diode between the doped well and the substrate on which the doped well is formed. Examples of PID protection devices include, but are not limited to, N-type diodes, P-type diodes, diode-connected Metal Oxide Semiconductor (MOS) transistors, diode-connected Bipolar Junction Transistors (BJTs), or any device having a P-N junction or a configuration P-N junction. In at least one embodiment, the reverse diode is configured to discharge charge accumulated in the doped well during fabrication of the IC device to the substrate through leakage current of the reverse diode. Thus, in one or more embodiments, the trap PID problem is avoided or alleviated, particularly in some process nodes and/or circuit designs where the trap PID problem is of concern due to large differences in trap dimensions. In at least one embodiment, the forward diode is configured to withstand an operating voltage applied across the doped well and the substrate by itself or in combination with the reverse diode during operation of the IC device. Thus, in one or more embodiments, direct Current (DC) requirements related to operating voltage may be met in addition to PID requirements. This is an improvement over other approaches in that a single diode discharging the charge accumulated in the doped well may not be sufficient to maintain a high operating voltage (e.g., 36V) in operation. In some embodiments, one or more further advantages may be realized, including, but not limited to, low chip area impact, no impact on the function and/or operation of the IC device, no electrostatic discharge (ESD) problems, suitability for various designs with different voltage applications, suitability for each technology node (or process node), etc.

Fig. 1A is a schematic cross-sectional view of an IC device 100A according to some embodiments.

The IC device 100A includes a substrate 110, the substrate 110 having a front side 111 and a back side 112 in a thickness direction of the IC device 100A. The thickness direction is designated as the Z-axis in fig. 1A. In the example configuration in fig. 1A, the substrate 110 is a P-type substrate (also referred to as a P-substrate). In some embodiments, the substrate 110 includes: elemental semiconductor including silicon or germanium in crystalline, polycrystalline or amorphous structure; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and GaInAsP; any other suitable material; combinations thereof, and the like. In some embodiments, the alloy semiconductor substrate has a graded SiGe feature in which Si and Ge composition changes from one ratio at one location of the graded SiGe feature to another ratio at another location. In some embodiments, alloy SiGe is formed on a silicon substrate. In some embodiments, the substrate 110 comprises a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. In at least one embodiment, the substrate 110 comprises an N-type substrate (also referred to as an N-substrate). One of the N-type and P-type is an example of a first conductivity, and the other of the N-type and P-type is an example of a second conductivity opposite the first conductivity. The region having P-type conductivity is a P-type region. Examples of P-type regions include, but are not limited to, regions of a P-type substrate, P-doped regions, P-wells, and the like. The region having N-type conductivity is an N-type region. Examples of N-type regions include, but are not limited to, regions of an N-type substrate, N-doped regions, N-wells, and the like.

The IC device 100A further includes a first doped region NBL-a and a second doped region NBL-B on the front side 111 of the substrate 110. Doped region NBL-B is different from doped region NBL-A. For example, the doped region NBL-B is physically and/or electrically isolated from the doped region NBL-A by an isolation structure, such as a Shallow Trench Isolation (STI) region. In another example, doped region NBL-B is discontinuous with doped region NBL-A. In the example configuration in fig. 1A, each of doped regions NBL-a and NBL-B is an N-type doped region that is a volume within substrate 110 that includes one or more N-type dopants (e.g., phosphorus or arsenic) and has a doping concentration sufficient to form a P-N junction with a surrounding portion of substrate 110. In some embodiments, the N-type doped regions are referred to as N+ Buried Layers (NBL) or deep N-wells (DNWs), and the doped regions NBL-A and NBL-B are sometimes referred to as doped regions DNW-A and DNW-B, respectively. In at least one embodiment, for example, when substrate 110 is an N-type substrate, at least one of doped region NBL-A or doped region NBL-B is a P-type doped region, such as a deep P-well (DPW). The number and/or conductivity type of doped regions on the substrate 110 described is an example. Other doped region configurations are within the scope of the various embodiments.

The doped region NBL-A includes therein a P-well PW1 and an N-well NW1. The doped region NBL-B includes therein a P-well PW2 and an N-well NW2. In some embodiments, IC device 100A also includes isolation structures (not shown) that electrically isolate adjacent P-wells and N-wells, e.g., P-well PW1 from N-well NW1 and/or P-well PW2 from N-well NW2. In at least one embodiment, P-well PW1 and N-well NW1 together form a P-N junction, and/or P-well PW2 and N-well NW2 together form a P-N junction. A P-well, such as P-well PW1 or P-well PW2, is a volume that includes one or more P-type dopants in a corresponding doped region and has a doping concentration sufficient to form one or more N-type semiconductor devices thereon. An N-well, such as N-well NW1 or N-well NW2, is a volume that includes one or more N-type dopants within a corresponding doped region and has a doping concentration sufficient to form one or more P-type semiconductor devices thereon. P-wells (denoted by reference numeral "PW" in the figures) and N-wells (denoted by reference numeral "NW" in the figures) are examples of doped wells. In the example configuration in fig. 1A, the transistor P1 and the transistor P2 are examples of P-type semiconductor devices formed on the corresponding N-well NW1 and N-well NW2, and the transistor N1 and the transistor N2 are examples of N-type semiconductor devices formed on the corresponding P-well PW1 and P-well PW 2. Other semiconductor device configurations, such as diodes, are within the scope of the various embodiments.

As described herein, semiconductor devices in the P-well and/or N-well on the substrate 110 are electrically coupled to one another to form one or more functional circuits. The functional circuitry is configured to perform desired functions of the IC device 100A, such as data processing, data storage, input/output (I/O), and the like. Examples of one OR more circuits, logic, OR cells included in a functional circuit include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OAI, MUX, flip-flop, BUFF, latch, delay, clock, memory such as Static Random Access Memory (SRAM), decoupling capacitors, analog amplifiers, logic drivers, digital drivers, AND the like. In some embodiments, the circuitry, logic, or cells included in the functional circuitry include functional transistors or core transistors that are protected from antenna effects during fabrication of the IC device 100A. Examples of transistors in functional circuits and other circuits described herein include, but are not limited to, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, P-channel metal oxide semiconductor, high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFET/NFET), finfets, planar MOS transistors with raised source/drain, nanoplatelet FETs, nanowire FETs, and the like. In addition to functional circuitry, the IC device 100A includes one or more PID protection circuits, as described herein.

A semiconductor device includes a gate and source/drain. A detailed description of the transistor N1 is given herein. Specifically, transistor N1 includes a gate structure 120, gate structure 120 having a gate dielectric 121 over P-well PW and a gate electrode or gate 122 over gate dielectric 121. Example conductive materials for the gate 122 include, but are not limited to, polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and the like. Example materials for gate dielectric 121 include, but are not limited to, silicon dioxide, silicon nitride (Si ₃N₄), low-k materials with k values less than 3.8, high-k materials with k values greater than 3.8, such as aluminum oxide (Al ₂O₃), hafnium oxide (HfO ₂), tantalum pentoxide (Ta ₂O₅), or titanium oxide (TiO ₂), among others. In some embodiments, IC device 100A further includes sidewalls (not shown in fig. 1A) on opposite sides of gate structure 120. Exemplary sidewalls are described with respect to fig. 4A-4B.

Transistor N1 also includes source/drains 123, 124 located above P-well PW 1. Each of the source/drains 123, 124 is an N-doped region with N-type dopants implanted into the P-well PW 1. In some embodiments, one or more of the source/drains 123, 124 extend over the front side 111 of the substrate 110. In some embodiments, the IC device 100A further includes lightly doped regions (not shown in fig. 1A) adjacent to the source/drains 123, 124 and below the sidewalls. In some embodiments, the first element and the second element being adjacent to each other includes a situation in which the first element is directly adjacent to the second element. In some embodiments, the first element and the second element being adjacent to each other includes a case where an intermediate element is positioned between the first element and the second element. In some embodiments, the lightly doped region is configured to maintain a low leakage current of transistor N1. An exemplary lightly doped region is described with respect to fig. 4A-4B.

IC device 100A also includes a body contact 125 as a P-doped region in P-well PW 1. In some embodiments, body contact 125 is configured and/or fabricated in the same manner and/or at the same time as the source/drains of P-type semiconductor devices, such as transistor P1 and transistor P2. The body contacts in the doped well are sometimes referred to as well taps. The bulk contacts in the substrate are sometimes referred to as substrate taps. The body contacts are configured to provide electrical connection to a corresponding doped well or substrate. For example, body contact 125 is configured to provide an electrical connection to P-well PW 1. In the example configuration in fig. 1A, body contact 125 is configured to provide an electrical connection between P-well PW1 and PID protection circuit 171, as described herein. In some embodiments, P-well PW1 further includes another body contact configured to electrically couple P-well PW1 to a reference voltage, such as ground voltage VSS, to prevent leakage of transistor N1 and/or other N-type semiconductor devices formed over P-well PW 1. In some embodiments, body contact 125 is configured as a common electrical connection from P-well PW1 to PID protection circuit 171 and VSS. In some embodiments, VSS is supplied to P-well PW1 from a VSS supply rail (not shown) on the back side 112 of substrate 110, with or without a well tap on front side 111. In some embodiments, source/drain 124 is electrically coupled to body contact 125.

The configuration of transistor P1 above P-well PW1 is similar to transistor N1, except that the N-type and P-type components (e.g., doped regions, doped wells, etc.) of transistor P1 correspond to the P-type and N-type components of transistor N1. For example, transistor P1 includes gate dielectric 131, gate 132, source/drain 133, 134, and body contact 135 corresponding to gate dielectric 121, gate 122, source/drain 123, 124, and body contact 125 of transistor N1. Body contact 135 is an N-doped region configured to electrically couple N-well NW1 to a supply voltage (e.g., VDD) to prevent leakage of transistor P1 and/or other P-type semiconductor devices formed over N-well NW 1. In some embodiments, the N-well NW1 further comprises another body contact configured to provide an electrical connection between the N-well NW1 and the PID protection circuit, e.g., as described with respect to fig. 1B. In some embodiments, body contact 135 is configured as a common electrical connection from N-well NW1 to the PID protection circuit and VDD. In some embodiments, VDD is provided to N-well NW1 from a VDD power rail (not shown) on back side 112 of substrate 110 with or without a well tap on front side 111. In the example configuration in fig. 1A, the source/drain 134 of transistor P1 is electrically coupled to the body contact 135. Other configurations are within the scope of the various embodiments. For example, in one or more embodiments, the source/drain 134 is not electrically coupled to the body contact 135.

Transistor N2 over P-well PW2 is configured similarly to transistor N1 and includes source/drains 143, 144 and body contact 145 corresponding to source/drains 123, 124 and body contact 125 of transistor N1. In the example configuration in FIG. 1A, body contact 145 is a P-doped region configured to electrically couple P-well PW2 to VSS. In some embodiments, P-well PW2 further includes another body contact configured to provide an electrical connection between P-well PW2 and a PID protection circuit, e.g., as described with respect to fig. 1B. In some embodiments, body contact 145 is configured as a common electrical connection from P-well PW2 to the PID protection circuit and VSS. In some embodiments, VSS is supplied to P-well PW2 from a VSS supply rail (not shown) on the back side 112 of substrate 110, with or without a well tap on front side 111. In the example configuration in fig. 1A, the source/drain 144 of transistor N2 is electrically coupled to the body contact 145. Other configurations are within the scope of the various embodiments. For example, in one or more embodiments, the source/drain 144 is not electrically coupled to the body contact 145.

The transistor P2 over the N-well NW2 is configured similarly to the transistor P1 and includes source/drains 153, 154 and body contacts 155 corresponding to the source/drains 133, 134 and body contacts 135 of the transistor P1. In the example configuration in fig. 1A, the body contact 155 is an N-doped region configured to electrically couple the N-well NW2 to the PID protection circuit 172, as described herein. In some embodiments, N-well NW2 further includes another body contact configured to provide an electrical connection between N-well NW2 and VDD. In some embodiments, the body contact 155 is configured as a common electrical connection from the N-well NW2 to the PID protection circuit 172 and VDD. In some embodiments, VDD is provided to N-well NW2 from a VDD power rail (not shown) on back side 112 of substrate 110 with or without a well tap on front side 111. In some embodiments, the source/drain 154 is electrically coupled to the body contact 155.

The IC device 100A also includes contact structures (not shown) over and in electrical contact with the corresponding source/drains of the transistors N1, P1, N2, P2. The contact structure is sometimes referred to as a metal-to-device (MD) contact structure. The MD contact structure includes a conductive material, such as a metal, formed over the corresponding source/drain electrodes to define electrical connections between the semiconductor devices of the IC device 100A, thereby forming one or more functional circuits and/or PID protection circuits. In some embodiments, MD contact structures are formed over one or more of the body contacts 125, 135, 145, 155.

The IC device 100A also includes vias (not shown) over and in electrical contact with the respective gate and MD contact structures. The vias that are located over and in electrical contact with the MD contact structures are sometimes referred to as via-to-device (VD) vias. The via located above and in electrical contact with the gate is sometimes referred to as a via-to-gate (VG) via. Example materials for VD and/or VG vias include metals. Other configurations are within the scope of the various embodiments.

The IC device 100A further includes a redistribution structure 160 over the VD, VG vias. The redistribution structure 160 includes a plurality of metal layers and via layers sequentially and alternately arranged over VD, VG vias. The redistribution structure 160 further includes various inter-layer dielectric (ILD) layers (not shown) having metal layers and via layers embedded therein. The metal layer and the via layer of the redistribution structure 160 are configured to electrically couple the various elements or circuits of the IC device 100A to each other and to external circuitry. In the redistribution structure 160, the lowest metal layer immediately above and in electrical contact with the VD, VG vias is the M0 (metal zero) layer, the next metal layer immediately above the M0 layer is the M1 layer, the next metal layer immediately above the M1 layer is the M2 layer, and so on. The conductive pattern in the M0 layer is referred to as an M0 conductive pattern, the conductive pattern in the M1 layer is referred to as an M1 conductive pattern, and so on. The via layer Vm is disposed between and electrically couples the Mm layer and the mm+1 layer, where m is an integer greater than zero. For example, the via zero (V0) layer is the lowermost via layer disposed between the M0 layer and the M1 layer and electrically coupling the M0 layer and the M1 layer. The other via layers are via layers such as V1 and V2. The via in the V0 layer is referred to as a V0 via, the via in the V1 layer is referred to as a V1 via, and so on. For simplicity, the metal layers and via layers in the redistribution structure 160 are not fully shown in fig. 1A.

In the example configuration in fig. 1A, the redistribution structure 160 includes a conductive structure 161, the conductive structure 161 including conductive patterns in various metal layers and corresponding vias in various via layers and being electrically coupled to the source/drain 134 and the body contact 135 over the N-well NW 1. The redistribution structure 160 further includes a conductive structure 162, the conductive structure 162 including conductive patterns in various metal layers (e.g., M0 through Mn, where n is a positive integer) and corresponding vias in various via layers (e.g., V0 through Vn), and electrically coupled to the source/drain 144 and the body contact 145 over the P-well PW2. In some embodiments, conductive structure 161 is configured to electrically couple the VDD supply rail to N-well NW1 and/or conductive structure 162 is configured to electrically couple the VSS supply rail to P-well PW2. In some embodiments, IC device 100A includes conductive structures similar to conductive structures 161, 162 and is electrically coupled to P-well PW1 and/or N-well NW2.

The redistribution structure 160 further includes an interconnect 163. In some embodiments, the interconnect is a collection of one or more conductive patterns and one or more vias on the substrate 110 that together electrically couple circuit elements (e.g., semiconductor devices). In the example configuration in fig. 1A, the interconnect 163 includes conductive patterns in various metal layers (e.g., M0 through Mk, where k is a positive integer) and corresponding vias in various via layers, and electrically couples the source/drains 143, 153 to the gates 122, 132. The Mk layer is the highest metal layer that includes the conductive pattern of the interconnect 163. Interconnect 163 is an example of a signal path from one or more semiconductor devices (e.g., transistors N1, P1) to one or more additional semiconductor devices (e.g., transistors N2, P2). Interconnect 163 is also an example showing that an N-well (e.g., N-well NW 2) or a P-well (e.g., P-well PW 2) may be electrically connected to a gate (e.g., 122) over another P-well (e.g., P-well PW 1) and/or a gate (e.g., 132) over another N-well (e.g., N-well NW 1). In some embodiments, the interconnect 163 is electrically coupled to one, but not both, of the source/drains 143, 153 and/or to one, but not both, of the gates 122, 132. Other configurations are within the scope of the various embodiments.

During fabrication/fabrication of IC device 100A, and in particular during fabrication/fabrication of redistribution structure 160 from the M0 layer upwards, positive and/or negative charges potentially accumulate in one or more of N-well NW1, P-well PW1, N-well NW2, P-well PW 2. For example, when conductive structure 161 is fabricated, charge is potentially accumulated in N-well NW1 due to the electrical connection between N-well NW1 and conductive structure 161 through source/drain 134 and/or body contact 135. For example, when conductive structure 162 is fabricated, charge is potentially accumulated in P-well PW2 due to the electrical connection between P-well PW2 and conductive structure 162 through source/drain 144 and/or body contact 145. Similarly, charges potentially accumulate in P-well PW1 and/or N-well NW 2. In some cases, negative charges often accumulate in the P-well and/or positive charges often accumulate in the N-well.

When fabrication of the interconnect 163 is completed, the potential of the charge accumulated in the P-well PW2 and/or N-well NW2 is applied to the gates 122, 132 through the completed interconnect 163. There is a risk of: such a potential, together with the potential of the charge accumulated in the P-well PW1 or N-well NW1, generates an undesirably high voltage across the corresponding gate dielectric 121 or 131, thereby causing an undesirable PID to the gate dielectrics 121 and 131. In some cases, negative charges accumulated in P-wells (e.g., P-well PW1 and P-well PW 2) may potentially damage the gate dielectric of an N-type semiconductor device (e.g., transistor N1), and/or positive charges accumulated in N-wells (e.g., N-well NW1, N-well NW 2) may potentially damage the gate dielectric of a P-type semiconductor device (e.g., transistor P1). One of the positive and negative charges is an example of a charge of a first polarity and the other of the positive and negative charges is an example of a charge of a second polarity opposite to the first polarity. Semiconductor devices (e.g., transistors N2, P2) that potentially lead to PID to other semiconductor devices are sometimes referred to as PID aggressors. Semiconductor devices (e.g., transistors N1, P1) that are potentially susceptible to PID effects caused by other semiconductor devices are sometimes referred to as PID victims.

In some embodiments, to prevent or at least mitigate PID problems, charges in one or more of N-well NW1, P-well PW1, N-well NW2, and P-well PW2 are discharged by one or more corresponding PID protection circuits before fabrication of interconnect 163 is completed. In the example configuration in fig. 1A, the IC device 100A includes PID protection circuits 171, 172 corresponding to the P-well PW1 and the N-well NW 2. In at least one embodiment, one or more of N-well NW1, P-well PW2 further comprises one or more corresponding PID protection circuits, e.g., as described with respect to FIG. 1B.

The PID protection circuit 171 includes PID protection devices 175, 176 electrically coupled in series between the substrate 110 and the P-well PW 1. PID protection devices 175, 176 are schematically illustrated in fig. 1A and are formed in or on the substrate 110 in one or more embodiments. For example, the PID protection devices 175, 176 include one or more of N-doped regions, P-doped regions, body contacts (or taps), N-wells, and/or P-wells configured and/or fabricated similar to one or more of the N-doped regions, P-doped regions, body contacts (or taps), N-wells, and/or P-wells described with respect to transistors N1, P1, N2, P2. Examples of PID protection devices include, but are not limited to, N-type diodes, P-type diodes, diode-connected MOS transistors, diode-connected BJTs, or any device having a P-N junction or a configuration P-N junction.

In the PID protection circuit, one of the PID protection devices is configured as a forward diode, and the other PID protection device is configured as a reverse diode. For example, in the PID protection circuit 171, the PID protection device 175 is configured as a forward diode, while the PID protection device diode 176 is configured as a reverse diode, or vice versa. For simplicity, PID protection devices are sometimes referred to herein as protection devices or diodes. Diode 175 has an anode 165 electrically coupled to P-well PW1 through body contact 125, and a cathode (not numbered) coupled to the cathode (not numbered) of diode 176. Diode 176 has anode 166 electrically coupled to substrate 110, for example, at region 116 outside of doped regions NBL-A and NBL-B.

In some embodiments, the anode 165 of the diode 175 is electrically coupled to the body contact 125 through one or more MD contact structures, VD vias, and first interconnects. In some embodiments, the anode 166 of the diode 176 is electrically coupled to a body contact or substrate tap on the front side 111 of the substrate 110 through one or more MD contact structures, VD vias, and a second interconnect. The second interconnect is not fully shown for simplicity. The Mi layer is the highest metal layer comprising the conductive pattern of the first interconnect or the second interconnect, where i is an integer less than k. For example, in one or more embodiments, k=3 and i=0. As a result, when the Mi layer (e.g., M0 layer where i=0) is formed and before the interconnect 163 is completed (e.g., before the M3 layer is formed where k=3), the PID protection circuit 171 is electrically coupled between the P-well PW1 and the substrate 110. In the example configuration in fig. 1A, the highest Mi conductive pattern is in the first interconnect between anode 165 and body contact 125. In another example, the highest Mi conductive pattern is in a second interconnect (not shown) between the anode 166 and the substrate 110. In another example, each of the first and second interconnects includes a corresponding Mi conductive pattern. In at least one embodiment, at least one of the first interconnect or the second interconnect is omitted. For example, in one or more embodiments, the region 116 of the substrate 110 forms part of the diode 176 and the second interconnect is omitted.

The PID protection circuit 171 electrically coupled between the P-well PW1 and the substrate 110 is configured to discharge the charge accumulated in the P-well PW1 to the substrate 110. For example, diode 175 is turned on when the potential of P-well PW1 is higher than the potential of substrate 110 due to, for example, positive charges accumulated in P-well PW 1. Positive charge accumulated in the P-well PW1 passes through the turned-on diode 175 and then discharges to the substrate 110 through the leakage current of the diode 176, as schematically shown by the arrows in fig. 1A. For example, diode 176 is turned on when the potential of P-well PW1 is lower than the potential of substrate 110 due to, for example, negative charge accumulated in P-well PW 1. Negative charges accumulated in the P-well PW1 are discharged by the leakage current of the diode 175, and then reach the substrate 110 through the turned-on diode 176.

The PID protection circuit 172 includes PID protection devices 177, 178 electrically coupled in series between the substrate 110 and the N-well NW 2. PID protection devices 177, 178 are schematically illustrated in fig. 1A and are formed in or on the substrate 110 in one or more embodiments. For example, the PID protection devices 177, 178 include one or more of N-doped regions, P-doped regions, body contacts (or taps), N-wells, and/or P-wells configured and/or fabricated similar to one or more of the N-doped regions, P-doped regions, body contacts (or taps), N-wells, and/or P-wells described with respect to the transistors N1, P1, N2, P2. Examples of PID protection devices include, but are not limited to, N-type diodes, P-type diodes, diode-connected MOS transistors, diode-connected BJTs, or any device having a P-N junction or a configuration P-N junction.

In the PID protection circuit 172, the PID protection device 177 is configured as a reverse diode, and the PID protection device diode 178 is configured as a forward diode, or vice versa. For simplicity, the PID protection devices 177, 178 are sometimes referred to herein as protection devices or diodes. Diode 177 has a cathode 167 electrically coupled to N-well NW2 through body contact 155 and an anode (not numbered) coupled to the anode (not numbered) of diode 178. Diode 178 has a cathode 168 electrically coupled to substrate 110, for example, at region 118 outside of doped regions NBL-A and NBL-B. In other words, unlike the protection circuit 171 in which the diodes 175, 176 have corresponding cathodes electrically coupled together, in the PID protection circuit 172, the diodes 177, 178 have corresponding anodes electrically coupled together. These are merely examples. In some embodiments, diodes 177, 178 have corresponding cathodes electrically coupled together, and/or diodes 175, 176 have corresponding anodes electrically coupled together.

In some embodiments, the cathode 167 of the diode 177 is electrically coupled to the body contact 155 through one or more MD contact structures, VD vias, and a third interconnect. In some embodiments, the cathode 168 of the diode 178 is electrically coupled to a body contact or substrate tap on the front side 111 of the substrate 110 through one or more MD contact structures, VD vias, and fourth interconnects. The fourth interconnect is not fully shown for simplicity. The Mj layer is the highest metal layer including the conductive pattern of the third interconnect or the fourth interconnect, where j is an integer less than k. In some embodiments, j is the same as i. In at least one embodiment, j is different from i. For example, in one or more embodiments, k=3 and j=0. As a result, the PID protection circuit 172 is electrically coupled between the N-well NW2 and the substrate 110 when the Mj layer (e.g., the M0 layer where j=0) is formed and before the interconnect 163 is completed (e.g., before the M3 layer is formed, where k=3). In the example configuration in fig. 1A, the highest Mj conductive pattern is in the third interconnect between the cathode 167 and the body contact 155. In another example, the highest Mj conductive pattern is in a fourth interconnect (not shown) between the cathode 168 and the substrate 110. In another example, each of the third interconnect and the fourth interconnect includes a corresponding Mj conductive pattern. In at least one embodiment, at least one of the third interconnect or the fourth interconnect is omitted. For example, in one or more embodiments, region 118 of substrate 110 forms part of diode 178 and the fourth interconnect is omitted.

The PID protection circuit 172 electrically coupled between the N-well NW2 and the substrate 110 is configured to discharge the charge accumulated in the N-well NW2 to the substrate 110. For example, when the potential of the N-well NW2 is lower than the potential of the substrate 110 due to, for example, negative charges accumulated in the N-well NW2, the diode 177 is turned on. Negative charges accumulated in the N-well NW2 pass through the turned-on diode 177 and then are discharged to the substrate 110 by leakage current of the diode 178. For another example, diode 178 is turned on when the potential of N-well NW2 is higher than the potential of substrate 110 due to, for example, positive charges accumulated in N-well NW 2. Positive charges accumulated in the N-well NW2 are discharged by leakage current of the diode 177 and then reach the substrate 110 through the turned-on diode 178.

The configuration described in which the cathodes of two serially coupled diodes are electrically coupled together (e.g., in PID protection circuit 171) or the anodes of two serially connected diodes are electrically coupled together (e.g., in PID protection circuit 172) is an example of what is sometimes referred to herein as a double reverse junction configuration.

In some embodiments, IC device 100A further includes a PID protection circuit similar to protection circuit 171 and electrically coupled between P-well PW2 and substrate 110, and/or a PID protection circuit similar to protection circuit 172 and electrically coupled between N-well NW1 and substrate 110. In at least one embodiment, positive and/or negative charges accumulated in the N-well NW1 and/or P-well PW2 are discharged to the substrate 110 by corresponding PID protection circuits in a manner similar to that described with respect to the protection circuits 171 and/or 172.

In some embodiments, during fabrication of IC device 100A, the electrical connections or interconnects of the PID protection circuit and substrate 110 and the corresponding doped well are completed at one or more metal layers below the Mk layer, i.e., before interconnect 163 is completed. Thus, in one or more embodiments, the charge accumulated in one or more of the N-well NW1, P-well PW1, N-well NW2, and P-well PW2 is discharged to the substrate 110 through the corresponding one or more PID protection circuits before the interconnect 163 is completed, thereby preventing an undesirably high voltage from being applied across one or more of the gate dielectrics 121, 131, and avoiding or at least mitigating PID problems.

In some embodiments, an operating voltage is applied across one or more PID protection circuits during operation of IC device 100A. For example, when N-well NW2 is electrically coupled to or biased by VDD and substrate 110 is electrically coupled to or biased by VSS, an operating voltage of VDD-VSS is applied between N-well NW2 and substrate 110 (i.e., across protection circuit 172). In some cases, this operating voltage is a high DC voltage, for example 36V. Other operating voltage values are within the scope of the various embodiments. In some embodiments, the presence of multiple PID protection devices 177, 178 in the protection circuit 172 enables the protection circuit 172 to maintain a high operating voltage without causing damage and/or reliability problems to the IC device 100A. This is an improvement over other approaches in that a single diode discharging the charge accumulated in the doped well may not be sufficient to maintain a high operating voltage (e.g., 36V) in operation.

In at least one embodiment, the PID protection circuitry does not affect the function and/or operation of the various functional circuits in the IC device 100A. In some embodiments, one or more further advantages may be realized, including, but not limited to, low chip area impact, no ESD problems, etc. PID protection circuits according to some embodiments are suitable for use in various designs having different voltage applications and/or for use in each technology node (or process node). PID protection circuits according to some embodiments enable all DC, ESD and PID requirements to be met.

Fig. 1B is a schematic circuit diagram of an IC device 100B according to some embodiments. In some embodiments, IC device 100B corresponds to IC device 100A. For simplicity, corresponding components of the IC devices 100A, 100B are denoted by the same reference numerals.

IC device 100B includes doped region NBL-A and doped region NBL-B. The doped region NBL-A includes an N-well NW1 and a P-well PW1. The doped region NBL-B includes an N-well NW2 and a P-well PW2.

IC device 100B also includes one or more semiconductor devices formed over doped region NBL-a that configure potential PID victims. In the example configuration in FIG. 1B, the potential PID victim includes an NMOS transistor 181 over the P-well PW1 and/or a PMOS transistor 182 over the N-well NW 1. In some embodiments, NMOS transistor 181 corresponds to transistor N1 and/or PMOS transistor 182 corresponds to transistor P1. The gates (not numbered) of NMOS transistor 181 and PMOS transistor 182 are electrically coupled together and electrically connected to electrical connector 183. In some embodiments, electrical connection 183 is a signal path and/or corresponds to interconnect 163. In some embodiments, the electrical connector 183 is electrically coupled to one, but not both, of the gate of the NMOS transistor 181 and the gate of the PMOS transistor 182. In fig. 1B, electrical connections that exist in some designs or circuits but are not in others are schematically shown with dots (dashed lines). For example, in one or more embodiments, the source/drain 180 of the NMOS transistor 181 is electrically coupled to the P-well PW1, or in one or more other embodiments is not electrically coupled to the P-well PW1.

IC device 100B also includes one or more semiconductor devices formed on doped region NBL-B that configure potential PID aggressors. In the example configuration in fig. 1B, a potential PID attacker includes one or more of diodes 184, 185, and/or one or more of MOS devices such as PMOS transistor 186 and NMOS transistor 187, and/or one or more of BJTs such as NPN BJT 188 and PNP BJT 190. In some embodiments, the PID aggressor includes any P-N junction electrically coupled to the gate of the PID victim. In the example configuration in fig. 1B, electrical connector 183 is electrically coupled to the base of PNP BJT 190. In further examples, electrical connection 183 is electrically coupled to one or more of a junction 191 between diodes 184, 185, a junction 192 between PMOS transistor 186 and NMOS transistor 187, and/or a junction 193 between NPN BJT 188 and PNP BJT 189. In some embodiments, PMOS transistor 186 corresponds to transistor P2 and/or NMOS transistor 187 corresponds to transistor N2.

IC device 100B also includes PID protection circuits 171-174 electrically coupled between substrate 110 and corresponding P-well PW1, N-well NW2, N-well NW 1, P-well PW 2. Each of the PID protection circuits 171-174 includes a pair of PID protection devices configured as a forward diode and a reverse diode, respectively, e.g., as described with respect to fig. 1A. In the example configuration in fig. 1B, the forward and reverse diodes (not numbered) of the PID protection circuits 173, 174 have corresponding cathodes electrically coupled together, similar to the diodes 175, 176 of the PID protection circuit 171. In some embodiments, similar to diodes 177, 178 of PID protection circuit 172, in at least one of PID protection circuits 173, 174, the forward and reverse diodes have corresponding anodes electrically coupled together. Other configurations are within the scope of the various embodiments. In at least one embodiment, one or more of the PID protection circuits 171-174 are omitted.

In the example configuration in FIG. 1B, each of the PID protection circuits 171-174 is shown as including a pair of diodes. This is just one example. In some embodiments, the PID protection circuit includes more than one forward diode and/or more than one reverse diode. For example, the PID protection circuit 179 includes a pair of forward diodes (e.g., 146, 147) and a pair of reverse diodes 148, 149 electrically coupled in series between the substrate 110 and the doped well. The PID protection circuit 179 is electrically coupled to the doped well at a first end corresponding to the anode 156 of the diode 146. For example, anode 156 is electrically coupled to a body contact in the doping well in a manner similar to that described with respect to body contact 125 or body contact 155 in fig. 1A. The PID protection circuit 179 is electrically coupled to the substrate 110 at a second end corresponding to the anode 158 of the diode 148. For example, anode 158 is electrically coupled to substrate 110 in a manner similar to that described with respect to anode 166 in fig. 1A. In the example configuration in FIG. 1B, the diodes 146-149 are coupled in a manner similar to the diodes 175, 176 in the PID protection circuit 171. Specifically, the cathode of diode 146 is electrically coupled to the anode of diode 147, the cathodes of diodes 147, 149 are electrically coupled together, and the anode of diode 149 is electrically coupled to the cathode of diode 148. In some embodiments, the cathodes and anodes of diodes 146-149 exchange positions resulting in a configuration similar to that described with respect to PID protection circuit 172. In some embodiments, PID protection circuit 179 or PID protection circuit with a plurality of forward diodes and/or a plurality of reverse diodes replaces one or more of PID protection circuits 171-174. In some embodiments, the number of forward diodes in a PID protection circuit is different from the number of reverse diodes of the same PID protection circuit.

In at least one embodiment, the PID protection circuit 179 or PID protection circuit with a plurality of forward diodes and/or a plurality of reverse diodes is configured to operate in a manner similar to the PID protection circuits 171-174, i.e., to discharge charge accumulated in the corresponding doped wells to the substrate during fabrication of the IC device 100B prior to formation of the electrical connections 183 or corresponding signal paths. The increased number of diodes in the PID protection circuit 179 compared to the PID protection circuits 171-174 improves the ability of the PID protection circuit 179 to maintain a high operating voltage in operation while having a corresponding increased resistance in the leakage current path for discharging charge from the doped well during fabrication. In at least one embodiment, the number and/or configuration of diodes in the PID protection circuit is a design consideration and is selected to ensure that the PID protection circuit provides the desired PID protection against antenna effects during manufacture while maintaining adequate robustness at the desired operating voltage in operation.

The IC device 100B also includes a local PID protection circuit 194 formed in the doped region NBL-a. The partial PID protection circuit 194 includes an NMOS transistor 195 and a PMOS transistor 196. In at least one embodiment, NMOS transistor 195 is formed over P-well PW1 and/or PMOS transistor 196 is formed over N-well NW1. The NMOS transistor 195 is electrically connected in a configuration sometimes referred to as a grounded-gate NMOS (ggNMOS) in which the gate, first source/drain, and body (bulk) of the NMOS transistor 195 are electrically coupled together and to the P-well PW1.PMOS transistor 196 is electrically connected in a configuration sometimes referred to as gate VDD PMOS (gdPMOS), wherein the gate, first source/drain, and body of PMOS transistor 196 are electrically coupled together and to N-well NW1. The second source/drain of NMOS transistor 195 and the second source/drain of PMOS transistor 196 are electrically coupled together to electrical connection 183 and the gates of NMOS transistor 181 and PMOS transistor 182 as potential PID victims.

During the fabrication of IC device 100B, NMOS transistor 195 and PMOS transistor 196 are electrically coupled to the gate of the potential PID victim prior to completion of electrical connector 183, and NMOS transistor 195/PMOS transistor 196/is configured to discharge the charge on electrical connector 183 when electrical connector 183 is completed to protect the gate dielectric of the potential PID victim from PID problems. In operation of IC device 100B, NMOS transistor 195 and PMOS transistor 196 are turned off and do not affect the function or operation of one or more functional circuits including potential PID victims to be protected. In some embodiments, one of NMOS transistor 195 and PMOS transistor 196 is omitted. In at least one embodiment, the local PID protection circuit 194 is omitted.

IC device 100B also includes a cross-well PID protection circuit 197. The cross-well PID protection circuit 197 includes a diode 198 and a diode 199 formed on the substrate 110. Diode 198 has an anode electrically coupled to P-well PW1 and a cathode electrically coupled to P-well PW 2. Diode 199 has an anode electrically coupled to P-well PW2 and a cathode electrically coupled to P-well PW 1. In some embodiments, diodes 198, 199 are electrically coupled to P-wells PW1, PW2 at corresponding body contacts, as described with respect to fig. 1A.

In the fabrication of IC device 100B, diodes 198, 199 are formed and electrically coupled to P-wells PW1, PW2 prior to completion of electrical connection 183, and at least one of diodes 198, 199 is configured to transfer charge between P-wells PW2, PW 1. As a result, high voltages due to the potential difference between the P-wells PW1, PW2 are unlikely to be applied across the gate dielectric of the potential PID victim above the doped region NBL-a. The diodes 198, 199 do not affect the function or operation of one or more functional circuits including the potential PID victim to be protected. In some embodiments, one of the diodes 198, 199 is omitted. In at least one embodiment, the cross-trap PID protection circuit 197 is omitted. In at least one embodiment, one or more of the advantages described herein may be realized by IC device 100B.

FIG. 2 includes schematic circuit diagrams of various PID protection devices 203-209 according to some embodiments. In some embodiments, any of the PID protection devices 203-209 corresponds to any of the PID protection circuits (e.g., PID protection circuits 171-174, 179) described herein.

The PID protection device 203 comprises a diode D3. In some embodiments, diode D3 is an N-type diode, i.e., a diode formed on or in a P-well or P-doped region. In some embodiments, diode D3 is a P-type diode, i.e., a diode formed on or in an N-well or N-doped region. The N-type diode is schematically represented in the figures by the reference "N" or "N diode". The P-type diode is schematically indicated in the drawings by the reference "P" or "P diode". The diode, which may be an N-type diode or a P-type diode, is schematically indicated by the reference "N/P" or "N/P diode" in the figures. Examples of N-type and P-type diodes are described with respect to fig. 3A-3E.

The PID protection device 204 comprises a diode connected NMOS transistor and is sometimes referred to herein as a diode connected NMOS204. The diode-connected NMOS204 has a gate GN, a source SN, and a drain DN. The gate GN is electrically coupled to the source SN and to the body of the diode-connected NMOS204. As a result, diode-connected NMOS204 configures diode D4, diode D4 having an anode corresponding to gate GN/source SN/body and a cathode corresponding to drain DN. An example of a diode-connected NMOS transistor is described with respect to fig. 4A.

The PID protection device 205 comprises a diode-connected PMOS transistor and is sometimes referred to herein as a diode-connected PMOS205. The diode-connected PMOS205 has a gate GP, a source SP, and a drain DP. The gate GP is electrically coupled to the source SP and to the body of the diode-connected PMOS205. As a result, the diode-connected PMOS205 configures a diode D5, the diode D5 having a cathode corresponding to the gate GP/source SP/body and an anode corresponding to the drain DP. An example of a diode-connected PMOS transistor is described with respect to fig. 4B.

The PID protection device 206 comprises a diode-connected NPN BJT and is sometimes referred to herein as a diode-connected NPN BJT 206. Diode-connected NPN BJT 206 includes base BN, collector CN, and emitter EN. The base BN is electrically coupled to the emitter EN. As a result, diode-connected NPN BJT 206 configures diode D6, diode D6 having an anode corresponding to base BN/emitter EN and a cathode corresponding to collector CN.

The PID protection device 207 comprises a diode-connected NPN BJT, sometimes referred to herein as a diode-connected NP BJT 207. Like diode-connected NPN BJT 206, diode-connected NP BJT 207 includes a base BN, a collector CN, and an emitter EN. The diode-connected NPN BJT 207 includes a different electrical connection than the diode-connected NPN BJT 206. Specifically, in diode-connected NPN BJT 207, base BN is electrically coupled to collector CN. Accordingly, diode-connected NP BJT 207 is configured with diode D7, which diode D7 has an anode corresponding to base BN/collector CN and a cathode corresponding to emitter EN. Examples of diode-connected NPN BJTs are described with respect to fig. 5A-5B.

The PID protection device 208 includes a diode-connected PNP BJT, and is sometimes referred to herein as a diode-connected PNP BJT 208. Diode-connected PNP BJT 208 includes base BP, collector CP, and emitter EP. The base BP is electrically coupled to the emitter EP. As a result, the diode-connected PNP BJT 208 configures a diode D8, which diode D8 has a cathode corresponding to the base BP/emitter EP and an anode corresponding to the collector CP.

The PID protection device 209 includes a diode-connected PNP BJT and is sometimes referred to herein as diode-connected PNP BJT 209. Like diode-connected PNP BJT 208, diode-connected PNP BJT 209 includes base BP, collector CP, and emitter EP. Diode-connected PNP BJT 209 includes a different electrical connection than diode-connected PNP BJT 208. Specifically, in diode-connected PNP BJT 209, base BP is electrically coupled to collector CP. As a result, the diode-connected PNP BJT 209 configures a diode D9, which diode D9 has a cathode corresponding to the base BP/collector CP and an anode corresponding to the emitter EP. Examples of diode-connected PNP BJTs are described with respect to fig. 6A-6B.

The described N-type diode, diode connected NMOS and diode connected NPN BJT are examples of N-type PID protection devices. The described P-type diode, diode-connected PMOS and diode-connected PNP BJT are examples of P-type PID protection devices. In at least one embodiment, one or more of the advantages described herein may be realized by and/or in an IC device that includes any one or more of the PID protection devices 203-209.

Fig. 3A is a schematic cross-sectional view of a PID protection device 300A according to some embodiments. In some embodiments, the PID protection device 300A corresponds to any PID protection device in any PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). In one or more embodiments, the PID protection device 300A is a P-type diode corresponding to the PID protection device 203. The PID protection device 300A is referred to herein as a P-type diode 300A.

P-type diode 300A is formed over substrate 310. In some embodiments, substrate 310 corresponds to substrate 110. In at least one embodiment, P-type diode 300A is formed over a doped region (e.g., a deep well as described with respect to fig. 1A). The P-type diode 300A includes an N-well 311, a P-doped region 315, an N-doped region 316, and conductive structures 317, 318.

In some embodiments, N-well 311 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG. 1A. In some embodiments, P-doped region 315 and N-doped region 316 correspond to or are similar to the P-doped region and N-doped region described with respect to fig. 1A. In some embodiments, P-type diode 300A further includes one or more STI regions (not shown).

The P-N structure between P-doped region 315 and N-well 311 is diode 319. The P-doped region 315 corresponds to the anode of the diode 319 and the N-well 311 corresponds to the cathode of the diode 319. In some embodiments, diode 319 corresponds to diode D3 as a P-type diode.

Conductive structure 317 is electrically coupled to P-doped region 315 to provide an electrical connection to the anode of diode 319. Conductive structure 318 is electrically coupled to N-doped region 316 to provide an electrical connection to the cathode of diode 319. In some embodiments, each or at least one of the conductive structures 317, 318 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all below the Mk layer. In some embodiments, each of the conductive structures 317, 318 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or the substrate 310.

Fig. 3B is a schematic cross-sectional view of a PID protection device 300B according to some embodiments. In some embodiments, the PID protection device 300B corresponds to any PID protection device in the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). In one or more embodiments, the PID protection device 300B is an N-type diode corresponding to the PID protection device 203. The PID protection device 300B is referred to herein as an N-type diode 300B.

N-type diode 300B is formed over substrate 310. In at least one embodiment, an N-type diode 300B is formed over a doped region (e.g., a deep well as described with respect to fig. 1A). The N-type diode 300B includes a P-well 321, an N-doped region 325, a P-doped region 326, and conductive structures 327, 328. In some embodiments, P-well 321 is omitted, and substrate 310 is a P-type substrate configured as the anode of N-type diode 300B.

In some embodiments, P-well 321 corresponds to or is similar to P-well PW1 or P-well PW2 described with respect to FIG. 1A. In some embodiments, N-doped region 325 and P-doped region 326 correspond to or are similar to the N-doped region and P-doped region described with respect to FIG. 1A. In some embodiments, N-type diode 300B also includes one or more STI regions (not shown).

The P-N structure between the N-doped region 325 and the P-well 321 (or between the N-doped region 325 and the P-type substrate in the case where the P-well 321 is omitted) is a diode 329. The N-doped region 325 corresponds to the cathode of the diode 329 and the P-well 321 (or P-type substrate in the case where the P-well 321 is omitted) corresponds to the anode of the diode 327. In some embodiments, diode 329 corresponds to diode D3.

Conductive structure 327 is electrically coupled to N-doped region 325 to provide an electrical connection to the cathode of diode 329. Conductive structure 328 is electrically coupled to P-doped region 326 to provide an electrical connection to the anode of diode 329. In some embodiments, each or at least one of the conductive structures 327, 328 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via all below the Mk layer. In some embodiments, each of the conductive structures 327, 328 is configured to be electrically coupled to an anode or cathode of another PID protection device, doped well, or substrate 310.

Fig. 3C is a schematic cross-sectional view of a PID protection device 300C according to some embodiments. The PID protection device 300C comprises two P-type diodes electrically coupled in series in a similar manner to the diodes 146, 147 or diodes 148, 149 described with respect to fig. 1B. For simplicity, the components of the PID protection device 300C having corresponding components in the N-type diode 300A are indicated by the same reference numbers or by increasing the reference numbers of the N-type diode 300A by 20.

The first P-type diode of the PID protection device 300C corresponds to the P-type diode 300A and comprises an N-well 311, a P-doped region 315, an N-doped region 316, a conductive structure 317 and a diode 319. The second P-type diode of the PID protection device 300C is similar to the P-type diode 300A and includes an N-well 331, a P-doped region 335, an N-doped region 336, a conductive structure 338 and a diode 339.PID protection device 300C further comprises a conductive structure 337, conductive structure 337 electrically coupling N-doped region 316 and P-doped region 335, i.e. electrically coupling the cathode of diode 319 to the anode of diode 339. In some embodiments, each or at least one of the conductive structures 337, 338 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all below the Mk layer. In some embodiments, each of the conductive structures 317, 338 is configured to be electrically coupled to an anode or cathode of another PID protection device, doped well or substrate 310.

Fig. 3D is a schematic cross-sectional view of a PID protection device 300D according to some embodiments. The PID protection device 300D comprises two N-type diodes electrically coupled in series in a similar manner to the diodes 146, 147 or diodes 148, 149 described with respect to fig. 1B. For simplicity, the components of the PID protection device 300D having corresponding components in the N-type diode 300B are indicated by the same reference numbers or by increasing the reference numbers of the N-type diode 300B by 20.

The first N-type diode of the PID protection device 300D corresponds to the N-type diode 300B and comprises a P-well 321, an N-doped region 325, a P-doped region 326, a conductive structure 327 and a diode 329. The second N-type diode of the PID protection device 300D is similar to the N-type diode 300B and includes a P-well 341, an N-doped region 345, a P-doped region 346, a conductive structure 348, and a diode 349. The PID protection device 300D further comprises a conductive structure 347 electrically coupling the P-doped region 326 and the N-doped region 345, i.e. electrically coupling the anode of the diode 329 to the cathode of the diode 349. In some embodiments, each or at least one of the conductive structures 347, 348 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all below the Mk layer. In some embodiments, each of the conductive structures 327, 348 is configured to be electrically coupled to an anode or cathode of another PID protection device, doped well, or substrate 310.

FIG. 3E is a schematic cross-sectional view of a PID protection circuit 300E according to some embodiments. In some embodiments, the PID protection circuit 300E corresponds to the PID protection circuit 703 described with respect to fig. 7A.

The PID protection circuit 300E includes a P-type diode 300A and an N-type diode 300B electrically coupled in a double reverse junction. In the example configuration in fig. 3E, the P-well 321 of the N-type diode 300B is omitted. The N-doped region 316 of the P-type diode 300A is electrically coupled to the N-doped region 325 of the N-type diode 300B by a conductive structure 357, thereby electrically coupling the cathodes of the diodes 319, 329 together. Conductive structure 317 is configured to be electrically coupled to a doped well from which charge is to be released, and conductive structure 328 corresponds to a substrate tap of substrate 310.

The PID protection circuit 300E is an example in which an interconnection between the substrate and the PID protection circuit is omitted, because the substrate 310 is a P-type substrate configured as an anode of the N-type diode 300B. During fabrication of an IC device including PID protection circuit 300E, charge accumulated in a doped well (not shown) electrically coupled to conductive structure 317 is discharged through diode 319, conductive structure 357, and diode 329 to substrate 310.

In operation of the IC device including the PID protection circuit 300E, the substrate 310 is biased with an operating voltage applied to the conductive structure 328. An operating voltage of the doped well is applied to the conductive structure 317. In the event that the operating voltage of substrate 310 is higher than the operating voltage of the doped well (at conductive structure 317), P-N junction 358 between substrate 310 and N-well 311 will be forward biased, as schematically indicated by arrow 359, and potentially induce undesirable current. In one or more embodiments, this is why the PID protection circuit 300E is used in a circuit design or application, where a lower operating voltage is applied to the substrate 310 and a higher operating voltage is applied to the doped well from which charge will be discharged during fabrication.

For similar reasons, in one or more embodiments, for an IC device, application, or circuit design having different operating voltages applied to a substrate and a doped well, a PID protection circuit to be electrically coupled between the substrate and the doped well is selected such that the PID protection circuit includes an N-type PID protection device on a lower operating voltage side (i.e., a device having or over a P-type region such as a P-type substrate or P-well), and a P-type PID protection device on a higher operating voltage side (i.e., a device having or over an N-type region such as an N-type substrate or N-well). For example, in one or more embodiments, when the substrate has a lower operating voltage than the doped well, an N-type PID protection device (e.g., an N-type diode, NMOS, or NPN BJT) is electrically coupled to the substrate having the lower operating voltage, and a P-type PID protection device (e.g., a P-type diode, PMOS, or PNP BJT) is electrically coupled to the doped well having the higher operating voltage. Various examples are described with respect to one or more of fig. 7A-7E.

Fig. 4A is a schematic cross-sectional view of a PID protection device 400A according to some embodiments. In some embodiments, the PID protection device 400A corresponds to any PID protection device in any PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 400A is a diode-connected NMOS transistor that corresponds to diode-connected NMOS204 in one or more embodiments. The PID protection device 400A is referred to herein as a diode-connected NMOS 400A.

A diode-connected NMOS400A is formed over a substrate 410. In some embodiments, substrate 410 corresponds to substrate 110. In at least one embodiment, diode-connected NMOS400A is formed over a doped region (e.g., a deep well as described with respect to fig. 1A). Diode connected NMOS400A includes P-well 411, STI regions 412, 413, 414 of dielectric material, P-doped region 415, N-doped regions 416-419, gate dielectric 421, gate 422, sidewall 423, lightly doped regions 424, 425, and conductive structures 435, 436, 438, 439.

In some embodiments, P-well 411 corresponds to or is similar to P-well PW1 or P-well PW2 described with respect to FIG. 1A. Gate dielectric 421 and gate 422 are similar to gate dielectric 121 and gate 122 described with respect to fig. 1A. Gate 422 corresponds to gate GN of diode-connected NMOS 204. The P-doped region 415 and the N-doped regions 416-419 correspond to or are similar to the P-doped region and the N-doped region described with respect to fig. 1A. The N-doped regions 417, 418 correspond to the source SN and drain DN of the diode connected NMOS 204. P-doped region 415 is a body contact in P-well 411, similar to body contacts 125, 145, and is sometimes referred to as a body tap. The N-doped regions 416, 419 are body contacts in the substrate 410 or DNW and are sometimes referred to as substrate taps or well taps. Conductive structures 435, 436, 438, 439 are located above P-doped region 415 and N-doped regions 416, 418, 419, respectively. In some embodiments, each or at least one of the conductive structures 435, 436, 438, 439 includes one or more of MD contact structures, VD vias, VG vias, conductive patterns, and vias all below the Mk layer.

Conductive structure 435 electrically couples the gate GN, source SN, and body tap of diode connected NMOS 400A together. As a result, diode-connected NMOS 400A configures diode 449 at the P-N junction between N-doped region 418 and P-well 411. N-doped region 418 corresponds to the cathode of diode 449 and P-well 411 corresponds to the anode of diode 449. In some embodiments, diode 449 corresponds to diode D4.

Conductive structure 435 is electrically coupled to P-doped region 415 to provide an electrical connection to the anode of diode 449. Conductive structure 438 is electrically coupled to N-doped region 418 to provide an electrical connection to the cathode of diode 449. In some embodiments, each of the conductive structures 435, 438 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or the substrate 410. For example, when the conductive structure 436 or 439 is a substrate tap of the substrate 410, the substrate tap is electrically coupled to the conductive structure 435 or 438, e.g., by a conductive pattern in a metal layer below the Mk layer.

Fig. 4B is a schematic cross-sectional view of a PID protection device 400B according to some embodiments. In some embodiments, the PID protection device 400B corresponds to any PID protection device in a PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 400B is a diode-connected PMOS transistor that corresponds to diode-connected PMOS205 in one or more embodiments. The PID protection device 400B is referred to herein as diode-connected PMOS 400B.

A diode-connected PMOS 400B is formed over a substrate 410. In at least one embodiment, diode-connected PMOS 400B is formed over a doped region (e.g., deep well described with respect to fig. 1A). Diode-connected PMOS 400B includes N-well 461, STI regions 462, 463, 464 of dielectric material, N-doped regions 465, P-doped regions 466-469, gate dielectric 471, gate 472, sidewall 473, lightly doped regions 474, 475, and conductive structures 485, 486, 488, 489.

In some embodiments, N-well 461 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG. 1A. Gate dielectric 471 and gate 472 are similar to gate dielectric 121 and gate 122 described with respect to fig. 1A. Gate 472 corresponds to gate GP of diode connected PMOS 205. N-doped regions 465 and P-doped regions 466-469 correspond to or are similar to the N-doped regions and P-doped regions described with respect to FIG. 1A. The P-doped regions 467, 468 correspond to the source SP and drain DP of the diode connected PMOS 205. The N-doped region 465 is a body contact in the N-well 461, similar to body contacts 135, 155, and is sometimes referred to as a body tap. The P-doped regions 466, 469 are body contacts in the substrate 410 or DNW and are sometimes referred to as substrate taps or well taps. Conductive structures 485, 486, 488, 489 are respectively located over N-doped region 465 and P-doped regions 466, 468, 469. In some embodiments, each or at least one of the conductive structures 485, 486, 488, 489 includes one or more of MD contact structures, VD vias, VG vias, conductive patterns, and vias all under the Mk layer.

Conductive structure 485 electrically couples together the gate GP, source SP and body tap of diode connected PMOS 400B. As a result, diode-connected PMOS 400B configures diode 499 at the P-N junction between P-doped region 468 and N-well 461. The P-doped region 468 corresponds to the anode of the diode 499 and the N-well 461 corresponds to the cathode of the diode 499. In some embodiments, diode 499 corresponds to diode D5.

Conductive structure 485 is electrically coupled to N-doped region 465 to provide an electrical connection to the cathode of diode 499. Conductive structure 488 is electrically coupled to P-doped region 468 to provide an electrical connection to the anode of diode 499. In some embodiments, each of the conductive structures 485, 488 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or the substrate 410. For example, when conductive structure 486 or 489 is a substrate tap of substrate 410, the substrate tap is electrically coupled to conductive structure 485 or 488, such as through a conductive pattern in a metal layer below the Mk layer.

Fig. 5A is a schematic cross-sectional view of a PID protection device 500A according to some embodiments. In some embodiments, the PID protection device 500A corresponds to any PID protection device in any PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 500A is a diode-connected NPN BJT that corresponds to diode-connected NP BJT 206 in one or more embodiments. The PID protection device 500A is referred to herein as a diode-connected NPN BJT 500A.

A diode-connected NPN BJT 500A is formed over substrate 510. In some embodiments, substrate 510 corresponds to substrate 110. In at least one embodiment, substrate 510 comprises an N-type substrate. In some embodiments, diode-connected NPN BJT 500A is formed over an N-type doped region (e.g., DNW described with respect to fig. 1A). The DNW or N-type substrate forms part of a diode-connected NPN BJT 500A. Diode-connected NPN BJT 500A further includes P-well 511, N-doped region 516, and conductive structures 517, 518.

In some embodiments, P-well 511 corresponds to or is similar to P-well PW1 or P-well PW2 described with respect to FIG. 1A. N-doped region 516 corresponds to or is similar to the N-doped region described with respect to fig. 1A. In at least one embodiment, diode-connected NPN BJT 500A further includes one or more body contacts, such as substrate taps and/or well taps, for electrically connecting conductive structure 517 to DNW or substrate 510, and for electrically connecting conductive structure 518 to P-well 511. In some embodiments, each or at least one of the conductive structures 517, 518 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all below the Mk layer.

DNW or substrate 510 corresponds to collector CN of diode-connected NPN BJT 206. P-well 511 corresponds to the base BN of diode-connected NPN BJT 206. N-doped region 516 corresponds to the emitter EN of diode-connected NPN BJT 206. Conductive structure 518 electrically couples base BN and emitter EN of diode-connected NPN BJT 500A together. As a result, diode-connected NPN BJT 500A configures diode 519 at the P-N junction between P-well 511 and DNW or substrate 510. The DNW or substrate 510 corresponds to the cathode of the diode 519 and the P-well 511 corresponds to the anode of the diode 519. In some embodiments, diode 519 corresponds to diode D6. Conductive structure 517 provides an electrical connection to the cathode of diode 519. The conductive structure 518 provides an electrical connection to the anode of the diode 519. In some embodiments, each of the conductive structures 517, 518 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or the substrate 510.

Fig. 5B is a schematic cross-sectional view of a PID protection device 500B according to some embodiments. In some embodiments, the PID protection device 500B corresponds to any PID protection device in a PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 500B is a diode-connected NPN BJT that corresponds to diode-connected NP BJT 207 in one or more embodiments. PID protection device 500B is referred to herein as diode-connected NPN BJT500B. For simplicity, components of diode-connected NPN BJT500B having corresponding components in diode-connected NPN BJT 500A are indicated by the same reference numbers or by increasing the reference number of diode-connected NPN BJT 500A by ten.

The diode-connected NP BJT500B includes a different electrical connection compared to the diode-connected NPN BJT 500A. Specifically, in diode-connected NPN BJT500B, conductive structure 527 electrically couples base BN and collector CN together. As a result, diode-connected NPN BJT500B configures diode 529 at the P-N junction between P-well 511 and N-doped region 516. N-doped region 516 corresponds to the cathode of diode 529 and P-well 511 corresponds to the anode of diode 523. In some embodiments, diode 529 corresponds to diode D7. Conductive structure 527 provides an electrical connection to the anode of diode 529. A conductive structure 528 over and in electrical contact with the N-doped region 516 provides an electrical connection to the cathode of the diode 529. In some embodiments, each or at least one of the conductive structures 527, 528 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all under the Mk layer. In some embodiments, each of the conductive structures 527, 528 is configured to be electrically coupled to the anode or cathode of another PID protection device, doped well, or substrate 510.

Fig. 6A is a schematic cross-sectional view of a PID protection device 600A according to some embodiments. In some embodiments, the PID protection device 600A corresponds to any PID protection device in any PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 600A is a diode-connected PNP BJT that corresponds to diode-connected PNP BJT 208 in one or more embodiments. The PID protection device 600A is referred to herein as a diode-connected PNP BJT 600A.

A diode-connected PNP BJT 600A is formed over a substrate 610. In some embodiments, substrate 610 corresponds to substrate 110. In at least one embodiment, substrate 610 comprises a P-type substrate. In some embodiments, diode-connected PNP BJT 600A is formed over a P-type doped region, such as a deep P-well (DPW). The DPW or P-type substrate forms part of a diode-connected PNP BJT 600A. Diode-connected PNP BJT 600A further includes N-well 611, P-doped region 616, and conductive structures 617, 618.

In some embodiments, N-well 611 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG. 1A. The P-doped region 616 corresponds to or is similar to the P-doped region described with respect to fig. 1A. In at least one embodiment, diode-connected PNP BJT 600A further includes one or more body contacts, such as substrate taps and/or well taps, for electrically connecting conductive structure 617 to DPW or substrate 610, and for electrically connecting conductive structure 618 to N-well 611. In some embodiments, each or at least one of the conductive structures 617, 618 includes one or more of MD contact structures, VD vias, conductive patterns, and vias all below the Mk layer.

DPW or substrate 610 corresponds to collector CP of diode-connected PNP BJT 208. N-well 611 corresponds to the base BP of diode-connected PNP BJT 208. The P-doped region 616 corresponds to the emitter EP of the diode-connected PNP BJT 208. Conductive structure 618 electrically couples the base BP and emitter EP of diode-connected PNP BJT 600A together. As a result, diode-connected PNP BJT 600A configures diode 619 at the P-N junction between N-well 611 and DPW or substrate 610. DPW or substrate 610 corresponds to the anode of diode 619 and N-well 611 corresponds to the cathode of diode 619. In some embodiments, diode 619 corresponds to diode D8. Conductive structure 617 provides an electrical connection to the anode of diode 619. Conductive structure 618 provides an electrical connection to the cathode of diode 619. In some embodiments, each of the conductive structures 617, 618 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or the substrate 610.

Fig. 6B is a schematic cross-sectional view of a PID protection device 600B according to some embodiments. In some embodiments, the PID protection device 600B corresponds to any PID protection device in a PID protection circuit described herein (e.g., PID protection circuits 171-174, 179). PID protection device 600B is a diode-connected PNP BJT that corresponds to diode-connected PNP BJT 209 in one or more embodiments. The PID protection device 600B is referred to herein as a diode-connected PNP BJT600B. For simplicity, components of diode-connected PNP BJT600B having corresponding components in diode-connected PNP BJT 600A are indicated by the same reference numbers or by incrementing the reference number of diode-connected PNP BJT 600A by ten.

The diode-connected PNP BJT600B includes different electrical connections than the diode-connected PNP BJT 600A. Specifically, in diode-connected PNP BJT600B, conductive structure 627 electrically couples base BP and collector CP together. As a result, diode-connected PNP BJT600B configures diode 629 at the P-N junction between N-well 611 and P-doped region 616. The P-doped region 616 corresponds to the anode of the diode 629 and the N-well 611 corresponds to the cathode of the transistor 629. In some embodiments, diode 629 corresponds to diode D9. Conductive structure 627 provides an electrical connection to the cathode of diode 629. A conductive structure 628 over the P-doped region 616 and in electrical contact with the P-doped region 616 provides an electrical connection to the anode of the diode 629. In some embodiments, each or at least one of the conductive structures 627, 628 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via all below the Mk layer. In some embodiments, each of the conductive structures 627, 628 is configured to be electrically coupled to an anode or cathode of another PID protection device, a doped well, or a substrate 610.

7A-7F include schematic circuit diagrams of PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 according to some embodiments.

In some embodiments, any of PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 corresponds to any of PID protection circuits 171-174. For simplicity, corresponding parts in fig. 7A to 7F are denoted by the same reference numerals as in fig. 2. Although in fig. 7A-7F, all PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are shown electrically coupled between the substrate 751 and the doped well 752 (e.g., an N-well or a P-well), this is for illustrative purposes. In some embodiments, not all PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are included in the same IC device. In some embodiments, any two of the PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are included in the same IC device and are electrically coupled to the same substrate of the IC device, but correspond to two different doped wells on the substrate. In some embodiments, any two of the PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are included in different IC devices and electrically coupled to different substrates and different doped wells. In some embodiments, the substrate 751 corresponds to one or more of the substrates 110, 310, 410, 510, 610, and the doped well 752 corresponds to one or more of the described N-well and/or P-well on the corresponding substrate. In at least one embodiment, one or more diodes in one or more of the PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 correspond to one or more of the PID protection device 203, the P-type diode 300A, and the N-type diode 300B. In at least one embodiment, one or more of the MOS transistors in one or more of the PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 corresponds to one or more of the PID protection devices 204, 205, the diode connected NMOS400A, and the diode connected PMOS 400B. In at least one embodiment, one or more BJTs in one or more of PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 correspond to one or more of PID protection devices 206-209, diode-connected NPN BJTs 500A, 500B, and diode-connected PNP BJTs 600A, 600B.

FIG. 7A includes schematic circuit diagrams of PID protection circuits 701-704 configured by diodes, according to some embodiments.

The PID protection circuit 701 includes two P-type diodes having cathodes electrically coupled together. The anode of one of the two P-type diodes is electrically coupled to a substrate 751. The anode of the other P-type diode is electrically coupled to a doped well 752.

The PID protection circuit 702 includes two N-type diodes having cathodes electrically coupled together. The anode of one of the two N-type diodes is electrically coupled to a substrate 751. The anode of the other N-type diode is electrically coupled to a doped well 752.

The PID protection circuit 703 includes an N-type diode electrically coupled to a substrate 751 and a P-type diode electrically coupled to a doped well 752. The N-type diode and the P-type diode have cathodes electrically coupled together. The anode of the N-type diode is electrically coupled to a substrate 751. The anode of the P-type diode is electrically coupled to a doped well 752.

The PID protection circuit 704 includes a P-type diode electrically coupled to the substrate 751 and an N-type diode electrically coupled to the doped well 752. The N-type diode and the P-type diode have cathodes electrically coupled together. The anode of the P-type diode is electrically coupled to a substrate 751. The anode of the N-type diode is electrically coupled to a doped well 752.

In the example configuration in FIG. 7A, the diodes in each of the PID protection circuits 701-704 are electrically coupled in a manner similar to that described with respect to the PID protection circuit 171. In some embodiments, the diodes in each of the PID protection circuits 701-704 are electrically coupled in a manner similar to that described with respect to the PID protection circuit 172.

The PID protection circuits 701-702 comprise the same type of diode (i.e., two P-type diodes or two N-type diodes) electrically coupled to the substrate 751 and the doped well 752, and are selected for inclusion in an IC device, application, or circuit design according to some embodiments without operating voltage constraints related to the operating voltages of the substrate 751 and the doped well 752 in operation. The PID protection circuits 703-704 comprise different types of diodes (i.e., one P-type diode and one N-type diode) electrically coupled to the substrate 751 and the doped well 752, and are selected for inclusion in an IC device, application, or circuit design having operating voltage constraints according to some embodiments. In some embodiments, the operating voltage of substrate 751 is the operating voltage of the region outside of doped well 752 and outside of the doped region containing doped well 752. For example, as described with respect to fig. 1A, the operating voltage of substrate 110 is the operating voltage of region 116 or region 118.

In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, the PID protection circuit 703 is selected because in the PID protection circuit, the P-type PID protection device (e.g., P-type diode) is on the higher voltage side (e.g., doped well 752) and the N-type PID protection device (e.g., N-type diode) is on the lower voltage side (e.g., substrate 751).

In at least one embodiment where the operating voltage of doped well 752 is lower than the operating voltage of substrate 751, PID protection circuit 704 is selected because in this PID protection circuit, a P-type PID protection device (e.g., P-type diode) is on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., N-type diode) is on the lower voltage side (e.g., doped well 752).

Fig. 7B includes a schematic circuit diagram of PID protection circuits 705-710 configured by MOS transistors, according to some embodiments.

The PID protection circuit 705 comprises two diode-connected PMOS205, which are electrically coupled in such a way that the respective diodes D5 electrically couple the anodes together. The cathode of one of the two diodes D5 is electrically coupled to the substrate 751. The cathode of the other diode D5 is electrically coupled to the doped well 752.

The PID protection circuit 706 includes two diode-connected NMOS204 that are electrically coupled in such a way that the respective diodes D4 electrically couple the cathodes together. The anode of one of the two diodes D4 is electrically coupled to the substrate 751. The anode of the other diode D4 is electrically coupled to the doped well 752.

PID protection circuit 707 includes diode-connected PMOS205 electrically coupled to doped well 752 and diode-connected NMOS204 electrically coupled to substrate 751. The diode-connected PMOS205 and the diode-connected NMOS204 are electrically coupled in such a way that the corresponding diodes D5 and D4 electrically couple the cathodes together. The anode of diode D5 is electrically coupled to doped well 752. The anode of diode D4 is electrically coupled to substrate 751.

The PID protection circuit 708 includes a diode-connected PMOS205 electrically coupled to the doped well 752 and a diode-connected NMOS204 electrically coupled to the substrate 751. The diode-connected PMOS205 and the diode-connected NMOS204 are electrically coupled in such a way that the corresponding diodes D5 and D4 electrically couple the anodes together. The cathode of diode D5 is electrically coupled to doped well 752. The cathode of diode D4 is electrically coupled to substrate 751.

The PID protection circuit 709 includes a diode connected PMOS205 electrically coupled to the substrate 751 and a diode connected NMOS204 electrically coupled to the doped well 752. The diode-connected PMOS205 and the diode-connected NMOS204 are electrically coupled in such a way that the corresponding diodes D5 and D4 electrically couple the cathodes together. The anode of diode D5 is electrically coupled to substrate 751. The anode of diode D4 is electrically coupled to doped well 752.

The PID protection circuit 710 includes a diode-connected PMOS205 electrically coupled to the substrate 751 and a diode-connected NMOS204 electrically coupled to the doped well 752. The diode-connected PMOS205 and the diode-connected NMOS204 are electrically coupled in such a way that the corresponding diodes D5 and D4 electrically couple the anodes together. The cathode of diode D5 is electrically coupled to substrate 751. The cathode of diode D4 is electrically coupled to doped well 752.

In at least one embodiment where there is no operating voltage constraint related to the operating voltage of the substrate 751 and the doping well 752 in operation, one of the PID protection circuits 705, 706 is selected because in these PID protection circuits both PID protection devices are of the same type, i.e. both PID protection devices are P-type devices (e.g. two PMOS) or both PID protection devices are N-type devices (e.g. two NMOS).

In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 707, 708 is selected, because in these PID protection circuits the P-type PID protection device (e.g. PMOS) is on the higher voltage side (e.g. doped well 752) and the N-type PID protection device (e.g. NMOS) is on the lower voltage side (e.g. substrate 751).

In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, one of the PID protection circuits 709, 710 is selected, because in these PID protection circuits the P-type PID protection device (e.g. PMOS) is on the higher voltage side (e.g. substrate 751) and the N-type PID protection device (e.g. NMOS) is on the lower voltage side (e.g. doped well 752).

Fig. 7C includes a schematic circuit diagram of PID protection circuits 711-716 configured by BJTs, according to some embodiments.

The PID protection circuit 711 includes a diode-connected NPN BJT 206 electrically coupled to the substrate 751 and a diode-connected NPN BJT 207 electrically coupled to the doped well 752. Diode-connected NPN BJT 206 and diode-connected NP BJT 207 are electrically coupled in such a way that the corresponding diodes D6 and D7 electrically couple the cathodes together. The anode of diode D6 is electrically coupled to substrate 751. The anode of diode D7 is electrically coupled to doped well 752.

PID protection circuit 712 includes diode-connected PNP BJT 209 electrically coupled to substrate 751 and diode-connected PNP BJT 208 electrically coupled to doped well 752. Diode-connected PNP BJT 208 and diode-connected PNP BJT 209 are electrically coupled in such a way that the corresponding diodes D8 and D9 electrically couple the anodes together. The cathode of diode D9 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752.

PID protection circuit 713 includes diode-connected NPN BJT 206 electrically coupled to substrate 751 and diode-connected PNP BJT 209 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected PNP BJT 209 are electrically coupled in such a way that the corresponding diodes D6 and D9 electrically couple the cathodes together. The anode of diode D6 is electrically coupled to substrate 751. The anode of diode D9 is electrically coupled to doped well 752.

PID protection circuit 714 includes diode-connected NPN BJT 207 electrically coupled to substrate 751 and diode-connected PNP BJT 208 electrically coupled to doped well 752. The diode-connected NPN BJT 207 and the diode-connected PNP BJT 208 are electrically coupled in such a way that the corresponding diodes D7 and D8 electrically couple the anodes together. The cathode of diode D7 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752.

PID protection circuit 715 includes diode-connected PNP BJT 209 electrically coupled to substrate 751 and diode-connected NPN BJT 206 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected PNP BJT 209 are electrically coupled in such a way that the corresponding diodes D6 and D9 electrically couple the cathodes together. The anode of diode D9 is electrically coupled to substrate 751. The anode of diode D6 is electrically coupled to doped well 752.

PID protection circuit 716 includes diode-connected PNP BJT 208 electrically coupled to substrate 751 and diode-connected NPN BJT 207 electrically coupled to doped well 752. The diode-connected NPN BJT 207 and the diode-connected PNP BJT 208 are electrically coupled in such a way that the corresponding diodes D7 and D8 electrically couple the anodes together. The cathode of diode D8 is electrically coupled to substrate 751. The cathode of diode D7 is electrically coupled to doped well 752.

In at least one embodiment where there is no operating voltage constraint related to the operating voltage of the substrate 751 and the doped well 752 in operation, one of the PID protection circuits 711, 712 is selected because in these PID protection circuits, both PID protection devices are of the same type, i.e. both PID protection devices are P-type devices (e.g. both PNP BJTs) or both PID protection devices are N-type devices (e.g. both NPN BJTs).

In at least one embodiment in which the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 713, 714 is selected because of these PID protection circuits the P-type PID protection device (e.g. PNP-BJT) is on the higher voltage side (e.g. doped well 752) and the N-type PID protection device (e.g. NPN BJT) is on the lower voltage side (e.g. substrate 751).

In at least one embodiment in which the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, one of the PID protection circuits 715, 716 is selected because of these PID protection circuits the P-type PID protection device (e.g. PNP-BJT) is on the higher voltage side (e.g. substrate 751) and the N-type PID protection device (e.g. NPN BJT) is on the lower voltage side (e.g. doped well 752).

Fig. 7D includes a schematic circuit diagram of PID protection circuits 717N-720N configured by N-type diodes and MOS transistors, in accordance with some embodiments.

PID protection circuit 717N includes an N-type diode electrically coupled to substrate 751 and a diode connected PMOS205 electrically coupled to doped well 752. The N-type diode of diode-connected PMOS205 and the corresponding N-type diode D5 have anodes electrically coupled together. The cathode of the N-type diode is electrically coupled to a substrate 751. The cathode of the N-type diode D5 is electrically coupled to the doped well 752.

The PID protection circuit 718N includes an N-type diode electrically coupled to the doped well 752 and a diode connected NMOS204 electrically coupled to the substrate 751. The N-type diode of diode connected NMOS204 and the corresponding N-type diode D4 have cathodes electrically coupled together. The anode of the N-type diode is electrically coupled to a doped well 752. The anode of the N-type diode D4 is electrically coupled to the substrate 751.

The PID protection circuit 719N includes an N-type diode electrically coupled to the doped well 752 and a diode-connected PMOS205 electrically coupled to the substrate 751. The N-type diode of diode-connected PMOS205 and the corresponding N-type diode D5 have anodes electrically coupled together. The cathode of the N-type diode is electrically coupled to a doped well 752. The cathode of the N-type diode D5 is electrically coupled to the substrate 751.

PID protection circuit 720N includes an N-type diode electrically coupled to substrate 751 and a diode-connected NMOS204 electrically coupled to doped well 752. The N-type diode of diode connected NMOS204 and the corresponding N-type diode D4 have cathodes electrically coupled together. The anode of the N-type diode is electrically coupled to a substrate 751. The anode of the N-type diode D4 is electrically coupled to the doped well 752.

Fig. 7D also includes a schematic circuit diagram of PID protection circuits 721N-724N configured by N-type diodes and BJTs, according to some embodiments.

The PID protection circuit 721N comprises an N-type diode electrically coupled to the doped well 752, and a diode connected NPN BJT 206 electrically coupled to the substrate 751. The N-type diode of diode-connected NPN BJT 206 and corresponding N-type diode D6 have cathodes electrically coupled together. The anode of the N-type diode is electrically coupled to a doped well 752. The anode of the N-type diode D6 is electrically coupled to the substrate 751.

PID protection circuit 722N includes an N-type diode electrically coupled to doped well 752, and a diode connected NPN BJT 207 electrically coupled to substrate 751. The N-type diode of diode-connected NPN BJT 207 and the corresponding N-type diode D7 have anodes electrically coupled together. The cathode of the N-type diode is electrically coupled to a doped well 752. The cathode of the N-type diode D7 is electrically coupled to the substrate 751.

PID protection circuit 723N includes an N-type diode electrically coupled to substrate 751, and a diode-connected PNP BJT 208 electrically coupled to doped well 752. The N-type diode of the diode-connected PNP BJT 208 and the corresponding N-type transistor D8 have anodes electrically coupled together. The cathode of the N-type diode is electrically coupled to a substrate 751. The cathode of the N-type diode D8 is electrically coupled to the doped well 752.

PID protection circuit 724N includes an N-type diode electrically coupled to substrate 751, and a diode-connected PNP BJT 209 electrically coupled to doped well 752. The N-type diode of the diode-connected PNP BJT 209 and the corresponding N-type transistor D9 have cathodes electrically coupled together. The anode of the N-type diode is electrically coupled to a substrate 751. The anode of the N-type diode D9 is electrically coupled to the doped well 752.

In at least one embodiment, where there is no operating voltage constraint related to the operating voltage of the substrate 751 and the doped well 752 in operation, one of the PID protection circuits 718N, 720N, 721N, 722N is selected, because in these PID protection circuits both PID protection devices are of the same type, i.e. both PID protection devices are N-type devices (e.g. N-type diode and NMOS, or N-type diode and NPN BJT).

In at least one embodiment in which the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 717N, 723N, 724N is selected because of these PID protection circuits, the P-type PID protection device (e.g., PMOS or PNP BJT) is on the higher voltage side (e.g., doped well 752) and the N-type PID protection device (e.g., N-type diode) is on the lower voltage side (e.g., substrate 751).

In at least one embodiment in which the operating voltage of doped well 752 is lower than the operating voltage of substrate 751, PID protection circuit 719N is selected because in this PID protection circuit, a P-type PID protection device (e.g., PMOS) is on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., N-type diode) is on the lower voltage side (e.g., doped well 752).

Fig. 7E includes schematic circuit diagrams of PID protection circuits 717P-720P configured by P-type diodes and MOS transistors, in accordance with some embodiments. Fig. 7E also includes a schematic circuit diagram of PID protection circuits 721P-724P configured by P-type diodes and BJTs, according to some embodiments.

The PID protection circuits 717P-724P correspond to the PID protection circuits 716N-724N, except that the N-type diodes in the PID protection circuits 710N-724N are replaced with P-type diodes in the PID protection circuits 715P-724P.

In at least one embodiment where there is no operating voltage constraint related to the operating voltage of the substrate 751 and the doped well 752 in operation, one of the PID protection circuits 717P, 719P, 723P, 724P is selected because in these PID protection circuits both PID protection devices are of the same type, i.e. both PID protection devices are P-type devices (e.g. P-type diode and PMOS, or P-type diode and PNP BJT).

In at least one embodiment in which the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 718P, 721P, 722P is selected, because of these PID protection circuits, the P-type PID protection device (e.g. P-type diode) is on the higher voltage side (e.g. doped well 752) and the N-type PID protection device (e.g. NMOS or NPN BJT) is on the lower voltage side (e.g. substrate 751).

In at least one embodiment in which the operating voltage of doped well 752 is lower than the operating voltage of substrate 751, PID protection circuit 720P is selected because in this PID protection circuit, the P-type PID protection device (e.g., P-type diode) is on the higher voltage side (e.g., substrate 751) and the N-type PID protection device (e.g., NMOS) is on the lower voltage side (e.g., doped well 752).

Fig. 7F includes a schematic circuit diagram of PID protection circuits 725-732 configured by BJTs and MOS transistors, according to some embodiments.

PID protection circuit 725 includes a diode-connected NPN BJT 207 electrically coupled to substrate 751, and a diode-connected PMOS205 electrically coupled to doped well 752. The diode-connected NPN BJT 207 and the diode-connected PMOS205 are electrically coupled in such a way that the corresponding diodes D7 and D5 electrically couple the anodes together. The cathode of diode D7 is electrically coupled to substrate 751. The cathode of diode D5 is electrically coupled to doped well 752.

PID protection circuit 726 includes diode-connected NPN BJT 206 electrically coupled to substrate 751, and diode-connected PMOS205 electrically coupled to doped well 752. The diode-connected NPN BJT 206 and the diode-connected PMOS205 are electrically coupled in such a way that the corresponding diodes D6 and D5 electrically couple the cathodes together. The anode of diode D6 is electrically coupled to substrate 751. The anode of diode D5 is electrically coupled to doped well 752.

PID protection circuit 727 includes diode-connected NMOS204 electrically coupled to substrate 751, and diode-connected PNP BJT 208 electrically coupled to doped well 752. The diode-connected NMOS204 and the diode-connected PNP BJT 208 are electrically coupled in such a way that the corresponding diodes D4 and D8 electrically couple the anodes together. The cathode of diode D4 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752.

PID protection circuit 728 includes diode-connected NMOS204 electrically coupled to substrate 751, and diode-connected PNP BJT 209 electrically coupled to doped well 752. Diode-connected NMOS204 and diode-connected PNP BJT 209 are electrically coupled in such a way that the corresponding diodes D4 and D9 electrically couple the cathodes together. The anode of diode D4 is electrically coupled to substrate 751. The anode of diode D9 is electrically coupled to doped well 752.

PID protection circuit 729 includes diode-connected PMOS205 electrically coupled to substrate 751, and diode-connected NPN BJT 207 electrically coupled to doped well 752. The diode-connected PMOS205 and the diode-connected NPN BJT 207 are electrically coupled in such a way that the corresponding diodes D5 and D7 electrically couple the anodes together. The cathode of diode D5 is electrically coupled to substrate 751. The cathode of diode D7 is electrically coupled to doped well 752.

PID protection circuit 730 includes diode-connected PMOS205 electrically coupled to substrate 751, and diode-connected NPN BJT 206 electrically coupled to doped well 752. The diode-connected PMOS205 and the diode-connected NPN BJT 206 are electrically coupled in such a way that the anodes of the corresponding diodes D5 and D6 are electrically coupled together. The anode of diode D5 is electrically coupled to substrate 751. The anode of diode D6 is electrically coupled to doped well 752.

PID protection circuit 731 includes diode-connected PNP BJT 208 electrically coupled to substrate 751, and diode-connected NMOS204 electrically coupled to doped well 752. The diode-connected NMOS204 and the diode-connected PNP BJT 208 are electrically coupled in such a way that the anodes of the corresponding diodes D4 and D8 are electrically coupled together. The cathode of diode D8 is electrically coupled to substrate 751. The cathode of diode D4 is electrically coupled to doped well 752.

PID protection circuit 732 includes diode-connected PNP BJT 209 electrically coupled to substrate 751, and diode-connected NMOS204 electrically coupled to doped well 752. The diode-connected PNP BJT 209 and diode-connected NMOS204 are electrically coupled in such a way that the corresponding diodes D9 and D4 electrically couple the cathodes together. The anode of diode D9 is electrically coupled to substrate 751. The anode of diode D4 is electrically coupled to doped well 752.

In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 725-728 is selected because of these PID protection circuits, the P-type PID protection device (e.g., PMOS or PNP-BJT) is on the higher voltage side (e.g., doped well 752) and the N-type PID protection device (e.g., NMOS or NPN BJT) is on the lower voltage side (e.g., substrate 751).

In at least one embodiment in which the operating voltage of doped well 752 is lower than the operating voltage of substrate 751, one of PID protection circuits 729-732 is selected, because of these PID protection circuits, a P-type PID protection device (e.g., PMOS or PNP-BJT) is on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., NMOS or NPN BJT) is on the lower voltage side (e.g., doped well 752).

In at least one embodiment, the PID protection provided by the PID protection device is related to the resistance of the PID protection device to leakage current, i.e. the PID protection device having a lower resistance to leakage current provides better PID protection than the PID protection device having a higher resistance to leakage current. In some embodiments, the BJT has less resistance to leakage current (i.e., better PID protection) than the diode, which in turn has less resistance to leakage current (i.e., better PID protection) than the MOS transistor. However, MOS transistors occupy less chip area than diodes, which in turn occupy less chip area than BJTs. In some embodiments, PID protection circuits 711-716 configured by BJTs provide better PID protection and occupy more chip area than PID protection circuits 701-704 configured by diodes, and PID protection circuits 701-704 configured by diodes provide better PID protection but occupy more chip area than PID protection circuits 705-710 configured by MOS transistors.

In at least one embodiment, a balance between the expected level of PID protection and the chip area occupied by the PID protection circuitry (i.e., the chip area not available for functional circuitry) needs to be considered in selecting one or more PID protection circuits for the IC device. For example, in an application or circuit design where strong PID protection is a more important design consideration than the chip area occupied by the PID protection circuits, one or more of the PID protection circuits 711-716 configured by the BJT are selected to be included in the IC device to be designed and/or manufactured. For another example, in an application or circuit design where minimizing the chip area occupied by the PID protection circuits is a more important design consideration, one or more of the PID protection circuits 705-710 configured by MOS transistors are selected to be included in the IC device. In another example, where PID protection and the chip area occupied by the PID protection circuitry are design considerations of about the same importance, one or more of the PID protection circuitry 701-704 configured by diodes is selected to be included in the IC device.

In some embodiments, another design consideration in selecting a particular PID protection circuit for an IC device includes an operating voltage constraint, or lack thereof. The operating voltage constraint is related to the operating voltage of the substrate and the doped well on the substrate, as described herein. For example, without operating voltage constraints, one or more of the PID protection circuits 701-702, 705-706, 711-712, 718N, 720N, 721N, 722N, 717P, 719P, 723P, 724P (sometimes referred to herein as a first set of PID protection circuits) are selected. For another example, when the operating voltage of the doped well is higher than the operating voltage of the substrate, one or more of the PID protection circuits 703, 707-708, 713-714, 717N, 723N, 724N, 718P, 721P, 722P, 725-728 (sometimes referred to herein as a second set of PID protection circuits) are selected for discharging the charge in the doped well to the substrate. In another example, where the operating voltage of the doped well is lower than the operating voltage of the substrate, one or more of the PID protection circuits 704, 709-710, 715-716, 719N, 720P, 729-732 (sometimes referred to herein as a third set of PID protection circuits) are selected for discharging the charge in the doped well to the substrate.

In some embodiments, further design considerations in selecting a particular PID protection circuit include minimizing the number of masks used in manufacturing. To this end, in one or more embodiments, one or more "hybrid solutions" are selected, i.e., each of the PID protection circuits 717N-724N, 717P-724P, 725-732 are configured with different types of PID protection devices. As described herein, PID protection devices and circuits according to some embodiments include many components similar to features of functional circuits, such as doped regions, doped wells, substrate taps, well taps, vias, interconnects, and the like. Thus, in one or more embodiments, the PID protection circuitry, as well as the functional circuitry of the IC device, may be fabricated by using the same mask or with a minimum number of added masks. In some embodiments, one or more of the "hybrid" PID protection circuits 717N-724N, 717P-724P, 725-732 are selected based on the type of semiconductor device in the chip area and/or the functional circuit layout in or around the chip area where the functional circuits of the PID protection circuits are to be formed, to minimize the number of masks added. Other considerations for determining which PID protection circuit configuration to use to discharge a particular doped well to a substrate are within the scope of the various embodiments.

The PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are examples of PID protection circuits that may be configured by various combinations of the PID protection devices 203-209. The PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 are not intended to constitute an exhaustive list of all PID protection circuits configurable by the PID protection devices 203-209. Other PID protection circuit configurations are within the scope of the various embodiments. For example, in one or more embodiments, more than two of the PID protection circuits each including the PID protection devices 203-209 are configurable, as described with respect to the PID protection circuit 179. In at least one embodiment, one or more of the advantages described herein may be realized by an IC device that includes one or more of the PID protection circuits.

Fig. 8A is a flow chart of a method 800A of manufacturing an IC device according to some embodiments. In some embodiments, the IC devices correspond to one or more of the IC devices described with respect to fig. 1A-1B, as well as any IC device including the PID protection device and/or PID protection circuit described with respect to fig. 2-7F. In some embodiments, method 800A is performed during a design phase. In at least one embodiment, method 800A is performed by a processor of a computer system. The computer system also includes a non-transitory computer-readable storage medium coupled to the processor and configured to store computer-executable instructions that, when executed by the processor, cause the processor to perform the method 800A. One example of such a computer system is an Electronic Design Automation (EDA) system.

At operation 805, it is determined whether there is an operating voltage constraint associated with the substrate and the doped well on the substrate. For example, as described with respect to fig. 7A-7F, it is determined whether there is an operating voltage constraint associated with the substrate 751 and the doped well 752 above the substrate. In some embodiments, the determination is made based on a circuit design of the IC device and/or a layout of the IC device.

At operation 810, responsive to a negative determination at operation 805 indicating that there is no operating voltage constraint associated with the substrate and the doped well (i.e., "no"), PID protection circuitry to be coupled between the doped well and the substrate is selected from a first set of PID protection circuitry. 7A-7F, in response to determining that there are no operating voltage constraints associated with the substrate 751 and the doped well 752, a PID protection circuit to be coupled between the substrate 751 and the doped well 752 is selected from a first set of protection circuits including PID protection circuits 701-702, 705-706, 711-712, 718N, 720N, 721N, 722N, 717P, 719P, 723P, 724P.

At operation 815, in response to a positive determination (i.e., "yes") indicating that there is an operating voltage constraint associated with the substrate and the doped well at operation 805, it is determined whether the operating voltage of the doped well is higher than the operating voltage of the substrate. For example, as described with respect to fig. 7A-7F, it is determined whether the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751.

At operation 820, responsive to a positive determination at operation 815 that the operating voltage of the doped well is higher than the operating voltage of the substrate (i.e., "yes"), a PID protection circuit to be coupled between the doped well and the substrate is selected from a second set of PID protection circuits different from the first set of PID protection circuits. 7A-7F, in response to determining that the operating voltage of doped well 752 is greater than the operating voltage of substrate 751, PIC protection circuitry to be coupled between substrate 751 and doped well 752 is selected from a second set of PID protection circuitry including PID protection circuitry 703, 707-708, 713-714, 717N, 723N, 724N, 718P, 721P, 722P, 725-728.

At operation 830, responsive to a negative determination (i.e., "no") indicating that the operating voltage of the doped well is not higher than the operating voltage of the substrate at operation 815, PID protection circuits to be coupled between the doped well and the substrate are selected from a third set of PID protection circuits, different from the first and second sets of PID protection circuits. For example, as described with respect to fig. 7A-7F, in response to determining that the operating voltage of doped well 752 is not higher than the operating voltage of substrate 751, PID protection circuits to be coupled between substrate 751 and doped well 752 are selected from a third set of PID protection circuits including PID protection circuits 704, 709-710, 715-716, 719N, 720P, 729-732.

In some embodiments, a PID protection circuit to be coupled between the substrate 751 and the doped well 752 is selected from one of the first through third sets based on one or more further considerations described herein. For example, such further considerations include, but are not limited to, the desired level of PID protection, the chip area occupied by the PID protection circuitry, the type and/or layout of adjacent semiconductor devices for mask minimization, and the like. In some embodiments, when the PID protection circuit is selected from one of the first through third groups, the process proceeds to a subsequent operation (e.g., for manufacturing an IC device).

Fig. 8B is a flow chart of a method 800B of manufacturing an IC device according to some embodiments. In some embodiments, method 800B may be used to fabricate one or more IC devices described with respect to fig. 1A-1B, as well as any IC device including the PID protection device and/or PID protection circuit described with respect to fig. 2-7F.

At operation 840, a dopant implant is performed to form a first doped well, a second doped well, a first P-N junction, and a second P-N junction on the substrate. In some embodiments, as described with respect to fig. 1A, the first doped well comprises either P-well PW1 or N-well NW1, and the second doped well comprises either P-well PW2 or N-well NW 2. In some embodiments, as described with respect to one or more of fig. 3A-6B, the first or second P-N junctions include any P-N junction configuring any of the diodes 319, 329, 339, 349, 449, 499, 519, 529, 619, 629. For example, a first P-N junction corresponds to one of the diodes 175, 176, and a second P-N junction corresponds to the other of the diodes 175, 176. For example, a first P-N junction corresponds to one of the diodes 177, 178, and a second P-N junction corresponds to the other of the diodes 177, 178.

At operation 845, a gate is deposited over the first doped well and patterned. In one example, as described with respect to fig. 1A, the gate includes gate 122 when the first doped well includes P-well PW1, or gate 132 when the first doped well includes N-well NW 1.

At operations 850, 855, a redistribution structure is fabricated by depositing and patterning various metal layers and via layers to form interconnects over a substrate. In one example, the redistribution structure 160 is fabricated over the substrate 110 as described with respect to fig. 1A.

At operation 850, fabrication of the redistribution structure forms one or more interconnects that electrically couple the first P-N junction and the second P-N junction in series and in a dual reverse junction configuration between the further region of the substrate and one of the first doped well and the second doped well. In one example, as described with respect to fig. 1A, the first and second P-N junctions include diodes 175, 176 electrically coupled in series between the further region 116 of the substrate 110 and the first doped well as P-well PW 1. The diodes 175, 176 are electrically coupled in a double reverse junction configuration in which the cathodes (e.g., N-type regions) of the diodes 175, 176 are coupled together. In another example, as described with respect to fig. 1A, the first and second P-N junctions include diodes 177, 178 electrically coupled in series between the further region 118 of the substrate 110 and the second doped well that is the N-well NW 2. The diodes 177, 178 are electrically coupled in a double reverse junction configuration, wherein the anodes (e.g., P-type regions) of the diodes 177, 178 are coupled together. In some embodiments, as a result of operation 850, charge accumulated in the first or second doped well is discharged to the substrate through the double reverse junction described, thereby avoiding or at least mitigating PID problems in subsequent fabrication operations.

Following operation 850, at operation 855, fabrication of the redistribution structure forms an interconnect that electrically couples the gate on the first doped well to the second doped well. In one example, as described with respect to fig. 1A, an interconnect 163 is formed to electrically couple gate 122 or gate 132 over a first doped well (i.e., P-well PW1 or N-well NW 1) to a second doped well (i.e., P-well PW2 or N-well NW 2). The interconnect 163 is formed in a higher Mk layer than the electrical connection or interconnect described with respect to operation 850. In other words, interconnect 163 is formed after the double reverse junction (e.g., PID protection circuit 171 or PID protection circuit 172) has been formed and is electrically coupled between substrate 110 and either the first doped well of the potential PID victim or the second doped well of the potential PID aggressor. Since the charge accumulated in the first or second doped well as described with respect to operation 850 has been discharged to the substrate, PID problems associated with the formation of interconnect 163 and/or subsequent interconnect are avoided or at least alleviated. In at least one embodiment, one or more additional advantages described herein may be realized by an IC device fabricated by one or more of methods 800A, 800B.

The methods described include example operations, but are not necessarily required to be performed in the order shown unless specifically described otherwise herein. Operations may be added, replaced, sequenced, and/or eliminated as appropriate in accordance with the spirit and scope of embodiments of the present disclosure. Embodiments combining different features and/or different embodiments are within the scope of the present disclosure and will be apparent to one of ordinary skill in the art after reviewing the present disclosure.

In some embodiments, an Integrated Circuit (IC) device includes a substrate, a first semiconductor device located in a first doped region in the substrate, and a second semiconductor device located in a second doped region in the substrate. The first doped region and the second doped region are different from each other. The gate of the first semiconductor device is electrically coupled to the source/drain of the second semiconductor device. The IC device further includes: a first protection device configured as one of a first forward diode and a first reverse diode; and a second protection device configured as the other of the first forward diode and the first reverse diode, the first forward diode and the first reverse diode being electrically coupled in series between the substrate and the doped well. Wherein the doped well is located in the first doped region and the source/drain of the first semiconductor device is located in the doped well, or the doped well is located in the second doped region and the source/drain of the second semiconductor device is located in the doped well.

In some embodiments, each of the first protection device and the second protection device comprises at least one of: p-type diodes, N-type diodes, diode-connected MOS transistors, or diode-connected bipolar junction transistors.

In some embodiments, the doped well is configured to receive a voltage higher than a voltage of the substrate, and there is one of: the first protection device comprises a P-type diode having an anode electrically coupled to the doped well and the second protection device comprises an N-type diode having an anode electrically coupled to the substrate, the first protection device comprises a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected NMOS transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected PNP bipolar junction transistor and the second protection device comprises a diode-connected NPN bipolar junction transistor.

In some embodiments, the doped well is configured to receive a voltage higher than a voltage of the substrate, and there is one of: the first protection device comprises a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device comprises a diode having a cathode electrically coupled to the substrate, the first protection device comprises a diode having an anode electrically coupled to the doped well and the second protection device comprises a diode-connected NMOS transistor electrically coupled to the substrate, the first protection device comprises a diode having a cathode electrically coupled to the doped well and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected NMOS transistor electrically coupled to the doped well and the second protection device comprises a diode having an anode electrically coupled to the substrate.

In some embodiments, the doped well is configured to receive a voltage higher than a voltage of the substrate, and there is one of: the first protection device comprises a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected PNP bipolar junction transistor electrically coupled to the doped well and the second protection device comprises a diode-connected NMOS transistor electrically coupled to the substrate.

In some embodiments, the doped well is configured to receive a voltage lower than a voltage of the substrate, and there is one of: the first protection device comprises an N-type diode having an anode electrically coupled to the doped well and the second protection device comprises a P-type diode having an anode electrically coupled to the substrate, the first protection device comprises a diode-connected NMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected NPN bipolar junction transistor and the second protection device comprises a diode-connected PNP bipolar junction transistor.

In some embodiments, the doped well is configured to receive a voltage lower than a voltage of the substrate, and there is one of: the first protection device comprises a diode electrically coupled to the doped well and the second protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected PNP bipolar junction transistor electrically coupled to the doped well and the second protection device comprises a diode electrically coupled to the substrate.

In some embodiments, the doped well is configured to receive a voltage lower than a voltage of the substrate, and there is one of: the first protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the doped well and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or the first protection device comprises a diode-connected NMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected PNP bipolar junction transistor electrically coupled to the substrate.

In some embodiments, the first protection device and the second protection device are both: a P-type diode, an N-type diode, a diode-connected NMOS transistor, a diode-connected PMOS transistor, a diode-connected NPN bipolar junction transistor, or a diode-connected PNP bipolar junction transistor.

In some embodiments, the doped well is a first doped well in a second doped region, the second doped region further comprising a second doped well having an opposite conductivity to the first doped well, the gate of the first semiconductor device electrically coupled to the second doped well, and the integrated circuit device further comprising: a second forward diode; and a second reverse diode, the second forward diode and the second reverse diode being electrically coupled in series between the substrate and the second doped well.

In some embodiments, the doped well is a first doped well located in a first doped region, the first doped region further comprising a second doped well having an opposite conductivity to the first doped well, and the integrated circuit device further comprises: a third semiconductor device having a gate electrically coupled to the gate of the first semiconductor device; a second forward diode; and a second reverse diode, the second forward diode and the second reverse diode being electrically coupled in series between the substrate and the second doped well.

In some embodiments, the second doped region further comprises a third doped well in which the source/drain of the second semiconductor device is located, and the integrated circuit device further comprises: a third forward diode; and a third forward diode and a third reverse diode electrically coupled in series between the substrate and the second doped well.

In some embodiments, the second doped region further comprises a fourth doped well having an opposite conductivity to the third doped well, the gate of the first semiconductor device and the gate of the third semiconductor device are electrically coupled to the fourth doped well, and the integrated circuit device further comprises: a fourth forward diode; and a fourth reverse diode, the fourth forward diode and the fourth reverse diode being electrically coupled in series between the substrate and the fourth doped well.

In some embodiments, one of the first doped well and the second doped well is a first P-well, one of the third doped well and the fourth doped well is a second P-well, and the integrated circuit device further comprises: a first diode having an anode electrically coupled to the first P-well and a cathode electrically coupled to the second P-well; and a second diode having an anode electrically coupled to the second P-well and a cathode electrically coupled to the first P-well.

In some embodiments, one of the first doped well and the second doped well is a P-well, the other of the first doped well and the second doped well is an N-well, and the integrated circuit device further comprises at least one of: a grounded-gate NMOS transistor electrically coupled between the P-well and the gate of the first semiconductor device and the gate of the third semiconductor device, or a gate-grounded VDDPMOS transistor electrically coupled between the N-well and the gate of the first semiconductor device and the gate of the third semiconductor device.

In some embodiments, an Integrated Circuit (IC) device includes a substrate, a first doped well over the substrate, a first diode over the substrate, a second diode over the substrate, a first electrical connection electrically coupling an anode or cathode of the first diode to the first doped well, and a second electrical connection electrically coupling an anode or cathode of the second diode to the substrate. The anode of the first diode and the anode of the second diode are electrically coupled to each other, or the anode of the first diode and the cathode of the second diode are electrically coupled to each other.

In some embodiments, the integrated circuit device further comprises: the second doped well is positioned above the substrate, is different from the first doped well grid and is positioned above the first doped well; and a third electrical connection electrically coupling the gate to the second doped well, wherein the first electrical connection and the second electrical connection are located below a highest metal layer comprising the conductive pattern of the third electrical connection.

In some embodiments, the integrated circuit device further comprises: a second doped well over the substrate, the second doped well being different from the first doped well; a gate electrode located over the second doped well; and a third electrical connection electrically coupling the gate to the first doped well, wherein the first electrical connection and the second electrical connection are located below a highest metal layer comprising the conductive pattern of the third electrical connection.

In some embodiments, one of the first diode and the second diode is a reverse diode configured to discharge charge from the first doped well to the substrate through a leakage current of the reverse diode, and the other of the first diode and the second diode is a forward diode configured to maintain an applied operating voltage across the first doped well and the substrate in operation of the integrated circuit device.

In a method of manufacturing an Integrated Circuit (IC) device according to some embodiments, the method includes: a dopant implantation is performed to form a first doped well, a second doped well, a first P-N junction, and a second P-N junction over the substrate. The substrate includes another region outside the first doped well and the second doped well. A gate is deposited and patterned over the first doped well. An interconnect is deposited and patterned over the substrate to electrically couple the first P-N junction and the second P-N junction in series between the other region of the substrate and one of the first doped well and the second doped well, wherein the P-type region of the first P-N junction and the P-type region of the second P-N junction are electrically coupled to each other, or the N-type region of the first P-N junction and the N-type region of the second P-N junction are electrically coupled to each other, and then electrically couple the gate over the first doped well to the second doped well.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising:

A substrate;

A first semiconductor device located in a first doped region in the substrate;

a second semiconductor device in a second doped region in the substrate, wherein

The first doped region and the second doped region are different from each other, and

The gate of the first semiconductor device is electrically coupled to the source/drain of the second semiconductor device;

a first protection device configured as one of a first forward diode and a first reverse diode; and

A second protection device configured as the other of the first forward diode and the first reverse diode, the first forward diode and the first reverse diode being electrically coupled in series between the substrate and the doped well, wherein

The doped well is located in the first doped region and the source/drain of the first semiconductor device is located in the doped well, or

The doped well is located in the second doped region, and source/drain electrodes of the second semiconductor device are located in the doped well.

2. The integrated circuit device of claim 1, wherein

Each of the first protection device and the second protection device includes at least one of:

a P-type diode, which is formed by a semiconductor device,

An N-type diode, which is formed by a semiconductor device,

Diode-connected MOS transistor, or

Diode-connected bipolar junction transistors.

3. The integrated circuit device of claim 1, wherein

The doped well is configured to receive a voltage higher than the voltage of the substrate, and

There is one of the following:

The first protection device comprises a P-type diode having an anode electrically coupled to the doped well, and the second protection device comprises an N-type diode having an anode electrically coupled to the substrate,

The first protection device comprises a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected NMOS transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected PNP bipolar junction transistor and the second protection device includes a diode-connected NPN bipolar junction transistor.

4. The integrated circuit device of claim 1, wherein

There is one of the following:

The first protection device includes a diode-connected PMOS transistor electrically coupled to the doped well, and the second protection device includes a diode having a cathode electrically coupled to the substrate,

The first protection device includes a diode having an anode electrically coupled to the doped well, and the second protection device includes a diode-connected NMOS transistor electrically coupled to the substrate,

The first protection device comprises a diode having a cathode electrically coupled to the doped well, and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected NMOS transistor electrically coupled to the doped well, and the second protection device includes a diode having an anode electrically coupled to the substrate.

5. The integrated circuit device of claim 1, wherein

There is one of the following:

the first protection device comprises a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the doped well, and the second protection device includes a diode-connected NMOS transistor electrically coupled to the substrate.

6. The integrated circuit device of claim 1, wherein

The doped well is configured to receive a voltage lower than the voltage of the substrate, and

There is one of the following:

The first protection device comprises an N-type diode having an anode electrically coupled to the doped well, and the second protection device comprises a P-type diode having an anode electrically coupled to the substrate,

The first protection device comprises a diode-connected NMOS transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected NPN bipolar junction transistor and the second protection device includes a diode-connected PNP bipolar junction transistor.

7. The integrated circuit device of claim 1, wherein

There is one of the following:

The first protection device comprises a diode electrically coupled to the doped well and the second protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the doped well, and the second protection device includes a diode electrically coupled to the substrate.

8. The integrated circuit device of claim 1, wherein

There is one of the following:

The first protection device comprises a diode-connected NPN bipolar junction transistor electrically coupled to the doped well, and the second protection device comprises a diode-connected PMOS transistor electrically coupled to the substrate, or

The first protection device includes a diode-connected NMOS transistor electrically coupled to the doped well, and the second protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the substrate.

9. An integrated circuit device, comprising:

A substrate;

A first doped well over the substrate;

A first diode located above the substrate;

a second diode located over the substrate;

A first electrical connection electrically coupling an anode or a cathode of the first diode to the first doped well; and

A second electrical connection electrically coupling an anode or a cathode of the second diode to the substrate, wherein

The anode of the first diode and the anode of the second diode are electrically coupled to each other, or

The anode of the first diode and the cathode of the second diode are electrically coupled to each other.

10. A method of manufacturing an integrated circuit device, the method comprising:

performing a dopant implantation to form a first doped well, a second doped well, a first P-N junction, and a second P-N junction over a substrate, wherein the substrate includes another region outside the first doped well and the second doped well;

Depositing a gate over the first doped well and patterning the gate; and

Depositing and patterning interconnects over the substrate to

The first P-N junction and the second P-N junction are electrically coupled in series between the other region of the substrate and one of the first doped well and the second doped well, wherein the P-type region of the first P-N junction and the P-type region of the second P-N junction are electrically coupled to each other or the N-type region of the first P-N junction and the N-type region of the second P-N junction are electrically coupled to each other, and then the gate over the first doped well is electrically coupled to the second doped well.