CN118016136A

CN118016136A - Memory test circuit

Info

Publication number: CN118016136A
Application number: CN202211393854.1A
Authority: CN
Inventors: 林盛霖; 林士傑
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-11-08
Filing date: 2022-11-08
Publication date: 2024-05-10

Abstract

The invention discloses a test circuit which is used for testing a memory. The input end of the memory is coupled with the register, and the test circuit transmits data to the memory through the register. The test circuit sequentially performs the following operations: writing first data into a target address of the memory, wherein all bits of the target address are of the same level, and all bits of the first data are of the same level; writing second data into the target address of the memory, wherein all bits of the second data are of the same level, and the second data are not equal to the first data; reading out output data from the target address; and, confirming whether the output data is correct.

Description

Memory test circuit

Technical Field

The present invention relates to memories, and more particularly to memory testing and test circuits.

Background

A chip with specific functions (e.g., system on a chip (SoC)) typically includes logic circuitry, functional registers (functional register), and memory. Functional registers refer to registers that the chip would use in normal operation (e.g., to perform the particular function). The tests performed on the chip before the chip leaves the factory generally include a scan test and a memory built-in self-test (MBIST), but neither test can test a fault (e.g., a Bridge Fault (BF), a transition delay fault (transition delay fault, TDF), a bridge slow-to-fault (BSF) fault, or a bridge fast-to-run (BSF) fault) on a path between the functional register and the memory. To test for such failures, the conventional approach is to use an Automatic TEST PATTERN Generation (ATPG) tool for generating test vectors using a random access memory sequence (random access memory) and then use the test vectors to read and write to and from the memory for multiple cycles through the scan chain. However, since the scan chain includes many logic circuits, the complexity of the operation of generating test vectors with multiple cycles on the ATPG is high, which affects the controllability of the ATPG on the memory, resulting in the problems of long time required for generating test vectors, multiple test vectors, low test coverage, and the like.

Disclosure of Invention

In view of the shortcomings of the prior art, it is an object of the present invention to provide a memory test circuit that overcomes the shortcomings of the prior art.

An embodiment of the invention provides a test circuit for testing a memory, an input end of the memory is coupled with a register, and the test circuit transmits data to the memory through the register. The test circuit sequentially performs the following operations: writing first data into a first address of the memory, wherein any two adjacent bits in the first address are of different levels, and any two adjacent bits in the first data are of different levels; writing second data in a second address of the memory, wherein any two adjacent bits in the second address are of different levels, and any two adjacent bits in the second data are of different levels; reading out first output data from the first address; reading out second output data from the second address; and confirming whether the first output data and the second output data are correct.

Another embodiment of the present invention provides a test circuit for testing a memory, an input terminal of the memory is coupled to a register, and the test circuit transmits data to the memory through the register. The test circuit sequentially performs the following operations: writing first data into a first address of the memory, wherein all bits of the first address are at a first level, and all bits of the first data are at the first level; writing second data into a second address of the memory, wherein all bits of the second address are at a second level, and all bits of the second data are at the second level, and the second level is not equal to the first level; reading out first output data from the first address; reading out second output data from the second address; and confirming whether the first output data and the second output data are correct.

Another embodiment of the present invention provides a test circuit for testing a memory, an input terminal of the memory is coupled to a register, and the test circuit transmits data to the memory through the register. The test circuit sequentially performs the following operations: writing first data into a target address of the memory, wherein all bits of the target address are of the same level, and all bits of the first data are of the same level; writing second data into the target address of the memory, wherein all bits of the second data are of the same level, and the second data are not equal to the first data; reading out output data from the target address; and, confirming whether the output data is correct.

The technical means embodied by the embodiment of the invention can improve at least one of the defects of the prior art, so that the invention can reduce the complexity of the test vector compared with the prior art and solve the problems of long time, more test vectors, low test coverage rate and the like required by the generation of the test vector in the prior art.

The features, embodiments and effects of the present invention will now be described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 shows the internal circuitry of a chip;

FIG. 2 is a functional block diagram of a memory test circuit according to an embodiment of the present invention;

FIG. 3 shows the flow and signal content of the static bridge fault test of the present invention;

FIG. 4 shows a test flow and signal content of the static bridge fault test of the present invention;

FIG. 5 shows the test flow and signal content of the down-transition delay fault test of the present invention;

FIG. 6 shows the test flow and signal content of the rising transition delay fault test of the present invention;

FIG. 7 shows the test flow and signal content of the falling transition delay fault test and the rising transition delay fault test of the present invention;

FIG. 8 shows the test flow and signal content of the up-transition delay fault test and the down-transition delay fault test of the present invention;

FIG. 9 is a diagram showing the test flow and signal content of the bridge descent delay fault test of the present invention;

FIG. 10 shows the test flow and signal content of the bridge rising delay fault test of the present invention;

FIG. 11 is a diagram showing the flow and signal content of the bridge-down delay fault test and the bridge-up delay fault test according to the present invention;

FIG. 12 is a schematic diagram showing the flow and signal content of the bridge-up delay fault test and the bridge-down delay fault test according to the present invention; and

Fig. 13 shows the internal circuitry of another chip.

Detailed Description

Technical terms used in the following description are terms commonly used in the art, and if a part of the terms are described or defined in the specification, the explanation of the part of the terms is based on the description or definition of the specification.

The present disclosure includes memory test circuits. Since some of the components included in the test circuit of the present invention may be known components alone, details of the known components will be omitted from the following description without affecting the full disclosure and operability of the device.

Fig. 1 shows the internal circuitry of a chip. Chip 100 includes registers 110, logic 120, multiplexer 130, registers 140, multiplexer 150, memory 160, registers 170, MBIST circuit 180, registers 190, and memory test circuit 105. Register 110, register 140, and register 170 are functional registers, while register 190 is an MBIST register. The memory test circuit 105 is coupled to the memory 160 through the multiplexer 130, the register 140 and the multiplexer 150. The input of register 110 and the output of register 170 may be coupled to other logic circuits or functional registers (not shown) in the chip. In this case, the register is implemented by a scan D flip-flop (SCAN D FLIP-flop), but not limited thereto.

In MBIST MODE, a control circuit (not shown) internal or external to chip 100 controls multiplexer 150 to select the output of MBIST circuit 180 with a MODE control signal bist_mode and to take the output of memory 160 through register 190.

In the normal operation MODE, the MODE control signal BIST_MODE controls the multiplexer 150 to select the register 140 instead of the MBIST circuit 180, and the MODE control signal MSM_MODE controls the multiplexer 130 to select the functional signal SF output by the logic circuit 120 instead of the test signal (including the write enable (Wright) signal WE, the memory address ADDR and the test data DI (or referred to as a test vector) output by the memory test circuit 105, as will be described in the following Fang Xiangshu. The memory test circuit 105 does not receive the functional signal SF, that is, the functional signal SF does not pass through the memory test circuit 105.

In the test MODE of the memory test circuit 105, the multiplexer 130 is controlled to select the test signal output by the memory test circuit 105 with the MODE control signal MSM_MODE, and the multiplexer 150 is controlled to select the output of the register 140 with the MODE control signal BIST_MODE.

Because of the presence of the register 140 between the memory test circuit 105 and the memory 160, the memory test circuit 105 can test static bridge faults (embodiment one), rising-to-rise delay faults (slow-to-fall delay faults) (embodiment two) and bridging falling delay faults/bridging rising delay faults (embodiment three) (embodiments one to three will be described below Fang Xiangshu). By comparison, because there is no register between memory 160 and existing MBIST circuit 180, existing MBIST circuit 180 cannot test for the faults described above.

FIG. 2 is a functional block diagram of a memory test circuit according to an embodiment of the invention. The memory test circuit 105 includes a memory circuit 210, a control circuit 220, and a comparison circuit 230. In the test mode, the control circuit 220 controls or operates the memory 160 with the memory address ADDR, the write enable signal WE, and the test data DI. When the write enable signal WE is at a first level (e.g., a high level or a logic 1), the memory 160 may be written with data; when the write enable signal WE is at a second level (e.g., a low level or a logic 0), the memory 160 cannot be written with data. The test data DI is data to be written into the memory 160, and the memory address ADDR is a target address of a write operation or a read operation.

When performing the test, the control circuit 220 reads the test data DI from the memory circuit 210 and writes the test data DI to the memory address ADDR of the memory 160. The output data DO is data read out from the memory 160. The comparison circuit 230 compares the output data DO with the test data to generate a test result RLT, which indicates whether the output data DO is correct (i.e., indicates whether the memory 160 passes the test). For example, when the output data DO is the same as the test data (i.e., the output data DO is correct), the memory 160 passes the test.

In the following discussion, the memory address ADDR includes m bits, and the test data DI and the output data DO each include n bits, where m and n are positive integers greater than or equal to 2, and m may be equal to or different from n. "X" represents "don't care".

Example one (static bridge failure test)

Fig. 3 shows the test flow and signal content (test vector) of the static bridge fault test according to the present invention, including the following operations. In some embodiments, periods T1-T5 may be consecutive 5 periods of the clock CLK.

Period T1 (write operation, write enable signal we=1): the memory test circuit 105 writes the test data DI (=10..10) to the memory address ADDR (=10..10) of the memory 160. More specifically, the memory address ADDR and the test data DI are both logic 1 and logic 0 alternately, the most significant bits are all logic 1, and the least significant bits are all logic 0.

Period T2 (write operation, write enable signal we=1): the memory test circuit 105 writes the test data DI (=01..01) to the memory address ADDR (=01..01) of the memory 160. More specifically, the memory address ADDR and the test data DI are both logic 0 and logic 1 alternately, the most significant bits are all logic 0, and the least significant bits are all logic 1.

Period T3 (read operation and compare operation, write enable signal we=0): the memory test circuit 105 reads out the output data DO1 from the memory address ADDR (=10..10) of the memory 160, that is, reads out the data of the memory address ADDR (=10..10) stored in the memory 160. Since the memory address ADDR (=10..10) is written with the test data DI (=10..10) at the time of the period T1, the ideal value of the output data DO1 is "10..10". The memory test circuit 105 (more specifically, the comparison circuit 230) then compares the output data DO1 with the test data DI to generate a test result RLT (first test result, which is temporarily stored in the memory circuit 210).

Period T4 (read operation and compare operation, write enable signal we=0): the memory test circuit 105 reads out the output data DO2 from the memory address ADDR (=01..01) of the memory 160, that is, reads out the data of the memory address ADDR (=01..01) stored in the memory 160. Since the memory address ADDR (=01..01) is written with the test data DI (=01..01) at the time of the period T2, an ideal value of the output data DO2 is "01..01". The memory test circuit 105 (more specifically, the comparison circuit 230) then compares the output data DO2 with the test data to generate a test result RLT (second test result) temporarily stored in the memory circuit 210.

Period T5 (result acquisition (capture) operation): the two test results are read out by a scan chain (SCAN CHAIN). The data transfer via the scan chain is well known to those skilled in the art and will not be described in detail. When the first test result and the second test result indicate that the output data DO1 and the output data DO2 are correct, respectively (i.e., the output data DO1 and the output data DO2 are equal to "10..10" and "01..01"), respectively, the memory 160 passes the test. It should be noted that, since the present embodiment is to test the static bridge fault, ADDR (=10..10) in the periods T1, T3 may be replaced with (=01..01), and ADDR (=01..01) in the periods T2, T4 may be replaced with (=10..10), so that the same test purpose may be achieved.

Referring to fig. 4, in other embodiments (also test static bridge failure), the memory test circuit 105 writes the test data DI (=01..01) at the memory address ADDR (=01..01) at the period T1, writes the test data DI (=10..10) at the memory address ADDR (=10..10) at the period T2, reads the output data DO1 from the memory address ADDR (=01..01) at the period T3 and makes a comparison (i.e., confirms whether the output data DO1 is equal to "01..01"), and reads the output data DO2 from the memory address ADDR (=10..10) at the period T4 and makes a comparison (i.e., confirms whether the output data DO2 is equal to "10..10"). It should be noted that, since the present embodiment is to test the static bridge fault, ADDR (=01..01) in the periods T1, T3 may be replaced with (=10..10), and ADDR (=10..10) in the periods T2, T4 may be replaced with (=01..01), so that the same test purpose may be achieved.

Embodiment two (falling transition delay fault test and rising transition delay fault test)

FIG. 5 shows the test flow and signal content of the down-transition delay fault test of the present invention, including the following operations. In some embodiments, periods T1-T5 may be consecutive 5 periods of the clock CLK.

Period T1 (write operation): the memory test circuit 105 writes the test data DI (=11..11) to the memory address ADDR (=11..11) of the memory 160. More specifically, all bits of the memory address ADDR and the test data DI are logic 1.

Period T2 (write operation): the memory test circuit 105 writes the test data DI (=00..00) to the memory address ADDR (=00..00) of the memory 160. More specifically, all bits of the memory address ADDR and the test data DI are logic 0.

Period T3 (read operation and compare operation): the memory test circuit 105 reads out the output data DO1 from the memory address ADDR (=11..11) of the memory 160, and compares the output data DO1 with the test data DI (=11..11) to generate a test result RLT (first test result, temporarily stored in the memory circuit 210).

Period T4 (read operation and compare operation): the memory test circuit 105 reads out the output data DO2 from the memory address ADDR (=00..00) of the memory 160, and compares the output data DO2 with the test data DI (=00..00) to generate a test result RLT (second test result, temporarily stored in the memory circuit 210).

Period T5 (result acquisition operation): the two test results are read out by the scan chain. When the first test result and the second test result indicate that the output data DO1 and the output data DO2 are correct, respectively (i.e., the output data DO1 and the output data DO2 are equal to "11..11" and "00..00"), respectively, the memory 160 passes the test.

Since each bit of the write enable signal WE, the memory address ADDR and the test data DI goes through a transition from logic 1 to logic 0, a falling transition delay fault between the memory 160 and the functional registers 140, 170 can be tested.

FIG. 6 shows the test flow and signal content of the rising transition delay fault test of the present invention. Fig. 6 is similar to fig. 5, and those skilled in the art can know the operation details of fig. 6 from the discussion about fig. 5, so that the detailed description is omitted. In the embodiment of FIG. 6, since each bit of the memory address ADDR and the test data DI goes through a transition of logic 0 to logic 1, a rising transition delay fault between the memory 160 and the functional registers 140, 170 can be tested.

FIG. 7 shows the test flow and signal content of the falling transition delay fault test and the rising transition delay fault test of the present invention. In some embodiments, periods T1-T9 may be 9 consecutive periods of the clock CLK. The period T1 to the period T4 of fig. 7 are the same as the period T1 to the period T4 of fig. 5, and the period T5 to the period T9 of fig. 7 are the same as the period T1 to the period T5 of fig. 6. In other words, in the embodiment of fig. 7, the memory test circuit 105 performs the falling state delay fault test (period T1 to period T4) on the memory 160, then performs the rising state delay fault test (period T5 to period T8), and finally obtains the test result in period T9. The ideal values of the output data DO3 (period T7) and the output data DO4 (period T8) of fig. 7 are the test data DI (=00..00) of the period T5 and the test data DI (=11..11) of the period T6, respectively.

FIG. 8 shows the test flow and signal content of the up-transition delay fault test and the down-transition delay fault test of the present invention. Fig. 8 is similar to fig. 7, in that in the embodiment of fig. 8, the memory test circuit 105 performs the rising transition delay fault test (period T1 to period T4), then performs the falling transition delay fault test (period T5 to period T8), and finally obtains the test result in period T9.

Compared to the embodiments of fig. 5 and 6, the embodiments of fig. 7 and 8 can also perform a rising transition delay fault test on the write enable signal WE (i.e., the write enable signal WE transitions from logic 0 to logic 1 in the period T4-T5).

The test of the second embodiment may also be used to test a stuck-at fault (stuck-at) on the path between register 140 and memory 160.

Embodiment III (bridge falling delay Fault test and bridge rising delay Fault test)

FIG. 9 shows the test flow and signal content of the bridge drop delay fault test of the present invention, including the following operations. In some embodiments, the period T1-period T4 may be 4 consecutive periods of the clock CLK.

Period T1 (write operation): the memory test circuit 105 writes the test data DI (=11..11) to the memory address ADDR (=00..00) of the memory 160. More specifically, all bits of the memory address ADDR are logic 0, and all bits of the test data DI are logic 1.

Period T3 (read operation and compare operation): this operation is similar to the period T3 or the period T4 of fig. 3, and thus will not be described again. The ideal value of the output data DO1 is the test data DI (=00..00) of the period T2.

Period T4 (result acquisition operation): this operation is similar to the period T5 of fig. 3, and will not be described again.

FIG. 10 shows the test flow and signal content of the bridge rising delay fault test of the present invention, including the following operations. In some embodiments, the period T1-period T4 may be 4 consecutive periods of the clock CLK.

Period T1 (write operation): the memory test circuit 105 writes the test data DI (=00..00) to the memory address ADDR (=00..00) of the memory 160. More specifically, all bits of the memory address ADDR and the test data DI are logic 0.

Period T2 (write operation): the memory test circuit 105 writes the test data DI (=11..11) to the memory address ADDR (=00..00) of the memory 160. More specifically, all bits of the memory address ADDR are logic 0, and all bits of the test data DI are logic 1.

Period T3 (read operation and compare operation): this operation is similar to the period T3 or the period T4 of fig. 3, and thus will not be described again. The ideal value of the output data DO1 is the test data DI (=11..11) of the period T2.

FIG. 11 shows the test flow and signal content of the bridge-down delay fault test and the bridge-up delay fault test of the present invention. In some embodiments, the period T1-period T7 may be 7 consecutive periods of the clock CLK. The period T1 to the period T3 of fig. 11 are the same as the period T1 to the period T3 of fig. 9, and the period T4 to the period T6 of fig. 11 are the same as the period T1 to the period T3 of fig. 10. In other words, in the embodiment of fig. 11, the memory test circuit 105 performs the bridge-down delay fault test (period T1 to period T3) on the memory 160, performs the bridge-up delay fault test (period T4 to period T6), and finally obtains the test result in period T7. The ideal values of the output data DO1 and the output data DO2 of fig. 11 are the test data DI (=00..00) of the period T2 and the test data DI (=11..11) of the period T5, respectively.

FIG. 12 shows the test flow and signal content of the bridge-up delay fault test and the bridge-down delay fault test of the present invention. Fig. 12 is similar to fig. 11, in that in the embodiment of fig. 12, the memory test circuit 105 first performs a bridge rising delay fault test (period T1 to period T3), then performs a bridge falling delay fault test (period T4 to period T6), and finally obtains a test result in period T9.

As can be seen from the above embodiments, since there is no complex logic circuit between the memory test circuit 105 and the memory 160, the present invention can test the static bridge fault, the falling transition delay fault, the rising transition delay fault, the bridge falling delay fault and the bridge rising delay fault between the memory 160 and the functional registers 140 and 170 by using simple test data (i.e., the test data DI of fig. 3 to 12), without considering the complex timing in the logic circuit 120. In other words, compared with the existing ATPG technology, the method greatly reduces the complexity of the memory test, and can solve the problems of long time, more test vectors, low test coverage rate and the like required by generating the test vectors in the prior art.

The storage circuit 210 may be a memory or a register. The control circuit 220 may be a finite state machine (FINITE STATE MACHINE, FSM) comprised of a plurality of logic circuits, which may be accomplished by one skilled in the art in light of the above discussion. The comparison circuit 230 is well known to those skilled in the art, and will not be described in detail.

Fig. 13 shows an internal circuit of another chip for illustrating another application scenario of the memory test circuit 105 of the present invention. Chip 1300 includes memory test circuit 105, register 110, logic circuit 120, multiplexer 130, register 140, multiplexer 150, memory 160, register 170, MBIST circuit 180, register 190, register 110a, logic circuit 120a, multiplexer 130a, register 140a, logic circuit 145, and register 170a. Registers 110a, 140a, and 170a are functional registers. In this embodiment, the memory test circuit 105 is further coupled to the memory 160 through the multiplexer 130a, the register 140a, the logic 145 and the multiplexer 150. That is, the memory test circuit 105 can test various faults between the register 140a and the memory 160 (when the MODE control signal msm_mode=1 and the output data DO is output through the register 170), and also can test various faults between the register 140a and the memory 160 (when the MODE control signal msm_mode=1 and the output data DO is output through the register 170 a). Therefore, different data paths in the chip can share the memory test circuit 105 to save the area and cost of the circuit.

The foregoing disclosed embodiments are not limiting of the invention, and those skilled in the art can suitably apply the present invention to test other types of faults in light of the present disclosure.

It should be noted that the shapes, sizes and proportions of the components in the foregoing disclosed figures are merely illustrative, and are used for the understanding of the present invention by those skilled in the art, and are not meant to limit the present invention.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and those skilled in the art can make various changes to the technical features of the present invention according to the explicit or implicit disclosure of the present invention, and all such changes may be made within the scope of the present invention, in other words, the scope of the present invention shall be subject to the claims of the present specification.

Reference numerals illustrate:

100,1300 chip

105 Memory test circuit

110,140,170,190,110A,140a,170a: registers

120,120A,145 logic circuits

130,150,130A multiplexer

160 Memory

MBIST circuit 180:

BIST_MODE, MSM_MODE MODE control signal

SF functional signal

210 Memory circuit

220 Control circuit

230 Comparator circuit

ADDR memory Address

DI test data

WE write Enable Signal

DO, DO1, DO2, DO3, DO4: output data

RLT test results

CLK frequency

T1, T2, T3, T4, T5, T6, T7, T8, T9: period

Claims

1. A test circuit for testing a memory, an input terminal of the memory being coupled to a register, and the test circuit transmitting data to the memory through the register, the test circuit sequentially performing the following operations:

(A) Writing first data into a first address of the memory, wherein any two adjacent bits in the first address are of different levels, and any two adjacent bits in the first data are of different levels;

(B) Writing second data in a second address of the memory, wherein any two adjacent bits in the second address are of different levels, and any two adjacent bits in the second data are of different levels;

(C) Reading out first output data from the first address;

(D) Reading out second output data from the second address; and

(E) Confirm whether the first output data and the second output data are correct.

2. The test circuit of claim 1, wherein the most significant bit of the first address is a logic 1 and the most significant bit of the first data is a logic 1.

3. The test circuit of claim 2, wherein the most significant bit of the second address is a logic 0 and the most significant bit of the second data is a logic 0.

4. A test circuit for testing a memory, an input terminal of the memory being coupled to a register, and the test circuit transmitting data to the memory through the register, the test circuit sequentially performing the following operations:

(A) Writing first data into a first address of the memory, wherein all bits of the first address are at a first level, and all bits of the first data are at the first level;

(B) Writing second data into a second address of the memory, wherein all bits of the second address are at a second level, and all bits of the second data are at the second level, and the second level is not equal to the first level;

(C) Reading out first output data from the first address;

(D) Reading out second output data from the second address; and

5. The test circuit of claim 4, wherein operation (B) further comprises controlling a write enable signal of the memory to be high, and operation (C) further comprises controlling the write enable signal of the memory to be low to test for a falling transition delay fault of the write enable signal.

6. The test circuit of claim 4, wherein the first level is high and the second level is low.

7. The test circuit of claim 4, wherein the first level is low and the second level is high.

8. A test circuit for testing a memory, an input terminal of the memory being coupled to a register, and the test circuit transmitting data to the memory through the register, the test circuit sequentially performing the following operations:

(A) Writing first data into a target address of the memory, wherein all bits of the target address are of the same level, and all bits of the first data are of the same level;

(B) Writing second data into the target address of the memory, wherein all bits of the second data are of the same level, and the second data are not equal to the first data;

(C) Reading out output data from the target address; and

(D) Confirm whether the output data is correct.

9. The test circuit of claim 8, wherein all bits of the target address are low, all bits of the first data are high, and all bits of the second data are low.

10. The test circuit of claim 8, wherein all bits of the target address are low, all bits of the first data are low, and all bits of the second data are high.