CN118013926A - Method for verifying design layout detection model function, verification model and test system - Google Patents

Abstract

The invention relates to the technical field of electronic design automation, in particular to a method for verifying the function of a design layout detection model, a verification model and a test system. The method comprises the following steps: providing a standard design layout and judging the layer number of the standard design layout; if the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result; if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result; and judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model. The method provided by the embodiment verifies the function of the detection model to obtain a detection model with higher accuracy.

Description

Method for verifying design layout detection model function, verification model and test system

[ Field of technology ]

The invention relates to the technical field of electronic design automation, in particular to a method for verifying the function of a design layout detection model, a verification model and a test system.

[ Background Art ]

Along with the gradual reduction of the size of the chip technology node, the manufacturing of the process equipment can be completed only under a certain pattern condition under the process size which is more and more limited, so that the design limit of the layout pattern is more and more severe. The design rule checking (Design Rule Check, DRC) process is becoming more and more stringent during chip design and fabrication. In order to detect out places which do not accord with rules in a design layout with higher efficiency and high quality, a designer usually detects patterns in the layout according to the set design rules so as to ensure that the patterns are prepared into actual circuits to work normally.

The working states of the chips in different scenes can be greatly different. When the accuracy of the detection model is verified in the prior art, each layer of the layout needs to be marked manually, and the marked position is detected. However, each time it is detected, the design pattern on a different area of the same layer, or on a different layer, is subject to a different scene at the time of testing. I.e. the scene tested is different for each region. That is, the existing detection model verification method cannot cover all scenes due to poor coverage, so that the final test processing result has inaccuracy. In addition, when the verification detection model detects the design layout, a test area needs to be manually selected, and a large amount of time is consumed in the process. Namely, when the accuracy of the existing detection model is verified, the method consumes time, and the accuracy of the method is still to be verified. Therefore, verification of the accuracy of the detection model is required to obtain a more accurate detection model.

[ Invention ]

To verify the accuracy of the detection model, a more accurate detection model is obtained. The invention provides a method for verifying the function of a design layout detection model, a verification model and a test system.

The invention provides the following technical scheme for solving the technical problems: a method for verifying the function of a detection model of a design layout is used for verifying the test accuracy of the detection model, and comprises the following steps:

Providing a standard design layout and judging the layer number of the standard design layout;

If the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result;

if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result;

And judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model.

Preferably, providing the standard design layout specifically includes:

Acquiring a plurality of sample design layouts, extracting design patterns in the sample design layouts, and classifying the extracted design patterns according to preset classification rules to obtain a plurality of different types of design patterns;

each kind of design pattern is set on a layout to obtain a standard design layout.

Preferably, the standard design layout has an area smaller than the area of the sample design layout.

Preferably, generating the first test case for the single-layer standard design layout includes:

the single-layer standard design layout comprises a polygon layer and a linear layer;

The single-layer standard design layout generates at least two first test cases based on a polygon layer, a linear layer, a preset checking mode, a preset measuring method and a preset output form.

Preferably, generating the second test case for the double-layer standard design layout includes:

The double-layer standard design layout comprises a polygon layer and a linear layer;

Combining the polygonal layer and the linear layer to obtain a combined layer;

the double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form.

Preferably, the first scene and the second scene are formed by combining a plurality of limiting conditions, and the limiting conditions included in the first scene and the second scene are different.

Preferably, determining the accuracy of the first test result or the second test result includes:

obtaining an expected detection result of the standard design layout in the first scene or the second scene;

acquiring an actual detection result, wherein the actual detection result comprises a first test result and/or a second test result;

judging whether the expected detection result is the same as the actual detection result;

if the test results are the same, the accuracy of the test results is qualified;

if the test results are different, the accuracy of the test results is not qualified.

Preferably, before determining the accuracy of the first test result or the second test result, the method further includes:

screening the first test result or the second test result based on a preset filtering option, and judging the accuracy of the screened test result so as to verify the test accuracy of the detection model.

The invention provides another technical scheme for solving the technical problems as follows: a verification model for verifying test accuracy of a detection model, the verification model comprising:

and (3) a design module: for obtaining a standard design layout;

And a judging module: the method is used for judging the layer number of the standard design layout;

the processing module is used for: the method comprises the steps of generating a first test case or a second test case;

and a testing module: the method comprises the steps of testing a first test case based on a first scene to obtain a first test result, or testing a second test case based on a second scene to obtain a second test result;

and (3) a verification module: the method is used for judging the accuracy of the first test result or the second test result so as to verify the test accuracy of the detection model.

The invention provides another technical scheme for solving the technical problems as follows: the test system comprises an input module, an output module and the verification model;

The input module is used for inputting the design layout into the verification model;

the verification model is used for testing the design graph in the design layout in the system;

and the output module is used for outputting the result tested by the verification model.

Compared with the prior art, the method for verifying the function of the design layout detection model, the verification model and the test system provided by the invention have the following beneficial effects:

1. The method for verifying the function of the detection model of the design layout, provided by the embodiment of the invention, is used for verifying the test accuracy of the detection model and comprises the following steps:

Providing a standard design layout and judging the layer number of the standard design layout;

If the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result;

if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result;

And judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model. The embodiment innovatively provides a standard design layout, and different test cases are generated selectively aiming at different layers of the standard design layout. And different test cases can be tested under different scenes so as to obtain different test results. And finally, verifying the test accuracy of the detection model based on the test result. By the verification method provided by the embodiment, the accuracy of the detection model can be rapidly verified, so that a detection model with higher accuracy can be obtained.

2. The embodiment of the invention provides a standard design layout, which specifically comprises the following steps:

Acquiring a plurality of sample design layouts, extracting design patterns in the sample design layouts, and classifying the extracted design patterns according to preset classification rules to obtain a plurality of different types of design patterns; each kind of design pattern is set on a layout to obtain a standard design layout. According to the embodiment, the standard design layout is provided, the internal graphs have a representative effect, the time consumed for verifying the accuracy of the detection model can be shortened, and the verification efficiency is improved.

3. The method for generating the first test case for the single-layer standard design layout comprises the following steps: the single-layer standard design layout comprises a polygon layer and a linear layer; the single-layer standard design layout generates at least two first test cases based on a polygon layer, a linear layer, a preset checking mode, a preset measuring method and a preset output form. In the embodiment, for the first test cases with a plurality of numbers, which can be generated by directly dealing with the single-layer design layout, the data volume of the test cases is large when verification is performed finally, and the verification accuracy is improved.

5. The generating the second test case for the double-layer standard design layout comprises the following steps: the double-layer standard design layout comprises a polygon layer and a linear layer; combining the polygonal layer and the linear layer to obtain a combined layer; the double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form. In the embodiment, for the second test cases with a plurality of numbers, which can be generated by directly dealing with the single-layer design layout, the data volume of the test cases is large when verification is performed finally, and the verification accuracy is improved.

6. The first scene and the second scene are formed by combining a plurality of limiting conditions, and the limiting conditions included in the first scene and the limiting conditions included in the second scene are different. Because the single-layer standard design layout and the double-layer standard design layout are different in the first test case and the second test case which are finally extracted, the first scene set for the first test case is different from the second scene set for the second test case. The embodiment is suitable for different test cases and different scenes, and improves the accuracy of verification results.

7. The embodiment of the invention judges the accuracy of the first test result or the second test result, which comprises the following steps:

obtaining an expected detection result of the standard design layout in the first scene or the second scene;

acquiring an actual detection result, wherein the actual detection result comprises a first test result and/or a second test result;

judging whether the expected detection result is the same as the actual detection result;

if the test results are the same, the accuracy of the test results is qualified;

if the test results are different, the accuracy of the test results is not qualified. By the method provided by the embodiment, the accuracy of the detection model can be verified. And further evaluate the accuracy of the detection model during the test.

8. The embodiment of the invention further comprises the following steps before judging the accuracy of the first test result or the second test result: screening the first test result or the second test result based on a preset filtering option, and judging the accuracy of the screened test result so as to verify the test accuracy of the detection model. The embodiment can selectively screen the test results based on the requirements of the designer and verify the test accuracy of the detection model based on the test results, and has high selectivity.

9. The embodiment of the invention also provides a verification model which has the same beneficial effects as the method for verifying the function of the design layout detection model, and the description is omitted herein.

10. The embodiment of the invention also provides a test system, which has the same beneficial effects as the verification model, and is not described herein.

[ Description of the drawings ]

Fig. 1 is a flowchart of a method for verifying a function of a design layout detection model according to a first embodiment of the present invention.

Fig. 2a is a schematic diagram of a first preset inspection mode according to a first embodiment of the present invention.

Fig. 2b is a schematic diagram of a second preset checking mode according to the first embodiment of the present invention.

Fig. 2c is a schematic diagram of a third preset inspection mode according to the first embodiment of the present invention.

Fig. 3 is a schematic diagram of a preset measurement method according to a first embodiment of the present invention.

Fig. 4a is a schematic diagram of a standard design layout structure according to a first embodiment of the present invention.

FIG. 4b is a schematic diagram of the FIG. 4a generated test case.

FIG. 4c is another schematic diagram of the FIG. 4a generated test case.

FIG. 4d is yet another schematic diagram of the FIG. 4a generated test case.

Fig. 5 is a schematic structural diagram of a verification model according to a second embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a test system according to a third embodiment of the present invention.

The attached drawings are used for identifying and describing:

1. verifying the model; 2. a test system;

11. designing a module; 12. a judging module; 13. a processing module; 14. a test module; 15. a verification module; 16. a management module; 21. an input module; 22. and an output module.

[ Detailed description ] of the invention

For the purpose of making the technical solution and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples of implementation. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, result or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, results, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments and that the acts and modules referred to are not necessarily required for the present invention.

In various embodiments of the present invention, it should be understood that the sequence numbers of the foregoing processes do not imply that the execution sequences of the processes should be determined by the functions and internal logic of the processes, and should not be construed as limiting the implementation of the embodiments of the present invention.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of detection models, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based detection models which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Along with the gradual reduction of the size of the chip technology node, the manufacturing of the process equipment can be completed only under a certain pattern condition under the process size which is more and more limited, so that the design limit of the layout pattern is more and more severe. The design rule checking (Design Rule Check, DRC) process is becoming more and more stringent during chip design and fabrication. In order to detect out non-conforming places in the design layout with higher efficiency and high quality,

The designer usually detects the patterns in the layout according to the set design rules so as to ensure that the patterns are prepared into actual circuits to work normally. While the design layout typically has many layers. While there are numerous design patterns on each layer, in order to test the design patterns on each layer, the prior art generally provides a test model, which may be a program or algorithm model, specifically referred to as EDGE LAYER. EDGE LAYER can be used as a detection model, the spatial geometric relations of patterns of different layers on the design layout are calculated according to the set design rules, the places which do not accord with the design rules are detected, and finally the detection result is output.

It should be appreciated that the pattern of each layer on the design layout will ultimately be used in practice as a circuit layout on a chip. Different circuits laid out inside the chip are required to meet the requirement of normal operation in different scenes. A scenario refers to some artificial design rules, i.e. constraints. If the tested design graph can work normally under the scene, the design graph is a qualified graph, namely, the normal work of the chip is not affected according to the constraint condition of the circuit laid out by the graph. Otherwise, the unqualified graph, namely the circuit laid out according to the graph, can influence the normal operation of the chip under the constraint condition. For example, the resistance and capacitance values of the on-chip circuitry are affected by various processes, voltages, and temperatures. And after the values of the resistor and the capacitor in the chip are affected, the time delay of the gate and the line in the internal circuit of the chip can be greatly affected. Different scenarios may be understood as different values of process, voltage or temperature.

However, the detection model has complex functions and high integration, and the internal implementation requires more attention. The designer needs to verify the function of the detection model to ensure that the algorithm model can output the accuracy of the detection result. However, even if it takes a lot of time to traverse the test results, the accuracy thereof cannot be ensured. Therefore, a new verification method needs to be sought to verify the function of the detection model. But it has the following problems: first, the working states of chips in different scenes may be greatly different. In the prior art, when verifying the accuracy of the detection model, each layer of the layout needs to be marked manually and the marked position is detected. However, each time it is detected, the design pattern on a different area of the same layer, or on a different layer, is subject to a different scene at the time of testing. I.e. the scene tested is different for each region. Even if a certain region is qualified as a result that can be detected in its corresponding scene, its detection result in another scene may be unqualified. That is, the existing detection model verification method cannot cover all scenes due to poor coverage, so that the final test processing result has inaccuracy. Secondly, when the verification detection model detects the design layout, the test area needs to be manually selected, and a large amount of time is consumed in the process. That is, the above problem table reveals that it takes time to verify the accuracy of the existing detection model, and the accuracy itself remains to be verified. It is important to find a method for verifying the accuracy of a detection model to obtain a detection model with higher accuracy.

In order to find a method, the accuracy of the detection model is verified. Referring to fig. 1, a first embodiment of the present invention provides a method for verifying a function of a detection model of a design layout, which is used for verifying a test accuracy of the detection model, and includes the following steps:

S1, providing a standard design layout, and judging the layer number of the standard design layout;

S2, if the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result;

s3, if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result;

S4, judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model.

It can be appreciated that when the existing detection model verification method verifies the detection model, a certain area of a certain layer needs to be marked, and then a test is performed on the marked position based on a certain scene. When the other area is marked and then tested, the other area is tested based on the other scene, namely the two test results always lack some test scenes. The verification method is insufficient in test on the basis of consuming a large amount of resources, the accuracy of an output result cannot be guaranteed, and the test process is scattered and not concentrated. In this embodiment, a standard design layout is provided first, specifically, a design layout to be actually detected by the detection model is referred to as a sample design layout. And the standard design layout comprises a plurality of standard design patterns. The standard design pattern may be a pattern extracted from a sample design layout or a pattern manually designed by a designer. That is, the standard design layout may be considered a scaled-down version of the design layout. The standard design layout is different from the sample design layout in that the number of layers of the sample design layout is large, and the standard design layout is at most two layers. Further, the number of layers of the standard design layout can be judged. And if the standard design layout is a single layer, generating a first test case for the single-layer standard design layout. The first test case can be understood as: the method comprises the steps of designing the relationship between the graph edges or the graph and the graph on the layout based on a single-layer standard, and accordingly extracting a plurality of first test cases, wherein the first test cases can be tested based on a first scene and a first test result is obtained. Optionally, if the standard design layout is a bilayer, generating a second test case for the bilayer standard design layout, where the second test case may be understood as: based on the relation between the graph edges or graphs on each layer of the double-layer standard design layout or the relation between the graph edges or graphs on different layers, a plurality of second test cases are extracted, and the second test cases can be tested based on a second scene and a second test result is obtained. It should be noted that, the relationship between graphics may refer to a conflicting relationship between graphics. Further, the accuracy of the test of the detection model can be verified by judging the accuracy of the first test result or the second test result.

It should be appreciated that the present embodiment innovatively provides a standard design layout, and different test cases are selectively generated for different layers of the standard design layout. And different test cases can be tested under different scenes so as to obtain different test results. And finally, verifying the test accuracy of the detection model based on the test result. The first scene or the second scene is a combination of various scenes. The number of layers of the standard design layout corresponding to the plurality of scenes is combined, and then the first scene or the second scene obtained after the combination is tested, so that the test execution time is saved on the basis of ensuring the test coverage rate. In addition, after the first test result and the second test result are obtained, the accuracy and the performance of the detection model function can be ensured to reach the standard by judging the accuracy of the first test result and the second test result, and the method is simple and convenient. By the verification method provided by the embodiment, the accuracy of the detection model can be rapidly verified, so that a detection model with higher accuracy can be obtained.

Further, in the step S1, providing the standard design layout specifically includes:

s11, acquiring a plurality of sample design layouts, extracting design patterns in the sample design layouts, and classifying the extracted design patterns according to preset classification rules to obtain a plurality of different types of design patterns;

s12, setting each kind of design graph on a layout to obtain a standard design layout.

It will be appreciated that the standard design pattern may be a pattern extracted from the sample design layout. Specifically, a plurality of sample design layouts are firstly obtained, wherein at least one layer in the sample design layout is provided, and a large number of figures are designed in each layer. Further, extracting design graphics in the sample design layout, and classifying the extracted design graphics according to a preset classification rule. It should be understood that the classification process is a process of classifying the same type of graphics into one type. For example, graphics may be classified based on their shape. For example, the triangle pattern is classified as one type, the trapezoid pattern is classified as one type, or the rectangle pattern is classified as one type. For another example, graphics may be classified based on their relationship. For example, the distance between the graph and the contour edge of the graph is classified as being smaller than a preset value, and the distance between the graph and the contour edge of the graph is classified as being within a preset range. Namely, the process of classifying the graphics based on the preset classification rule is a process of simplifying the graphics in the sample design layout. It should be appreciated that the patterns for each layer of the sample design layout are numerous. And includes a number of repeating patterns of the same type. After classifying the graphics based on a preset classification rule, a plurality of different types of design graphics can be obtained, and the different types of design graphics have a representative effect. Further, each kind of design pattern is set on a layout to obtain a standard design layout. Specifically, the area of the standard design layout is smaller than the area of the sample design layout. And if the sample design layout is adopted, verifying the accuracy of the detection model. Because of the complex structure in the sample design layout, a lot of time is required. The embodiment has the advantages that the standard design layout is provided, the internal graphs have a representative effect, the time consumed for verifying the accuracy of the detection model can be shortened, and the verification efficiency is improved.

The pattern is selected from a certain category or may be manually designed by a designer. It is understood that a designer can freely design graphics according to own requirements, so that the graphic styles in the standard design layout are wider.

Specifically, in the step S2, generating the first test case for the single-layer standard design layout includes:

the single-layer standard design layout comprises a polygon layer and a linear layer;

The single-layer standard design layout generates at least two first test cases based on a polygon layer, a linear layer, a preset checking mode, a preset measuring method and a preset output form.

Specifically, in the step S3, generating the second test case for the double-layer standard design layout includes:

The double-layer standard design layout comprises a polygon layer and a linear layer;

Combining the polygonal layer and the linear layer to obtain a combined layer;

the double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form.

It should be appreciated that a single-level standard design layout may include two types of layers. A polygonal layer and a linear layer, respectively. The polygonal figure layer mainly comprises a polygonal figure, and the outline appearance of the polygonal figure layer can be triangle, rectangle, pentagon and the like. The linear pattern layer mainly comprises a linear pattern, and the outline shape of the linear pattern layer can be linear. For a single-layer standard design layout, only one mode of the layers is adopted, namely a polygon layer and a linear layer. For a dual-layer standard design layout, the polygon layers and the linear layers may be combined to obtain a combined layer. The combined layers can be formed by four combination modes: including polygon and polygon layers, polygon and linear layers, linear and linear layers, and linear and polygon layers. Namely, due to the difference between the double-layer standard design layout and the single-layer standard design layout, the double-layer standard design layout is more complex in the combination mode of the layers. It should be noted that, whether it is a double-layer standard design layout or a single-layer standard design layout, the content is only a polygon layer and a linear layer. However, the combined layer in the double-layer standard design layout is different from the layer in the single-layer standard design layout in that the arrangement modes of the polygon layer and the linear layer are different.

Further, the preset inspection mode mainly includes three inspection modes, which include: internal inspection (internal), external inspection (external), and internal and external inspection (close). The relationship between the graphics exists on each layer of the double-layer standard design layout or the single-layer standard design layout. The graphic includes an inner contour and an outer contour, wherein the inner inspection refers to inspecting the inner contour of the graphic and its adjacent inner contour of the graphic. As shown in fig. 2a, the inside of the pattern 2P1 and the inside of the pattern 2P2 are inspected. Wherein the external inspection refers to the inspection of the outer contour of the graphic and its neighboring outer contours. As shown in fig. 2b, the outside of the graph 2P3 and the outside of the graph 2P4 are inspected, and the specific inspection position is referred to as an arrow pointing position, which will not be described in detail. Wherein the inner and outer inspection refers to inspecting the outer or inner contour of a graphic and the inner or outer contour of its neighboring graphic. As shown in fig. 2c, the outside of the pattern 2P5 and the inside of the pattern 2P6 are inspected.

Further, the predetermined measurement method may be a plurality of measurement methods, such as a ring measurement method. For example, referring to fig. 3 together, a ring of annular race track shaped inspection areas may be generated outside the outline of the pattern 3P 1. By judging whether the inspection area intersects with the adjacent pattern 3P2, the relationship between the pattern 3P1 and the pattern 3P2 based on the annular measuring method can be obtained. That is, the preset measurement method is based on the rules selected by the designer to obtain the relationship between the graph and the neighboring graph. For another example, the predetermined measurement method may be a rectangular measurement method. Specifically, the contour edges of the graphic may generate rectangular inspection areas outside the graphic, and the side-to-side conflicting relationship of the graphic and its neighboring graphics may be inspected by the rectangular inspection areas. It should be noted that the type of the preset measurement method is not limited. Further, there are typically six preset output forms. The preset output form mainly refers to a final output form of the test case, which can be output in a line segment form, can be output in an edge form, can be output in a form of forming a region between graphs, can be output in a form of a complete graph, and can be output in a form of a partial graph. In particular, please refer to fig. 4a and 4b. Wherein, fig. 4a is a standard design layout with patterns 4P1, 4P2 and 4P3 distributed therein. FIG. 4b is a schematic diagram of the test case generated in FIG. 4 a. The generated test case 4E1 is separately arranged on a layout, and is output in a form of forming a region between the patterns 4P1 and 4P 2. FIG. 4c is another schematic diagram of the test case generated in FIG. 4 a. The generated test case 4E2 is independently arranged on a layout, and is output in the form of a partial graph in the graph 4P 1. FIG. 4d is a schematic diagram of the test case generated in FIG. 4 a. The generated test case 4E3 is independently arranged on a layout, and is output in the form of a complete graph in the graph 4P3. It should be appreciated that the single-layer standard design layout may generate at least two first test cases based on the polygon layer and the linear layer, the preset inspection mode, the preset measurement method, and the preset output form. The double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form.

It should be appreciated that fig. 4b, 4c, and 4d illustrate only a simple example of generating a portion of a test case. In fact, according to the method provided by the present embodiment, the number of general test case outputs is numerous. For example, if the layout is a double-layer standard design layout calculated by 4 combined layers, 3 preset inspection modes, 4 preset measurement methods and 6 preset output forms, 1152 second test cases can be generated. That is, based on the method provided by the embodiment, a large number of test cases can be extracted from the standard layout, and the verification data volume of the test result is further enlarged. So that the verification result is more accurate.

The purpose is that different circuits laid out inside the chip are required to meet the normal operation of each circuit in different scenes. A scenario refers to some artificial design rules, i.e. constraints. Wherein the scene includes a first scene and a second scene. Specifically, the first scene and the second scene are formed by combining a plurality of limiting conditions. It should be understood that, because the single-layer standard design layout and the double-layer standard design layout are different from each other, the first test case and the second test case which are finally extracted from the single-layer standard design layout are different from each other, so that the first scene set for the first test case is different from the second scene set for the second test case. I.e. the first scene and the second scene are not subject to the same constraints. The qualification refers to some conditions that the designer sets according to the performance ultimately desired to be achieved by the chip. Such as: the circuit on the chip satisfies that the current is less than a. In addition, unlike the prior art, the prior art has different scenes within each layer of layout, one region and another region. Further, when the whole layout is tested, all scenes cannot be covered, so that the final test processing result is inaccurate. In this embodiment, the first scenario is a set of scenarios set for the first test case. Specifically, the method comprises the step of collecting all possible scenes when the graphics in the single-layer standard design layout are applied to the actual chip and can work normally. Similarly, the second scene is a scene set for the second test case. Since it is directed to a double-layer standard design layout, i.e. there is also a correlation between layers, the second scene differs from the definition conditions comprised in the first scene.

Further, in the step S4, determining the accuracy of the first test result or the second test result includes:

s41, obtaining an expected detection result of the standard design layout in the first scene or the second scene;

S42, acquiring an actual detection result, wherein the actual detection result comprises a first test result and/or a second test result;

s43, judging whether the expected detection result is the same as the actual detection result;

S44, if the test results are the same, the accuracy of the test results is qualified;

s45, if the test results are different, the accuracy of the test results is not qualified.

It will be appreciated that the test cases as in fig. 4b, 4c and 4d have been obtained. And aiming at the first test case or the second test case, the first test case or the second test case corresponds to different first scenes and second scenes. Specifically, the first scene and the second scene are designed by a designer, that is, the designer knows that under the conventional condition when designing, the graphics on the layout are designed on the chip, and whether the normal operation of the chip is affected under the corresponding scenes is not affected. For example, if a certain scenario designed by the designer is to satisfy that the current when the chip is operating is less than a. If the current of the test result is greater than A during the test, the test accuracy is poor, that is, the test model cannot output a relatively accurate test result when testing the design layout.

Specifically, in this embodiment, the expected detection result of the standard design layout in the first scene or the second scene is obtained. The expected detection result shows the behavior that the test case should show in the corresponding scene, for example, if the manufacturing rule is violated here, the test case and the detection result are places where the violation of the rule can be detected and output; if the manufacturing rules are not violated here, no output should be made. If the test result is not influenced, the expected test result is the same as the corresponding first test result and/or second test result, and the accuracy of the test result is qualified. The accuracy of the detection model in testing the design layout is good. If the influence is over, the expected detection result is different from the corresponding first test result and/or second test, and the accuracy of the test result is unqualified. The accuracy of the detection model in testing the design layout is poor. It should be understood that by the method provided in this embodiment, the accuracy of the detection model can be verified. And further evaluate the accuracy of the detection model during the test. In addition, if the accuracy of the detection model for testing the design layout is poor, a designer can also correct the detection model to obtain a model with good testing accuracy.

Further, before judging the accuracy of the first test result or the second test result, the method further comprises: screening the first test result or the second test result based on a preset filtering option, and judging the accuracy of the screened test result so as to verify the test accuracy of the detection model.

It will be appreciated that when the first test result or the second test result is obtained, it is possible that some of the test results are not desired by the designer, and thus filtering options may be added to the test results and further screened. Further, the accuracy of the screened test result is further checked to verify the test accuracy of the detection model. It should be understood that, the present embodiment can selectively screen the test results based on the requirements of the designer, and verify the test accuracy of the test model based on the test results, so that the selectivity is high.

In order to solve the above-mentioned technical problem, referring to fig. 5, a verification model 1 is further provided in a second embodiment of the present invention, for verifying the test accuracy of the detection model, where the verification model 1 includes:

design module 11: for obtaining a standard design layout;

the judgment module 12: the method is used for judging the layer number of the standard design layout;

The processing module 13: the method comprises the steps of generating a first test case or a second test case;

Test module 14: the method comprises the steps of testing a first test case based on a first scene to obtain a first test result, or testing a second test case based on a second scene to obtain a second test result;

the verification module 15: for judging the accuracy of the first test result or the second test result to verify the test accuracy of the verification model 1.

Further, the verification model 1 further includes a management module 16, and when the first test case or the second test case is obtained, the test case may be added to the management module 16 to be managed as a regression test case. In addition, the designer may write a preset script to automatically obtain a test case library and the latest tested object, run the test case in the verification model 1 to monitor the stability of the verification model 1, and specifically, may also obtain information of the verification model 1 in checking the running time, the behavior output, the log printing line number, and the like. And automatically comparing the daily results with the previous standard to automatically generate a test report. The test report allows the user to more easily understand the operation state of the verification model 1. It will be appreciated that if there are different places compared to the reference, it is also possible to choose to manually check whether these different places are newly added functions or improvements or introduced defects.

Further, referring to fig. 6, a test system 2 is further provided according to a second embodiment of the present invention, which includes an input module 21, an output module 22, and the verification model 1 described above; wherein:

The input module 21 is used for inputting the design layout into the verification model 1;

the verification model 1 is used for testing the design graph in the design layout in the system;

The output module 22 is configured to output a result tested by the verification model 1.

The embodiment of the present invention further provides a test system 2, which has the same beneficial effects as the verification model 1 described above, and will not be described herein.

Compared with the prior art, the method for verifying the function of the design layout detection model, the verification model and the test system provided by the invention have the following beneficial effects:

1. The method for verifying the function of the detection model of the design layout, provided by the embodiment of the invention, is used for verifying the test accuracy of the detection model and comprises the following steps:

Providing a standard design layout and judging the layer number of the standard design layout;

If the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result;

if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result;

And judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model. The embodiment innovatively provides a standard design layout, and different test cases are generated selectively aiming at different layers of the standard design layout. And different test cases can be tested under different scenes so as to obtain different test results. And finally, verifying the test accuracy of the detection model based on the test result. By the verification method provided by the embodiment, the accuracy of the detection model can be rapidly verified, so that a detection model with higher accuracy can be obtained.

2. The embodiment of the invention provides a standard design layout, which specifically comprises the following steps:

Acquiring a plurality of sample design layouts, extracting design patterns in the sample design layouts, and classifying the extracted design patterns according to preset classification rules to obtain a plurality of different types of design patterns; each kind of design pattern is set on a layout to obtain a standard design layout. According to the embodiment, the standard design layout is provided, the internal graphs have a representative effect, the time consumed for verifying the accuracy of the detection model can be shortened, and the verification efficiency is improved.

3. The method for generating the first test case for the single-layer standard design layout comprises the following steps: the single-layer standard design layout comprises a polygon layer and a linear layer; the single-layer standard design layout generates at least two first test cases based on a polygon layer, a linear layer, a preset checking mode, a preset measuring method and a preset output form. In the embodiment, for the first test cases with a plurality of numbers, which can be generated by directly dealing with the single-layer design layout, the data volume of the test cases is large when verification is performed finally, and the verification accuracy is improved.

5. The generating the second test case for the double-layer standard design layout comprises the following steps: the double-layer standard design layout comprises a polygon layer and a linear layer; combining the polygonal layer and the linear layer to obtain a combined layer; the double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form. In the embodiment, for the second test cases with a plurality of numbers, which can be generated by directly dealing with the single-layer design layout, the data volume of the test cases is large when verification is performed finally, and the verification accuracy is improved.

6. The first scene and the second scene are formed by combining a plurality of limiting conditions, and the limiting conditions included in the first scene and the limiting conditions included in the second scene are different. Because the single-layer standard design layout and the double-layer standard design layout are different in the first test case and the second test case which are finally extracted, the first scene set for the first test case is different from the second scene set for the second test case. The embodiment is suitable for different test cases and different scenes, and improves the accuracy of verification results.

7. The embodiment of the invention judges the accuracy of the first test result or the second test result, which comprises the following steps:

obtaining an expected detection result of the standard design layout in the first scene or the second scene;

acquiring an actual detection result, wherein the actual detection result comprises a first test result and/or a second test result;

judging whether the expected detection result is the same as the actual detection result;

if the test results are the same, the accuracy of the test results is qualified;

if the test results are different, the accuracy of the test results is not qualified. By the method provided by the embodiment, the accuracy of the detection model can be verified. And further evaluate the accuracy of the detection model during the test.

8. The embodiment of the invention further comprises the following steps before judging the accuracy of the first test result or the second test result: screening the first test result or the second test result based on a preset filtering option, and judging the accuracy of the screened test result so as to verify the test accuracy of the detection model. The embodiment can selectively screen the test results based on the requirements of the designer and verify the test accuracy of the detection model based on the test results, and has high selectivity.

9. The embodiment of the invention also provides a verification model which has the same beneficial effects as the method for verifying the function of the design layout detection model, and the description is omitted herein.

10. The embodiment of the invention also provides a test system, which has the same beneficial effects as the verification model, and is not described herein.

The above describes in detail a method for verifying the function of a design layout detection model, a verification model and a test system, and specific examples are applied to describe the principle and implementation of the present invention, and the description of the above embodiments is only used to help understand the method and core idea of the present invention; meanwhile, as for those skilled in the art, according to the idea of the present invention, there are changes in the specific embodiments and the application scope, and in summary, the present disclosure should not be construed as limiting the present invention, and any modifications, equivalent substitutions and improvements made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method for verifying the function of a detection model of a design layout is used for verifying the test accuracy of the detection model and is characterized in that: the method comprises the following steps:

Providing a standard design layout and judging the layer number of the standard design layout;

If the single-layer standard design layout is single-layer, generating a first test case, and testing the first test case based on a first scene to obtain a first test result;

if the design is double-layer, generating a second test case for the double-layer standard design layout, and testing the second test case based on a second scene to obtain a second test result;

And judging the accuracy of the first test result or the second test result to verify the test accuracy of the detection model.

2. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: providing a standard design layout specifically includes:

Acquiring a plurality of sample design layouts, extracting design patterns in the sample design layouts, and classifying the extracted design patterns according to preset classification rules to obtain a plurality of different types of design patterns;

each kind of design pattern is set on a layout to obtain a standard design layout.

3. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: the area of the standard design layout is smaller than that of the sample design layout.

4. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: generating a first test case for the single-layer standard design layout comprises:

the single-layer standard design layout comprises a polygon layer and a linear layer;

The single-layer standard design layout generates at least two first test cases based on a polygon layer, a linear layer, a preset checking mode, a preset measuring method and a preset output form.

5. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: generating a second test case for the double-layer standard design layout comprises:

The double-layer standard design layout comprises a polygon layer and a linear layer;

Combining the polygonal layer and the linear layer to obtain a combined layer;

the double-layer standard design layout generates at least three second test cases based on the combined layers, the preset check mode, the preset measurement method and the preset output form.

6. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: the first scene and the second scene are formed by combining a plurality of limiting conditions, and the limiting conditions included in the first scene and the limiting conditions included in the second scene are different.

7. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: judging the accuracy of the first test result or the second test result comprises:

obtaining an expected detection result of the standard design layout in the first scene or the second scene;

acquiring an actual detection result, wherein the actual detection result comprises a first test result and/or a second test result;

judging whether the expected detection result is the same as the actual detection result;

if the test results are the same, the accuracy of the test results is qualified;

if the test results are different, the accuracy of the test results is not qualified.

8. A method of verifying design layout detection model functionality as claimed in claim 1, wherein: before judging the accuracy of the first test result or the second test result, the method further comprises the following steps:

screening the first test result or the second test result based on a preset filtering option, and judging the accuracy of the screened test result so as to verify the test accuracy of the detection model.

9. A verification model for verify the test accuracy of a detection model, characterized in that: the verification model includes:

and (3) a design module: for obtaining a standard design layout;

And a judging module: the method is used for judging the layer number of the standard design layout;

the processing module is used for: the method comprises the steps of generating a first test case or a second test case;

and a testing module: the method comprises the steps of testing a first test case based on a first scene to obtain a first test result, or testing a second test case based on a second scene to obtain a second test result;

and (3) a verification module: the method is used for judging the accuracy of the first test result or the second test result so as to verify the test accuracy of the detection model.

10. A test system, characterized by: the test system comprising an input module, an output module and a verification model as claimed in claim 9;

The input module is used for inputting the design layout into the verification model;

the verification model is used for testing the design graph in the design layout in the system;

and the output module is used for outputting the result tested by the verification model.