CN118013918A - Global polygon processing method and layout parallel acceleration processing method - Google Patents

Abstract

The invention discloses a global polygon processing method and a layout parallel acceleration processing method. The processing method of the global polygon comprises the following steps: classifying global polygons in the layout according to the shapes of the global polygons, wherein the classification comprises at least one of standard polygons and complex polygons; if the complex polygon exists, decomposing the complex polygon into a plurality of standard polygons to jointly represent the complex polygon; determining the distribution condition of each standard polygon in a unit square threshold of the layout; the standard polygon with global polygon distributed on a plurality of unit square threshold is characterized by a plurality of sub-polygons; after the corresponding operation is completed by each unit square, each corresponding sub-polygon is stitched into a corresponding global polygon; and performing an equivalent verification operation on the stitched global polygon and the original global polygon. The invention can accelerate the processing speed of the integrated circuit layout.

Description

Global polygon processing method and layout parallel acceleration processing method

Technical Field

The invention relates to the technical field of processing of large-chip electronic integrated circuits in EDA industry, in particular to a global polygon processing method of a layout of an integrated circuit and a parallel acceleration processing method of the layout, which are suitable for improving the speed, the efficiency and the accuracy of circuit verification and circuit performance optimization in the electronic design process; meanwhile, the method is also suitable for realizing and optimizing parallel algorithms of full-chip process equipment simulation in a semiconductor manufacturing end.

Background

The field of application of modern semiconductor electronic integrated circuits is more and more, the functions which can be realized are stronger and stronger, the method is a fine process of complexity, fine division, long time and fine processing from design to manufacture, sealing and final forming and assembling of finished products, and generally, an electronic product can be put on the market for a period of one year or even a plurality of years from the formation concept, the circuit design, the production and manufacturing, the sample performance test and the like.

Because of the increasing complexity and diversity of integrated circuits, the accuracy and reliability of the design at the beginning is particularly important, and the existing progressive simulation verification method is difficult to meet the requirements of new products for coming out as soon as possible.

To break through increasingly lengthy and unbearable circuit design process verification, error correction, and iteration processes, various new alternative acceleration algorithms are in the attempt.

As shown in fig. 1, in the prior art, in order to achieve acceleration of processing of an integrated circuit, a layout of the integrated circuit is generally divided into a plurality of blocks, each block is a unit side (tile), each unit side (tile) is sent to one woker (such as a server or a process) of a distributed system for processing, for decoupling between the unit sides (tile), the unit side (tile) sent to each woker also extends a part outwards according to a polygon spacing requirement of a rule constraint, and a part of surrounding unit sides (tile) is also encapsulated to form an extended unit side (context tile), and the extended unit side (context) is also called a partition, and each unit side (tile) is actually sent to each work for processing in a form of an extended unit side (tile).

Along with the division of the layout, the polygons on the layout are also divided into local polygons, the shapes of the existing local polygons are uncertain, if the existing local polygons are positioned at the corresponding expansion unit square limit, the local polygons are sent to the corresponding woker for processing, then the local polygons are combined into new global polygons, and the specific processing of the local polygons lacks a corresponding accelerating technical scheme, namely, how to process the global polygons, so that the processing of an integrated circuit can be accelerated.

Disclosure of Invention

In order to solve the technical problem that the processing of the global polygon is relatively slow in the prior art, the invention provides a global polygon processing method and a layout parallel acceleration processing method.

The invention provides a processing method of global polygons in an integrated circuit layout, which comprises the following steps:

Classifying global polygons in the layout according to the shapes of the global polygons, wherein the classification comprises at least one of standard polygons and complex polygons;

If the complex polygon exists, decomposing the complex polygon into a plurality of standard polygons to jointly represent the complex polygon;

determining the distribution condition of each standard polygon in a unit square threshold of the layout;

the standard polygon with global polygon distributed on a plurality of unit square threshold is characterized by a plurality of sub-polygons;

after the corresponding operation is completed by each unit square, merging the corresponding sub-polygons into corresponding global polygons;

and performing peer verification operation on the combined global polygon and the original global polygon.

Further, the standard polygon is defined as: four sides which are mutually perpendicular are connected according to a single specific direction to form a closed quadrangle.

Further, the standard polygon, sub-polygon, is characterized by two vertices located on a diagonal.

Further, determining the distribution of each standard polygon in the unit square threshold of the layout specifically includes:

Determining a unit square threshold to which the standard polygon belongs;

calculating global coordinates of two vertexes which can represent the unit square threshold in the layout;

calculating global coordinates of two vertexes which can represent the standard polygon in the layout;

determining a unit square threshold which can be characterized as falling into two vertexes of the standard polygon, and calculating relative coordinates of the two vertexes on the corresponding unit square threshold;

the total number of cell-side threshold values spanned by the standard polygon is calculated.

Further, calculating global coordinates in the layout of two vertices that may characterize a cell side of the standard polygon include:

Determining the matrix position of the unit Fang Jue in the layout and the size of a unit square threshold;

and calculating global coordinates of two vertexes which can characterize the unit square threshold according to the matrix position and the size of the unit square threshold.

Further, determining a cell-side threshold that can characterize the two vertices of the standard polygon to fall into includes:

dividing the global coordinates of the vertexes by the corresponding size of the unit square threshold, and rounding down to obtain the matrix position of the unit Fang Jue in the layout, where the vertexes fall.

Further, the characterizing the standard polygon with the global polygon distributed on the plurality of unit square-poles by the plurality of sub-polygons specifically includes:

Determining a unit square threshold where each sub-polygon is located;

The relative coordinates of the two vertices characterizing each sub-polygon within the corresponding cell square are calculated.

The parallel acceleration processing method of the layout provided by the invention comprises the following steps:

Step 1, obtaining complete global polygon information of a layout and parallel calculation splitting information of the layout;

Step 2, processing the global polygon of the layout by adopting the processing method of the global polygon of the technical scheme;

And step 3, storing all polygons for completing the operation of peer verification according to a preset format.

The invention classifies the global polygon, then uniformly divides the global polygon into the shapes of the standard polygon for processing, further converts the global polygon into the corresponding sub-polygon for storing the corresponding information and data structure according to the cell side difference of the standard polygon, so that the speed of the integrated circuit in the parallel processing process can be further accelerated.

Drawings

The invention is described in detail below with reference to examples and figures, wherein:

FIG. 1 is a schematic diagram of a layout divided into cell side-to-side ratio of an embodiment of the present invention.

FIG. 2 is a schematic diagram of a complex polygon according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a standard polygon distribution within a cell side threshold according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a global polygon distribution within a cell side threshold according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a global polygon distribution within each cell side of an embodiment of the present invention.

FIG. 6 is a layout parallel acceleration flow diagram of an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.

The invention relates to a processing method of global polygons in an integrated circuit layout, which mainly comprises the following steps.

And step 10, classifying global polygons in the layout according to the shapes of the global polygons, wherein the classification of the global polygons comprises at least one of standard polygons and complex polygons. The standard polygon is a polygon which has a simple structure and can be relatively simple in corresponding calculation, and is named as simple polygon, spolygon for short, and detailed definition of the standard polygon is given later.

And step 20, if the complex polygon exists in the layout, decomposing the complex polygon into a plurality of standard polygons to be jointly represented. That is, all polygons in the layout may ultimately be represented by standard polygons, thereby increasing the processing speed of the integrated circuit. If there are extreme cases, such as no complex polygons in the layout, this step may be omitted.

And 30, determining the distribution condition of each standard polygon in the unit square threshold of the layout. A standard polygon may be distributed in one cell or in multiple cells, and thus the distribution of the standard polygon needs to be determined.

In step 40, the standard polygon with global polygons distributed over a plurality of cell squares is characterized by a plurality of sub-polygons. If the standard polygon is distributed among a plurality of unit square-poles, the standard polygon is divided into sub-polygons located in each unit square-pole according to the division manner of the unit square-poles, so that the global polygon can be finally represented by a plurality of sub-polygons.

Step 50, after each unit square is completed the corresponding operation, stitching each corresponding sub-polygon into a corresponding global polygon.

Step 60, performing an operation of verifying the equality of the stitched global polygon and the original global polygon.

The definition of the global polygon of the present invention is: in the original full-chip layout (layout), a geometric figure composed of paths completely closed along a single prescribed direction is composed of four or more vertices. I.e. in geometry, any edge made up of two adjacent vertices is a horizontal or vertical scene. The invention classifies the global polygon first, and uniformly disassembles the global polygon to be simplified into sub-polygons according to the classification condition, thereby accelerating the processing of the global polygon.

Although in existing integrated circuit designs, the global polygons that they contain typically have both standard and complex polygons. But either global polygon case falls within the scope of the present invention. That is, the shape of the global polygon in the layout is the standard polygon defined by the invention, or is the complex polygon defined by the invention, or both the standard polygon and the complex polygon are included, which belong to the protection scope of the invention.

In one embodiment, the standard polygon of the present invention refers to a closed quadrilateral composed of four sides that are perpendicular to each other and joined in a single specific direction. For example, four sides which are mutually perpendicular are connected in a counterclockwise direction or a clockwise direction to form a closed quadrangle.

Based on this embodiment, a person skilled in the art may further add corresponding features to define a specific standard polygon according to the specific situation, for example, define the standard polygon as a square, a rectangle with a given size, or the like in the specific application. The present invention is not limited to the standard polygon further limitations, and various further limitations are defined based on the standard polygon of the present invention, and therefore all fall within the scope of the present invention.

A standard polygon may be characterized by two vertices lying on a diagonal. For example, a standard polygon is characterized by an upper left corner vertex P1 (x 1, y 1), a lower right corner vertex P2 (x 2, y 2), or by an upper left corner vertex P1 (x 1, y 1), an upper right corner vertex P2 (x 2, y 2), or by an upper right corner vertex P1 (x 1, y 1), an upper left corner vertex P2 (x 2, y 2), or by an upper right corner vertex P1 (x 1, y 1), a lower left corner vertex P2 (x 2, y 2).

The sub-polygon is formed by dividing the standard polygon on different unit square-poles, so that the shape of the sub-polygon also accords with the definition of the standard polygon, and the sub-polygon can be characterized by two vertexes on the diagonal line. The sub-polygons may also be referred to as Local polygons, simply Lpolygon. The sub-polygons are divided into two types, one is a new sub-polygon, also called new Lpolygon, and the other is a next sub-polygon, also called next Lpolygon. When a sub-polygon is cut directly from a global polygon, then the sub-polygon is referred to as a new sub-polygon. After the global polygon is segmented by taking the unit square (tile) as a unit, the global polygon is contained in each extension unit square (tile) and is sent to each work for processing, and each group of sub-polygons and the global polygon corresponding to each group of sub-polygons always maintain the mapping relation between each other. When processing each sub-polygon, by maintaining the perception of the overall parameters of the global polygon (GPolygon) corresponding to the sub-polygon, the invention can process each LPolygon in parallel in different tiles, or correctly process each segment of GPolygon in tile units, then correctly stitch or merge each LPolygon after processing, and restore to processed GPolygon. Due to the parallel algorithm, intermediate results are generated during the merging process, and new LPolygon is generated continuously due to the partial merging of the sub-polygons, and the sub-polygons other than the new sub-polygon (new Lpolygon) and the global polygon (Gpolygon) are called secondary LPolygon. For example, newborns LPolygon, LPolygon2, LPolygon 3, LPolygon, and LPolygon are combined into LPolygon (1, 2) and LPolygon (3, 4) and GPolygon (1, 2,3, 4).

A complex polygon, also known as a combined polygon, is given in fig. 2 as a specific example of a complex polygon. The complex polygon has six vertices A, B, C, D, E, F. The complex polygon may be further decomposed into two connected Spolygon. I.e. white Spolygon and grey Spolygon in the illustration.

In a specific embodiment, the determining the distribution of each standard polygon in the cell square threshold of the layout in the above technical solution specifically includes the following steps.

Determining the unit square threshold to which the standard polygon belongs. Specifically, the matrix position of the cell Fang Jue in the layout, and the size of the cell side threshold may be determined first.

Global coordinates in the layout that characterize the two vertices of the cell side are calculated. Specifically, global coordinates of two vertices that can characterize the cell side may be calculated based on the matrix position and the size of the cell side.

Calculating global coordinates of two vertexes which can represent the standard polygon in the layout;

determining a unit square threshold which can be characterized as falling into two vertexes of the standard polygon, and calculating relative coordinates of the two vertexes on the corresponding unit square threshold;

The total number of cell-side threshold values spanned by the standard polygon is calculated.

In the above technical solution, determining the unit square threshold that two vertices of the characterizable standard polygon fall into includes: dividing the global coordinates of the vertexes by the corresponding size of the cell square threshold, and rounding down to obtain the matrix position of the cell Fang Jue in the layout, where the vertexes fall.

In the above technical solution, the standard polygon with global polygons distributed on multiple unit square-case points adopts multiple sub-polygon characterization specifically includes: determining a unit square threshold where each sub-polygon is located; the relative coordinates of the two vertices characterizing each sub-polygon within the corresponding cell square are calculated.

Fig. 3 shows a schematic diagram of the distribution of 7 different shapes of the standard polygon of the present invention in a certain cell. In the figure, the standard polygon 3, the standard polygon 4, the standard polygon 5, the standard polygon 8 and the standard polygon 9 all fall within the unit square threshold, the standard polygon 1 is the case of falling inside the tile, and the standard polygons 9 and the standard polygons 3 to 5 are respectively contacted with one side or two sides or three sides of the tile boundary. Standard polygon 6 and standard polygon 7 are different situations in which Spolygon may fall into more than one tile.

As shown in fig. 4, the coordinate system of the present invention adopts a cadier coordinate system whose absolute coordinates are based on an origin (0, 0) located at the lower left corner, the directions sequentially increasing in the x direction to the right and in the y direction to the upward. The global, i.e. absolute, coordinates of each vertex are positions relative to the origin of the lower left corner of the layout. The solid line box is a single tile, and i, j is used for representing the matrix position attribute, which indicates the tile currently being processed. the tile interior (including edges) is defined similarly, and relative to the global, the tile interior adopts a relative coordinate system, the origin (0, 0) of the relative coordinate system is set at the lower left corner of the square frame of each tile, the upper right corner is the maximum value of the coordinate system, and the relative coordinate system is determined by the size of the tile. In this case, the variable (a, b) is set as desired. The only constraints that must be satisfied are: a >0, b >0. In addition, for the simplicity of the computer programming and calculation process and the convenience of memory management, the values of the simplifications can be set to be integers, and the sizes of the simplifications can be determined to be known, namely, the simplifications can be set or automatically calculated according to the resources. m, n are matrix row and column maximum variables representing tile, and the values are selected from parameters and variables associated with algorithm, i.e. allocation and response of allocated resources such as CPU, memory, hard disk and other hardware resources.

The grey part in fig. 4 is an example of Gpolygon that needs to be examined. In this example, a standard Polygon (Simple Polygon) is selected as the global Polygon, and the standard Polygon can be characterized as two points in the figure, namely, a right lower corner P1 (x 1, y 1) and a left upper corner P2 (x 2, y 2) in the global position and the feature. Simple Polygon (Spolygon) is well defined and its read position and order need to be consistent by definition for any Spolygon.

Taking this global polygon as an example, the present invention needs to perform the following processing.

Step 101, characterizing Gpolygon and Lpolygon possibly distributed in different spatial domains, i.e. Lpolygon distributed in different cell lines;

Step 102, characterizing the distribution in different spatial domains Lpolygon;

Step 103, completing operations such as Lpolygon calculation and the like according to a given program and requirements;

Step 104, after all tiles containing Lpolygon complete the operation, the information merge Lpolygon and the peer verification work with Gpolygon are completed.

The step 103 is performed according to different requirements, and the step 103 is not necessary according to the application.

A specific algorithm will be described in detail using fig. 4 as an example.

The algorithm is used for guaranteeing the uniqueness of the value domain in the global range and minimizing the number of the spans, and for points on the span boundary, the algorithm makes the following constraint: the coordinate value range of the first row and the first column is X epsilon [0, a ], Y epsilon [0, b ]; the remainder is X.epsilon. (0, a), Y.epsilon. (0, b.) for the latter, the algorithm involved in the present invention will be adapted accordingly.

Let i=5; j=6; a=10; b=15.

The global coordinate of the top left vertex of the tile is (i x a, (j+1) x b), i.e., (50, 105). The global coordinates of the lower right vertex are (i+1) a, j b), i.e., (60, 90).

Then the coordinates of the two vertices (upper left corner vertex P1, lower right corner vertex P2) of the global polygon representing gray are p1.x=46, p1.y=95; p2.x=54, p2.y=84.

Observing the distribution of the global polygon in tile in the graph can calculate the following information.

The locations (r, c) of the row columns of the associated tile of the top left corner vertex of the global polygon are calculated, where r is the location of the column, i.e., the longitudinal direction (y-direction), and c is the location of the row, i.e., the lateral direction (y-direction).

P1.r=floor (p1.y/b), i.e. p1.r=floor (95/15) =6.

P1.c=floor (p1.x/a), i.e. p1.c=floor (46/10) =4.

The relative coordinate values (X, Y) of the vertex P1 of the global polygon in the figure at the tile where it is located are calculated.

P1.x= (p1.x)% a, i.e. p1.x=46%10=6;

p1.y= (p1.y)% b, i.e. p1.y=95%15=5.

And calculating the row and column positions of the tile to which the right lower corner vertex of the global polygon belongs.

P2.r=floor (p2.y/b), i.e. p2.r=floor (84/15) =5;

p2.c=floor (p2.x/a), i.e. p2.c=floor (54/10) =5.

And calculating the relative coordinate value (X, Y) of tile where P2 is located.

P2.x= (p2.x)% a, i.e. p2.x=54%10=4;

P2.y= (p2.y)% b, i.e. p2.y=84%15=9.

The total number of tiles spanned is calculated.

total＝(P2.c–P1.c+1)*(P1.r–P2.r+1)；

That is, total= (5-4+1) × (6-5+1) =4.

Fig. 5 is a schematic diagram showing the distribution of each of the different tiles Lpolygon and corresponding tiles for Gpolygon shown in fig. 4. Since the dimensions of the unit square are uniform, for convenience of explanation, fig. 5 places the relative dimensions of the unit square below the middle, and places the overall distribution of the global polygon above the middle, so as to refer to other sub-polygons, and at the same time, highlights each sub-polygon.

The rank positions of tile, and their corresponding coordinate values, that the global polygon may span, except for vertices P1, P2 are calculated.

The relative coordinates of the two vertices of the sub-polygon to the upper left of the global polygon in the figure are calculated as follows.

GP(1,1).P1.X＝P1.X＝6；GP(1,1).P1.Y＝P1.Y＝5；

GP(1,1).P2.X＝a＝10；GP(1,2).P1.Y＝0。

The rank position of tile in which the upper right sub-polygon of the global polygon is located, and the relative coordinates of the two vertices characterizing the sub-polygon are calculated as follows.

GP(1,2)＝pair(P1.r,P1.c+1)＝pair(6,5)；

GP(1,2).P1.X＝0；GP(1,2).P1.Y＝P1.Y＝5；

GP(1,2).P2.X＝P2.X＝4；GP(1,2).P1.Y＝0；

The rank position of tile in which the lower left sub-polygon of the global polygon is located, and the relative coordinates of the two vertices characterizing the sub-polygon are calculated as follows.

GP(2,1)＝pair(P2.r,P2.c-1)＝pair(5,4)；

GP(2,1).P1.X＝P1.X＝6；GP(2,1).P1.Y＝15；

GP(2,1).P2.X＝a＝10；GP(2,1).P2.Y＝P2.Y＝9；

The relative coordinates of the two vertices of the sub-polygon to the bottom right of the global polygon in the figure are calculated as follows.

GP(2,2).P1.X＝0；GP(2,2).P1.Y＝b＝15；

GP(2,2).P2.X＝P2.X＝4；GP(2,2).P1.Y＝P2.Y＝9。

Through the algorithm, the information of the global polygon divided into a plurality of sub-polygons is stored in a corresponding data structure.

The invention also provides a parallel acceleration processing method of the layout, which comprises the following steps.

Step 1, obtaining complete global polygon information of a layout and parallel calculation splitting information of the layout; the present invention is not limited to the specific content of the global polygon information, and may be information of vertices, information of shapes, or the like. The parallel calculation splitting information of the layout refers to the information of dividing the layout into a plurality of unit square limit and an expansion unit square limit.

Step 2, processing the global polygon of the layout by adopting the processing method of the global polygon of the technical scheme;

And step 3, storing all polygons for completing the operation of peer verification according to a preset format.

The full layout acceleration process flow of the present invention is shown in FIG. 6. The global polygon (GPolygon) in the figure stores information and data structures, which may be vertex information of the global polygon and corresponding data structures of tile where the global polygon is located, such as a pair data structure, and the parallel computing split information may be information that a layout is divided into a plurality of unit square-nodes and an expansion unit square-node. The sub-polygon (Lpolygon) storage information may be vertex information of the sub-polygon and information of a specific distributed cell-side. The pre-specified computation and operation can be set by those skilled in the art as required, and then the vertex information of the sub-polygons after computation and the information or data structure of the specifically distributed cell-side case are stored.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (8)

1. A method for processing global polygons in an integrated circuit layout, comprising:

Classifying global polygons in the layout according to the shapes of the global polygons, wherein the classification comprises at least one of standard polygons and complex polygons;

If the complex polygon exists, decomposing the complex polygon into a plurality of standard polygons to jointly represent the complex polygon;

determining the distribution condition of each standard polygon in a unit square threshold of the layout;

the standard polygon with global polygon distributed on a plurality of unit square threshold is characterized by a plurality of sub-polygons;

after the corresponding operation is completed by each unit square, each corresponding sub-polygon is stitched into a corresponding global polygon;

And performing an equivalent verification operation on the stitched global polygon and the original global polygon.

2. The method for processing global polygons in an integrated circuit layout according to claim 1, wherein said standard polygons are defined as: four sides which are mutually perpendicular are connected according to a single specific direction to form a closed quadrangle.

3. A method of processing global polygons in an integrated circuit layout according to claim 2, wherein the standard polygon and the sub-polygon are each characterized by two vertices located on their diagonals.

4. A method for processing global polygons in an integrated circuit layout according to claim 3, wherein determining the distribution of each standard polygon in the cell side of the layout comprises:

Determining a unit square threshold to which the standard polygon belongs;

Calculating global coordinates of two vertexes of a unit square threshold which can represent the standard polygon in the layout;

calculating global coordinates of two vertexes which can represent the standard polygon in the layout;

determining a unit square threshold which can be characterized as falling into two vertexes of the standard polygon, and calculating relative coordinates of the two vertexes on the corresponding unit square threshold;

the total number of cell-side threshold values spanned by the standard polygon is calculated.

5. The method according to claim 4, wherein calculating global coordinates in the layout of two vertices characterizing a cell side to which the standard polygon belongs, the global coordinates comprising:

Determining the matrix position of the unit Fang Jue in the layout and the size of a unit square threshold;

and calculating global coordinates of two vertexes which can characterize the unit square threshold according to the matrix position and the size of the unit square threshold.

6. The method of processing a global polygon in an integrated circuit layout according to claim 4, wherein determining a cell square threshold that characterizes two vertices of the standard polygon to fall into comprises:

dividing the global coordinates of the vertexes by the corresponding size of the unit square threshold, and rounding down to obtain the matrix position of the unit Fang Jue in the layout, where the vertexes fall.

7. The method for processing a global polygon in an integrated circuit layout according to claim 4, wherein the step of characterizing a standard polygon having the global polygon distributed on a plurality of unit square-poles with a plurality of sub-polygons specifically comprises:

Determining a unit square threshold where each sub-polygon is located;

The relative coordinates of the two vertices characterizing each sub-polygon within the corresponding cell square are calculated.

8. A parallel acceleration processing method of a layout is characterized by comprising the following steps:

Step 1, obtaining complete global polygon information of a layout and parallel calculation splitting information of the layout;

step2, processing the global polygon of the integrated circuit layout by adopting the processing method of the global polygon in the integrated circuit layout according to any one of claims 1 to 7;

And step 3, storing all polygons for completing the operation of peer verification according to a preset format.