CN118012225A - RTC timing system and method - Google Patents

Abstract

The invention discloses an RTC timing system and method. The system comprises a phase discrimination module for determining phase deviation between a low-frequency reference clock and a frequency division clock to be calibrated; the adjusting module is used for adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation to obtain a frequency calibration clock; the frequency division module is used for dividing the frequency calibration clock to obtain a current frequency division calibration clock, feeding the current frequency division calibration clock back to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock; and the time module is used for carrying out time alignment on the first target frequency division calibration clock and TOD time to obtain time correction time. According to the embodiment of the invention, the problem that the time correction precision is reduced or the residual calibration error is compensated due to environmental change can be solved by the technical scheme, the time correction accuracy can be improved, and the time correction requirement of high precision is met.

Description

RTC timing system and method

Technical Field

The invention relates to the technical field of RTC real-time clock calibration, in particular to an RTC timing system and an RTC timing method.

Background

The real-time clock rtc module provides stable system time for the soc system, and timing accuracy is very critical. In the prior art, an open loop structure is mostly adopted to calibrate or time the rtc timing, and by way of example, the time calibration is performed by utilizing the relation between the ambient temperature and the crystal output frequency, and the calibration mode cannot adapt to the ambient change in real time, so that the compensation precision is reduced, and the high-precision requirement cannot be met. In order to solve the problem that the time correction accuracy is reduced or the residual calibration error is compensated due to environmental changes (such as before and after the chip packaging process), a system and a method for RTC device time correction are needed.

Disclosure of Invention

In view of the above, the embodiment of the invention provides an RTC timing system, which can solve the problems of reduced timing precision or residual calibration error compensation caused by environmental changes, can improve the timing accuracy, and meets the timing requirement of high precision.

According to an aspect of the present invention, an embodiment of the present invention provides an RTC timing system, including: the device comprises a phase discrimination module, an adjustment module, a frequency division module and a time module;

the phase discrimination module is used for acquiring a low-frequency reference clock and a frequency division clock to be calibrated of the RTC real-time clock chip and determining phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated;

the adjusting module is used for adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation to obtain a frequency calibration clock after frequency calibration;

The frequency division module is used for dividing the frequency calibration clock after frequency calibration to obtain a current frequency division calibration clock after frequency division, feeding the current frequency division calibration clock back to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock;

and the time module is used for carrying out time alignment on the first target frequency division calibration clock and the preset TOD time so as to obtain the time correction time after the frequency division clock to be calibrated is aligned.

According to another aspect of the present invention, an embodiment of the present invention further provides an RTC timing method, which is characterized in that the method is applied to an RTC timing system, and includes:

acquiring a low-frequency reference clock and a frequency division clock to be calibrated of an RTC real-time clock chip through a phase discrimination module, and determining phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated;

Adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation by an adjusting module to obtain a frequency calibration clock after frequency calibration;

Dividing the frequency calibration clock by a frequency dividing module to obtain a current frequency division calibration clock after frequency division, feeding back the current frequency division calibration clock to a phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock;

and performing time alignment on the first target frequency division calibration clock and the preset TOD time through a time module to obtain the time alignment time of the frequency division clock to be calibrated after alignment.

In the technical scheme provided by the embodiment of the invention, the phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated is determined through the phase discrimination module; the adjusting module adjusts the output clock frequency of the frequency division clock to be calibrated according to the phase deviation to obtain a frequency calibration clock after frequency calibration; the frequency division module divides the frequency calibration clock after frequency calibration to obtain a current frequency division calibration clock after frequency division, and feeds back the current frequency division calibration clock to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock; and finally, performing time alignment on the first target frequency division calibration clock and TOD time through a time module to obtain time correction time. According to the embodiment of the invention, a simplified closed-loop negative feedback adjustment loop is formed through the phase discrimination module, the adjustment module, the frequency division module and the time module, the error is continuously reduced through multiple iterations, and finally the error approaches 0, so that the aim of timing is realized, the problem that the timing precision is reduced or the residual calibration error is compensated due to environmental changes (such as before and after chip packaging processing) can be solved, the timing accuracy can be improved, and the timing requirement of high precision is met.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an RTC timing system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an RTC timing system according to an embodiment of the present invention;

FIG. 3 is a flowchart of an RTC timing method according to an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the term "object" and the like in the description of the present invention and the claims and the above drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In an embodiment, fig. 1 is a schematic structural diagram of an RTC timing system according to an embodiment of the present invention, where the embodiment is applicable to a case of performing real-time timing on an RTC, and referring to fig. 1, the RTC timing system in the embodiment includes:

The device comprises a phase discrimination module 110, an adjustment module 120, a frequency division module 130 and a time module 140;

The phase discrimination module 110 is configured to obtain a low-frequency reference clock and a frequency division clock to be calibrated of the RTC real-time clock chip, and determine a phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated;

The adjusting module 120 is configured to adjust an output clock frequency of the frequency-divided clock to be calibrated according to the phase deviation to obtain a frequency-calibrated clock;

The frequency dividing module 130 is configured to divide the frequency calibration clock to obtain a current frequency-divided calibration clock after frequency division, and feed back the current frequency-divided calibration clock to the phase detection module 110 to form a closed-loop negative feedback adjustment loop, so that the phase detection module 110 outputs a first target frequency-divided calibration clock with an error reaching a preset error threshold to the time module 140 according to an error between the current frequency-divided calibration clock and the low-frequency reference clock;

And a time module 140, configured to time align the first target divided calibration clock with a preset TOD time, so as to obtain an aligned time correction time.

The frequency calibration clock refers to a frequency calibration clock obtained after the adjustment by the adjustment module 120. The preset error threshold refers to an error threshold which is preset and needs to be reached by the error between the current frequency division calibration clock and the low frequency reference clock, and the error threshold is generally close to 0 and can be set by the user according to requirements. The current divided calibration clock may be understood as a divided calibration clock obtained by dividing the frequency calibration clock. The first target frequency division calibration clock can be understood as a target frequency division calibration clock which is finally output by the phase discrimination module and reaches a preset error threshold under the condition of the external low-frequency reference clock.

In this embodiment, the low frequency reference clock may be understood as a reference clock transmitted to the RTC real-time clock chip by the external system; the frequency division clock to be calibrated is the RTC internal frequency division clock generated in the RTC real-time clock chip. In this embodiment, the phase detection module 110 may be configured to obtain the low-frequency reference clock transmitted from the outside and the frequency-division clock to be calibrated of the RTC real-time clock chip, and determine the phase deviation between the low-frequency reference clock and the frequency-division clock to be calibrated by using the rising edge or the falling edge of the low-frequency reference clock and the frequency-division clock to be calibrated respectively.

In this embodiment, the adjustment module 120 may receive the phase deviation transmitted by the phase detection module 110, convert the phase deviation into a corresponding capacitance adjustment amount by corresponding conversion, and adjust the output clock frequency of the RTC real-time clock chip according to the increase or decrease of the capacitance adjustment amount to obtain the frequency calibration clock after frequency calibration.

In this embodiment, the frequency dividing module 130 receives the frequency calibration clock after frequency calibration transmitted by the adjusting module 120, then divides the frequency calibration clock after frequency calibration to obtain a current frequency division calibration clock after frequency division, and feeds back the current frequency division calibration clock to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module 110 outputs a first target frequency division calibration clock with an error reaching a preset error threshold to the time module 140 according to an error between the current frequency division calibration clock and the low frequency reference clock; it can be understood that, the external low-frequency clock and the rtc frequency-divided clock enter the phase discrimination module 110, the phase deviation obtained by the phase discrimination module 110 is sent to the adjustment module 120, the adjustment module adjusts the phase deviation, then the adjusted clock is fed back to the phase discrimination module 110 again after being divided by the frequency division module 130, so as to form a closed-loop negative feedback adjustment loop, the error is continuously reduced after multiple iterations, and finally the error approaches 0. Specifically, the phase detection module 110 may judge the error between the current frequency division calibration clock and the low frequency reference clock, and in the case that the error does not reach the first target frequency division calibration clock with the preset error threshold, the phase detection module 110 uses the current frequency division calibration clock as the next frequency division calibration clock, calculates the error between the next frequency division calibration clock and the low frequency reference clock, and then inputs the error to the adjustment module again to execute the whole process until the output error reaches the preset error threshold, and outputs the first target frequency division calibration clock with the preset error threshold to the time module 140.

In this embodiment, the time module 140 performs time alignment on the first target frequency division calibration clock and the preset TOD time when the first target frequency division calibration clock whose error reaches the preset error threshold is received, so as to obtain the aligned time alignment time. In this embodiment, the time module 140 counts using the timing pulses, resulting in a calendar and TOD time.

In the technical scheme provided by the embodiment of the invention, the phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated is determined through the phase discrimination module; the adjusting module adjusts the output clock frequency of the RTC according to the phase deviation to obtain a frequency calibration clock after frequency calibration; the frequency division module divides the frequency calibration clock after frequency calibration to obtain a current frequency division calibration clock after frequency division, and feeds back the current frequency division calibration clock to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock; and finally, performing time alignment on the first target frequency division calibration clock and TOD time through a time module to obtain time correction time. According to the embodiment of the invention, a simplified closed-loop negative feedback adjustment loop is formed by the phase discrimination module, the adjustment module, the frequency division module and the time module, the error is continuously reduced after multiple iterations, and finally the error approaches 0, so that the aim of timing is realized, the problem that the timing precision is reduced or the residual calibration error is compensated due to environmental change can be solved, the timing accuracy can be improved, and the timing requirement of high precision is met.

In an embodiment, the system further comprises: a filtering module;

the filtering module is configured to receive the phase deviation transmitted by the phase detection module 110, perform low-pass filtering on the phase deviation to obtain a filtered phase deviation, and convert the phase deviation into a frequency deviation.

In this embodiment, the filtering module may be located between the phase detection module 110 and the adjustment module 120, and may be configured to receive the phase deviation transmitted by the phase detection module 110, perform low-pass filtering on the phase deviation to obtain a filtered phase deviation, and convert the phase deviation into a frequency deviation. Specifically, the manner of converting the phase deviation into the frequency deviation may include: the frequency deviation is obtained by the ratio of the phase deviation to the time, but of course, the conversion may be performed by other methods in the prior art, and the embodiment is not limited herein.

In an embodiment, the system further comprises: an interface module and a storage module;

The interface module is responsible for connecting the external upper computer and the message exchange of the storage module, and is used for reading the current frequency division calibration clock transmitted by the adjustment module 120 or the preset frequency calibration clock pre-designated by a user from the storage module;

the storage module is used for storing a preset temperature-frequency calibration relation curve, a current frequency division calibration clock and a preset frequency calibration clock.

In this embodiment, the preset frequency calibration clock may be understood as a frequency calibration value configured by a user in advance according to the requirement.

In this embodiment, the interface module may be connected to the memory module and the time module, where the interface module is responsible for connecting an external host computer and message exchange of the memory module, and is used to read the current frequency division calibration clock transmitted by the adjustment module from the memory module, or the preset frequency calibration clock specified in advance by the user, and the memory module may be connected to the adjustment module and the interface module, and is used to store the preset temperature-frequency calibration relationship curve, the current frequency division calibration clock, and the preset frequency calibration clock. In this embodiment, the clock for calibrating the preset frequency can be preconfigured from the interface module, so that when no external reference is accessed, the calibration error of the storage module can be obtained, the timing error can be automatically calibrated, and the timing pulse after frequency modulation and phase modulation is used for time timing, thereby realizing the high-precision timing function.

In some embodiments, the interface module is further to: a calendar and TOD times are preset.

In an embodiment, the adjusting module 120 is further configured to:

Under the condition that no external transmission low-frequency reference clock is accessed, the output clock frequency of the RTC real-time clock chip is automatically adjusted according to the preset frequency calibration clock and the frequency division clock to be calibrated of the RTC real-time clock chip by acquiring the preset frequency calibration clock preset by a user in the storage module, the adjusted target calibration clock is fed back to the frequency division module 130, so that the frequency division module 130 divides the target calibration clock to obtain a second target frequency division calibration clock after frequency division, and the second target frequency division calibration clock is input into the time module for time alignment.

The second target frequency division calibration clock can be understood as a target frequency division calibration clock which is finally output by the phase discrimination module and reaches a preset error threshold value under the condition of no external low-frequency reference clock, and it is to be noted that under the condition of no external low-frequency reference clock, a negative feedback loop formed by the phase discrimination module and the filtering module is not needed, and the output clock frequency of the RTC real-time clock chip is automatically adjusted according to the preset frequency calibration clock and the frequency division clock to be calibrated of the RTC real-time clock chip, so that the adjusted target calibration clock is obtained.

In this embodiment, under the condition that no external transmission is connected to the low-frequency reference clock, the adjustment module may first obtain a preset frequency calibration clock specified by a user in the storage module, and automatically adjust the output clock frequency of the RTC real-time clock chip according to the preset frequency calibration clock and the to-be-calibrated frequency division clock of the RTC real-time clock chip, so as to obtain an adjusted target calibration clock, and feed back the adjusted target calibration clock to the frequency division module 130, so that the frequency division module 130 divides the target calibration clock to obtain a divided second target frequency division calibration clock, and inputs the second target frequency division calibration clock to the time module for time alignment. It should be noted that, in the case of the low-frequency reference clock access without external transmission, the adjustment mode of the adjustment module 110, the frequency division mode of the frequency division module 130, and the time module 140 are the same as those in the case of the low-frequency reference clock access with external transmission.

In some embodiments, determining a phase offset between a low frequency reference clock and the divided clock to be calibrated comprises:

Identifying rising edges or falling edges respectively corresponding to the low-frequency reference clock and the frequency division clock to be calibrated;

The phase deviation is determined from the rising edge, or the falling edge.

In this embodiment, when determining the phase deviation between the low-frequency reference clock and the frequency-division clock to be calibrated, the phase discrimination module 110 may determine the phase deviation by identifying a rising edge or a falling edge of the low-frequency reference clock and the frequency-division clock to be calibrated, respectively, and determining the phase deviation according to the rising edge or the falling edge. The low-frequency reference clock and the frequency division clock to be calibrated have the same frequency. Specifically, the rising edges corresponding to the low-frequency reference clock and the frequency-division clock to be calibrated respectively may be compared to obtain the phase deviation between the two, or the falling edges corresponding to the low-frequency reference clock and the frequency-division clock to be calibrated respectively may be compared to obtain the phase deviation between the two, which is not limited in this embodiment.

In some embodiments, adjusting the output clock frequency of the divided clock to be calibrated according to the phase deviation to obtain the frequency-calibrated frequency calibration clock includes:

converting the phase deviation into a frequency deviation, and converting the frequency deviation into a capacitance adjustment quantity;

And adjusting the output clock frequency of the frequency division clock to be calibrated according to the capacitance adjustment quantity to obtain a frequency calibration clock after frequency calibration.

In this embodiment, when the adjustment module 120 adjusts the output clock frequency of the frequency division clock to be calibrated, it is necessary to convert the phase deviation into the frequency deviation, convert the frequency deviation into the capacitance adjustment amount, and then adjust the output clock frequency of the RTC real-time clock chip according to the capacitance adjustment amount to obtain the frequency calibration clock after frequency calibration. Specifically, the output clock frequency of the RTC clock chip is adjusted according to the adjustment amount of the capacitor to obtain the current frequency division calibration clock, and when the adjustment amount is increased, the frequency is slowed down; when the adjustment amount decreases, the frequency becomes faster.

In some embodiments, adjusting the output clock frequency of the frequency-divided clock to be calibrated according to the capacitance adjustment amount to obtain the frequency-calibrated clock includes:

under the condition that the capacitance adjustment amount is increased, adjusting the output clock frequency of the frequency division clock to be calibrated to be a first output frequency to obtain a slow frequency calibration value; the first output frequency is the frequency at which the output frequency threshold reaches a first preset frequency threshold;

under the condition that the capacitance adjustment amount is reduced, adjusting the output clock frequency of the RTC real-time clock chip to be a second output frequency to obtain a fast frequency calibration value; the second output frequency is the frequency at which the output frequency threshold reaches a second preset frequency threshold; the first preset frequency threshold is less than the second preset frequency threshold.

In this embodiment, under the condition that the capacitance adjustment amount is increased, adjusting the output clock frequency of the to-be-calibrated frequency division clock of the RTC real-time clock chip to be the first output frequency, to obtain the slow frequency calibration value; wherein the first output frequency is a slow frequency; under the condition that the capacitance adjustment amount is reduced, adjusting the output clock frequency of the to-be-calibrated frequency division clock of the RTC real-time clock chip to be the second output frequency to obtain a fast frequency calibration value; wherein the second output frequency is a fast frequency. It can be understood that, according to the adjustment amount of the capacitor, the output clock frequency of the RTC clock chip is adjusted to obtain the current frequency division calibration clock, and when the adjustment amount is increased, the frequency is slowed down; when the adjustment amount decreases, the frequency becomes faster.

In some embodiments, the phase detection module outputs a first target frequency division calibration clock to time module with an error reaching a preset error threshold according to an error between a current frequency division calibration clock and the low frequency reference clock, and the phase detection module comprises:

Comparing the current frequency division calibration clock with the low-frequency reference clock to obtain a comparison result; the comparison result represents the error between the current frequency division calibration clock and the low-frequency reference clock;

Under the condition that the error magnitude does not reach the first target frequency division calibration clock of the preset error threshold, taking the current frequency division calibration clock as the next frequency division calibration clock, calculating the error between the next frequency division calibration clock and the low frequency reference clock, inputting the error into the adjustment module again to execute the whole process until the output error reaches the preset error threshold, and outputting the first target frequency division calibration clock with the error reaching the preset error threshold to the time module.

The next frequency division calibration clock may be the first next frequency division calibration clock used as the current frequency division calibration clock, or may be the second next frequency division calibration clock, and so on, until the error between the next frequency division calibration clock and the low frequency reference clock reaches the preset error threshold.

In this embodiment, the phase demodulation module 110 compares the current frequency division calibration clock with the low frequency reference clock to obtain a comparison result when receiving the current frequency division calibration clock fed back by the frequency division module 120; wherein the comparison result characterizes the magnitude of the error between the current divided calibration clock and the low frequency reference clock; under the condition that the error magnitude does not reach the first target frequency division calibration clock of the preset error threshold, the current frequency division calibration clock is used as the next frequency division calibration clock, the error between the next frequency division calibration clock and the low frequency reference clock is calculated, the error is input to the adjustment module again, the adjustment module 120 is enabled to adjust the output clock frequency of the RTC real-time clock chip according to the error to obtain a frequency calibration value, the frequency calibration value is transmitted to the frequency division module again, the whole process is repeatedly executed until the output error reaches the preset error threshold, and the first target frequency division calibration clock with the preset error threshold is output to the time module. It should be noted that, the error in this embodiment may represent the magnitude of the phase deviation between the current frequency-dividing calibration clock and the low-frequency reference clock, which may be understood that, when the phase deviation between the current frequency-dividing calibration clock and the low-frequency reference clock is large, the steps corresponding to the adjusting module and the frequency-dividing module need to be re-executed until the current frequency-dividing calibration clock reaches balance (also referred to as locking), and after the first target frequency-dividing calibration clock is obtained, the user places the current tod time into the time module, and the time module uses this as a starting point to maintain tod timing, so that the system realizes high-precision time keeping.

In an embodiment, to facilitate better understanding of the structure of the RTC timing system, fig. 2 is a schematic structural diagram of another RTC timing system according to an embodiment of the present invention, and as shown in fig. 2, the system includes: phase discrimination module 210, filtering module 220, adjustment module 230, frequency division module 240, time module 250, interface module 260, and storage module 270.

In this embodiment, when external reference is accessed, the present invention can utilize the external low-frequency clock and the rtc frequency-divided clock to enter the phase demodulation module 210, the obtained phase deviation is sent to the adjustment module 230 after passing through the filtering module 220, the adjusted clock is sent to the phase demodulation module 210 after passing through the frequency division module 240 to divide the frequency, so as to form a closed-loop negative feedback adjustment loop, the error is continuously reduced after multiple iterations, and finally the error approaches 0. When no external reference is accessed, the preset frequency calibration clock appointed by the user in advance can be read through the interface module, the calibration error of the storage module 270 can be obtained through the adjustment module 230, the timing error is automatically calibrated, the time is timed by using the timing pulse after frequency modulation and phase modulation, and the high-precision timing function is realized.

In an embodiment, fig. 3 is a flowchart of an RTC timing method according to an embodiment of the present invention, where the method may be performed by RTC timing when performing RTC timing, and the RTC timing system may be implemented in hardware and/or software. The explanation of the nouns and the like appearing in the present embodiment has been correspondingly described above, and the present embodiment is not described.

As shown in fig. 3, the RTC timing method in this embodiment is applied to an RTC timing system, and the method specifically includes the steps of:

S310, acquiring a low-frequency reference clock and a frequency division clock to be calibrated of the RTC real-time clock chip through a phase discrimination module, and determining phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated.

S320, adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation by an adjusting module to obtain a frequency calibration value.

S330, the frequency calibration value is divided by the frequency division module to obtain a current frequency division calibration clock after frequency division, the current frequency division calibration clock is fed back to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock.

S340, performing time alignment on the first target frequency division calibration clock and the preset TOD time through a time module to obtain the time correction time after the frequency division clock to be calibrated is aligned.

In an embodiment, the method further comprises: and receiving the phase deviation transmitted by the phase discrimination module through the filtering module, performing low-pass filtering on the phase deviation to obtain the filtered phase deviation, and converting the phase deviation into frequency deviation.

In an embodiment, the method further comprises: the interface module is responsible for connecting an external upper computer and the message exchange of the storage module, and reads the current frequency division calibration clock transmitted by the adjustment module or the preset frequency calibration clock pre-designated by a user from the storage module;

and storing a preset temperature-frequency calibration relation curve, a current frequency division calibration clock and a preset frequency calibration clock through the storage module.

In an embodiment, the method further comprises: and presetting a calendar and TOD time through the interface module.

In an embodiment, the method further comprises: under the condition that no external transmission is connected with a low-frequency reference clock, a preset frequency calibration clock appointed in advance by a user in the storage module is obtained through the adjustment module, the output clock frequency of the RTC real-time clock chip is automatically adjusted according to the preset frequency calibration clock and a frequency division clock to be calibrated of the RTC real-time clock chip to obtain an adjusted target calibration clock, the adjusted target calibration clock is fed back to the frequency division module, so that the frequency division module divides the target calibration clock to obtain a second target frequency division calibration clock after frequency division, and the second target frequency division calibration clock is input into the time module to be aligned in time.

In an embodiment, the determining the phase deviation between the low frequency reference clock and the divided clock to be calibrated includes:

identifying rising edges or falling edges respectively corresponding to the low-frequency reference clock and the frequency division clock to be calibrated;

Determining a phase deviation according to the rising edge or the falling edge; the low-frequency reference clock and the frequency division clock to be calibrated are the same in frequency.

In an embodiment, the adjusting the output clock frequency of the RTC real-time clock chip according to the phase deviation to obtain the frequency-calibrated frequency calibration clock includes:

Converting the phase deviation into a frequency deviation and converting the frequency deviation into a capacitance adjustment amount;

And adjusting the output clock frequency of the frequency division clock to be calibrated according to the capacitance adjustment quantity to obtain a frequency calibration clock after frequency calibration.

In an embodiment, the adjusting the output clock frequency of the frequency-division clock to be calibrated according to the capacitance adjustment amount to obtain the frequency-calibrated frequency-calibration clock includes:

Under the condition that the capacitance adjustment amount is increased, adjusting the output clock frequency of the frequency division clock to be calibrated to be a first output frequency to obtain a slow frequency calibration value; the first output frequency is the frequency at which the output frequency threshold reaches a first preset frequency threshold;

Under the condition that the capacitance adjustment amount is reduced, adjusting the output clock frequency of the frequency division clock to be calibrated to be a second output frequency to obtain a fast frequency calibration value; the second output frequency is the frequency at which the output frequency threshold reaches a second preset frequency threshold; the first preset frequency threshold is less than the second preset frequency threshold.

In an embodiment, the phase detection module outputs a first target frequency division calibration clock, in which the error reaches a preset error threshold, to the time module according to the error between the current frequency division calibration clock and the low frequency reference clock, including:

Comparing the current frequency division calibration clock with the low-frequency reference clock to obtain a comparison result; wherein the comparison result characterizes the magnitude of error between the current divided calibration clock and the low frequency reference clock;

And under the condition that the error magnitude does not reach a first target frequency division calibration clock with a preset error threshold, taking the current frequency division calibration clock as a next frequency division calibration clock, calculating the error between the next frequency division calibration clock and the low frequency reference clock, inputting the error into the adjustment module again, repeatedly executing the whole process until the error output by the phase discrimination module reaches the preset error threshold, and outputting the first target frequency division calibration clock with the error reaching the preset error threshold to the time module.

In an embodiment, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the invention. The electronic device 10 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Terminal devices may also represent various forms of mobile devices such as personal digital assistants, cellular telephones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the terminal device 10 can also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the terminal device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the RTC timing system.

In some embodiments, the RTC timing system may be implemented as a computer program, which is tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the terminal device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more of the steps of the RTC timing system described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the RTC timing system in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable RTC timing system, such that the computer programs, when executed by the processor, cause the functions/operations specified in the flowchart and/or block diagram to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a terminal device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the terminal device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. An RTC timing system, the system comprising: the device comprises a phase discrimination module, an adjustment module, a frequency division module and a time module;

the phase discrimination module is used for acquiring a low-frequency reference clock and a frequency division clock to be calibrated of the RTC real-time clock chip and determining phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated;

the adjusting module is used for adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation to obtain a frequency calibration clock after frequency calibration;

The frequency dividing module is used for dividing the frequency calibration clock to obtain a current frequency division calibration clock after frequency division, feeding the current frequency division calibration clock back to the phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency division calibration clock with the error reaching a preset error threshold to the time module according to the error between the current frequency division calibration clock and the low-frequency reference clock;

and the time module is used for carrying out time alignment on the first target frequency division calibration clock and the preset TOD time so as to obtain the time correction time after the frequency division clock to be calibrated is aligned.

2. The system of claim 1, wherein the system further comprises: a filtering module;

the filtering module is used for receiving the phase deviation transmitted by the phase discrimination module, performing low-pass filtering on the phase deviation to obtain a filtered phase deviation, and converting the phase deviation into a frequency deviation.

3. The system of claim 1, wherein the system further comprises: an interface module and a storage module;

The interface module is responsible for connecting an external upper computer and the message exchange of the storage module and is used for reading the current frequency division calibration clock transmitted by the adjustment module or a preset frequency calibration clock appointed by a user from the storage module;

The storage module is used for storing a preset temperature-frequency calibration relation curve, a current frequency division calibration clock and a preset frequency calibration clock.

4. The system of claim 3, wherein the interface module is further configured to:

a calendar and TOD times are preset.

5. The system of claim 3, wherein the adjustment module is further configured to:

Under the condition that no external transmission low-frequency reference clock is connected, a preset frequency calibration clock appointed by a user in the storage module is obtained, the output clock frequency of the RTC real-time clock chip is automatically adjusted according to the preset frequency calibration clock and a frequency division clock to be calibrated of the RTC real-time clock chip, the target calibration clock is fed back to the frequency division module, so that the frequency division module divides the target calibration clock to obtain a frequency-divided second target frequency division calibration clock, and the second target frequency division calibration clock is input into the time module for time alignment.

6. The system of claim 1, wherein the determining a phase offset between the low frequency reference clock and the divided clock to be calibrated comprises:

identifying rising edges or falling edges respectively corresponding to the low-frequency reference clock and the frequency division clock to be calibrated;

Determining a phase deviation according to the rising edge or the falling edge; the low-frequency reference clock and the frequency division clock to be calibrated are the same in frequency.

7. The system of claim 1, wherein adjusting the output clock frequency of the RTC real-time clock chip according to the phase deviation yields a frequency-calibrated frequency calibration clock, comprising:

Converting the phase deviation into a frequency deviation and converting the frequency deviation into a capacitance adjustment amount;

And adjusting the output clock frequency of the frequency division clock to be calibrated according to the capacitance adjustment quantity to obtain a frequency calibration clock after frequency calibration.

8. The system of claim 7, wherein adjusting the output clock frequency of the divided clock to be calibrated according to the capacitance adjustment amount to obtain the frequency-calibrated frequency calibration clock comprises:

Under the condition that the capacitance adjustment amount is increased, adjusting the output clock frequency of the frequency division clock to be calibrated to be a first output frequency to obtain a slow frequency calibration value; the first output frequency is the frequency at which the output frequency threshold reaches a first preset frequency threshold;

Under the condition that the capacitance adjustment amount is reduced, adjusting the output clock frequency of the frequency division clock to be calibrated to be a second output frequency to obtain a fast frequency calibration value; the second output frequency is the frequency at which the output frequency threshold reaches a second preset frequency threshold; the first preset frequency threshold is less than the second preset frequency threshold.

9. The system of claim 1, wherein the phase discrimination module outputs a first target divided calibration clock to the time module for which the error reaches a preset error threshold based on the error between the current divided calibration clock and the low frequency reference clock, comprising:

Comparing the current frequency division calibration clock with the low-frequency reference clock to obtain a comparison result; wherein the comparison result characterizes the magnitude of error between the current divided calibration clock and the low frequency reference clock;

And under the condition that the error magnitude does not reach a preset error threshold, taking the current frequency division calibration clock as a next frequency division calibration clock, calculating the error between the next frequency division calibration clock and the low frequency reference clock, inputting the error into the adjustment module again, repeatedly executing the whole process until the error output by the phase discrimination module reaches the preset error threshold, and outputting a first target frequency division calibration clock with the error reaching the preset error threshold to the time module.

10. An RTC timing method, applied to an RTC timing system, the method comprising:

acquiring a low-frequency reference clock and a frequency division clock to be calibrated of an RTC real-time clock chip through a phase discrimination module, and determining phase deviation between the low-frequency reference clock and the frequency division clock to be calibrated;

adjusting the output clock frequency of the frequency division clock to be calibrated according to the phase deviation by an adjusting module to obtain a frequency calibration value;

Dividing the frequency calibration value by a frequency dividing module to obtain a current frequency dividing calibration clock after frequency division, feeding back the current frequency dividing calibration clock to a phase discrimination module to form a closed-loop negative feedback adjustment loop, so that the phase discrimination module outputs a first target frequency dividing calibration clock with the error reaching a preset error threshold to a time module according to the error between the current frequency dividing calibration clock and the low-frequency reference clock;

and performing time alignment on the first target frequency division calibration clock and the preset TOD time through a time module to obtain the time alignment time of the frequency division clock to be calibrated after alignment.