CN117998850A - One-time programmable memory device, preparation method thereof and one-time editable memory unit - Google Patents
One-time programmable memory device, preparation method thereof and one-time editable memory unit Download PDFInfo
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Abstract
A single programmable memory device, a preparation method thereof and a single editable memory unit. The one-time programmable memory device includes a semiconductor substrate, a first insulating layer, and one-time programmable memory cells. The semiconductor substrate comprises a first doped region, a first insulating layer is arranged on the semiconductor substrate, and the one-time programmable memory unit is arranged on one side of the first insulating layer away from the semiconductor substrate. The one-time programmable memory cell includes a first electrode, a dielectric layer, and a second electrode, the first electrode being electrically connected to the first doped region. The resistive state of the dielectric layer includes an initial high resistance state and a low resistance state, the dielectric layer being configured to form a conductive filament upon application of a programming voltage to the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high resistance state to the low resistance state, the conductive filament causing the resistive state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage. The one-time programmable memory device has the advantages of low power consumption, high reliability, high integration level and the like.
Description
Technical Field
Embodiments of the present disclosure relate to a one-time programmable memory device, a method of manufacturing the same, and a one-time editable memory cell.
Background
One time programmable (One Time Programmable, OTP) devices are a type of Non-Volatile Memory (NVM) that only allows for one time programming, and once programmed, the data cannot be modified. In today where information security is increasingly important, OTP is increasingly important. OTP is widely used to store certain data that is high in security requirements and can be read repeatedly, such as: encryption information, startup procedures, and important configuration parameters, etc.
Disclosure of Invention
The embodiment of the disclosure provides a single-time programmable memory device, a preparation method thereof and a single-time editable memory unit. The one-time programmable memory cell of the one-time programmable memory device is located at a side of the first insulating layer away from the semiconductor substrate, and a resistance state of the one-time programmable memory cell is stabilized in a low configuration after a programming voltage is applied. Therefore, the one-time programmable memory device has the performance advantages of smaller size, lower cost, low power consumption, high reliability, high integration level and high speed, and has simpler preparation process and process flow.
At least one embodiment of the present disclosure provides a one-time programmable memory device including: a semiconductor substrate including a first doped region; a first insulating layer disposed on the semiconductor substrate; and a single-time programmable memory cell disposed on a side of the first insulating layer remote from the semiconductor substrate, the single-time programmable memory cell including a first electrode, a second electrode disposed on a side of the first electrode remote from the semiconductor substrate, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer being in direct contact with the first electrode and the second electrode, respectively, the first electrode being electrically connected to the first doped region, a resistance state of the dielectric layer including an initial high resistance state and a low resistance state, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistance state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causing the resistance state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
For example, in the one-time programmable memory device provided in an embodiment of the present disclosure, the ratio of the oxygen binding capacity of the first electrode to the oxygen binding capacity of the second electrode ranges from 1.0 to 1.2.
For example, in the one-time programmable memory device provided in an embodiment of the present disclosure, the material of the second electrode includes a metal a, and the material of the first electrode includes a nitride of the metal a.
For example, in one-time programmable memory devices provided by an embodiment of the present disclosure, the metal a includes one or more of hafnium, titanium, zirconium, lanthanum, tantalum, and aluminum.
For example, in the one-time programmable memory device provided in an embodiment of the present disclosure, a thickness of the dielectric layer is less than or equal to 5nm, and a ratio of a thickness of the second electrode to a thickness of the dielectric layer is greater than or equal to 10.
For example, in one embodiment of the disclosure, the one-time programmable memory device further includes a control transistor, the semiconductor substrate further includes a second doped region, the one-time programmable memory device further includes a gate electrode located between the semiconductor substrate and the first insulating layer, and the control transistor includes the first doped region, the second doped region, and the gate electrode.
For example, the one-time programmable memory device provided in an embodiment of the present disclosure further includes: an n-th metal interconnection layer positioned on one side of the first insulating layer away from the semiconductor substrate; and an n+1th insulating layer, which is located at one side of the n-th metal interconnection layer far away from the semiconductor substrate, wherein the one-time programmable memory cell is located in the n+1th insulating layer, and a first electrode of the one-time programmable memory cell is in contact connection with the n-th metal interconnection layer and is electrically connected with the first doped region through the n-th metal interconnection layer, and n is a positive integer greater than or equal to 1.
For example, in the one-time programmable memory device provided in an embodiment of the present disclosure, the n+1-th insulating layer includes a dielectric barrier layer, the dielectric barrier layer is in contact with the n-th metal interconnection layer, the n-th metal interconnection layer includes a connection structure, the dielectric barrier layer includes a via, an orthographic projection of the via on the semiconductor substrate is located in an orthographic projection of the connection structure on the semiconductor substrate, and the first electrode is located in the via to be in contact with the connection structure, and a surface of a side of the first electrode away from the semiconductor substrate is flush with a surface of a side of the dielectric barrier layer away from the semiconductor substrate.
For example, in an one-time programmable memory device provided by an embodiment of the present disclosure, an orthographic projection of the first electrode on the semiconductor substrate is located within an orthographic projection of the dielectric layer on the semiconductor substrate.
At least one embodiment of the present disclosure provides a method for manufacturing a one-time programmable memory device, including: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; and forming a one-time programmable memory cell on a side of the first insulating layer away from the semiconductor substrate, the one-time programmable memory cell including a first electrode, a second electrode on a side of the first electrode away from the semiconductor substrate, and a dielectric layer between the first electrode and the second electrode, the resistive state of the dielectric layer including an initial high resistance state and a low resistance state, the semiconductor substrate including a first doped region, the first electrode being electrically connected to the first doped region, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causing the resistive state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
For example, in the preparation method provided in an embodiment of the present disclosure, the ratio of the oxygen binding capacity of the first electrode to the oxygen binding capacity of the second electrode ranges from 1.0 to 1.2.
For example, in the preparation method provided in an embodiment of the present disclosure, the material of the second electrode includes a metal a, and the material of the first electrode includes a nitride of the metal a, where the metal a includes one or more of hafnium, titanium, zirconium, lanthanum, tantalum, and aluminum.
For example, the preparation method provided in an embodiment of the present disclosure further includes: forming an n-th metal interconnection layer on a side of the first insulating layer away from the semiconductor substrate, wherein forming the one-time programmable memory cell on the side of the first insulating layer away from the semiconductor substrate comprises: and forming the one-time programmable memory cell on one side of the n-th metal interconnection layer far away from the semiconductor substrate, wherein a first electrode of the one-time programmable memory cell is in contact connection with the n-th metal interconnection layer and is electrically connected with the first doped region through the n-th metal interconnection layer, and n is a positive integer greater than or equal to 1.
For example, the preparation method provided in an embodiment of the present disclosure further includes: forming an n+1 insulating layer on one side of the n metal interconnection layer far away from the semiconductor substrate, wherein the n+1 insulating layer comprises a dielectric barrier layer, the dielectric barrier layer is in contact with the n metal interconnection layer, the n metal interconnection layer comprises a connection structure, the dielectric barrier layer comprises a via hole, the orthographic projection of the via hole on the semiconductor substrate is positioned in the orthographic projection of the connection structure on the semiconductor substrate, and the forming the one-time programmable memory unit on one side of the n metal interconnection layer far away from the semiconductor substrate comprises: a first electrode is formed within the via.
For example, in the method for manufacturing the one-time programmable memory cell according to an embodiment of the present disclosure, the forming the one-time programmable memory cell on a side of the nth metal interconnection layer away from the semiconductor substrate further includes: forming the dielectric material layer on one side of the first electrode away from the connection structure; forming the second electrode material layer on one side of the dielectric material layer away from the first electrode; and patterning the dielectric material layer and the second electrode material layer to form the dielectric layer and the second electrode.
At least one embodiment of the present disclosure provides a one-time programmable memory cell including: a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer being in direct contact with the first electrode and the second electrode, respectively, the resistive state of the dielectric layer comprising an initial high resistance state and a low resistance state, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causing the resistive state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
FIG. 1 is a schematic diagram of a one-time programmable memory device according to an embodiment of the present disclosure;
FIG. 2 is a programming graph of a one-time programmable memory device provided in an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another one-time programmable memory device according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a single-time programmable memory cell according to an embodiment of the present disclosure;
FIG. 5 is a flowchart of a method for manufacturing a one-time programmable memory device according to an embodiment of the present disclosure; and
Fig. 6 to 9 are flowcharts of a method for manufacturing an otp memory cell of an otp memory device according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, features such as "parallel", "perpendicular" and "identical" as used in the embodiments of the present disclosure include cases where "parallel", "perpendicular", "identical" and the like are in strict sense, and cases where "substantially parallel", "substantially perpendicular", "substantially identical" and the like include certain errors. For example, the above-described "approximately" may indicate that the difference of the compared objects is within 10%, or 5%, of the average value of the compared objects. Where the number of a component or element is not specifically indicated in the following description of embodiments of the present disclosure, it means that the component or element may be one or more or may be understood as at least one. "at least one" means one or more, and "a plurality" means at least two. The "same layer arrangement" in the embodiments of the present disclosure refers to a relationship between multiple film layers formed of the same material after the same step (e.g., one-step patterning process). The term "same layer" herein does not always mean that the thickness of the plurality of film layers is the same or that the heights of the plurality of film layers are the same in the cross-sectional view.
There are two types of OTP devices, one of which adopts an electronic fuse (eFuse) technology, which does not require an additional programmer, and which presents a low resistance state when data is not written in the factory, and the programming process is to apply a high-density current to a metal gate or a polysilicon gate by using a voltage higher than a certain threshold, and to electrically fuse the low-resistance metal by passing the high-density current, so that the low-resistance metal presents a high resistance state. The second is to use antifuse (Antifuse) technology, the fuse is composed of two metal electrodes and an antifuse dielectric layer between the metal electrodes, which presents a high resistance state when no data is written, and to apply a high voltage to the thin gate oxide when programming, the antifuse dielectric turns on, and the device changes from a high resistance state to a low resistance state.
Table 1 shows a comparison of performance metrics for two OTP devices
As shown in table 1, the eFuse OTP is blown by a thermal effect at a narrow middle metal gate or polysilicon gate after writing data due to a unique programming mechanism, and its programming node can be observed by an electron microscope, so that the stored content is easily broken, and the security is poor. In addition, with the development of advanced processes and the application of High-K materials, most eFuse OTPs are now changed to High-K metal materials, and fuse fragments generated in the programming process can grow reversely, which eventually leads to device failure. In addition, the eFuse OTP has a structure with two wide sides and a narrow middle part, and the larger areas at the two ends form larger temperature gradient with the middle part for heat dissipation on one hand, and the larger ends at the two ends occupy larger area for interconnection with the outside on the other hand, so that the area of the device is large, and the eFuse OTP cannot be miniaturized along with the size of a transistor, and the integration level is reduced. Finally, since the eFuse OTP is in a low resistance state when not programmed, this results in its quiescent power consumption becoming very high.
As shown in table 1, antifuse OTP including two transistors (2T) is taken as an example, since two transistors of 2T Antifuse OTP need to be formed on a semiconductor substrate, the area occupied by Antifuse OTP is large, and 2T Antifuse OTP has a problem that voltage stress is large on a control transistor after a gate dielectric of the control transistor is broken down, failure of the control transistor is easily caused, and reliability of Antifuse OTP is reduced.
The embodiment of the disclosure provides a one-time programmable memory device and a preparation method thereof. The one-time programmable memory device includes a semiconductor substrate, a first insulating layer, and one-time programmable memory cells. The semiconductor substrate comprises a first doped region, a first insulating layer is arranged on the semiconductor substrate, and the one-time programmable memory unit is arranged on one side of the first insulating layer away from the semiconductor substrate. The one-time programmable memory cell includes a first electrode, a second electrode located on a side of the first electrode remote from the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. The dielectric layer is in direct contact with the first electrode and the second electrode, respectively, and the first electrode is electrically connected with the first doped region. The resistive state of the dielectric layer includes an initial high resistance state and a low resistance state, the dielectric layer is configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causes the resistive state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causes the resistive state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
In the otp memory device provided in the embodiments of the present disclosure, the otp memory cell is disposed on a side of the first insulating layer away from the semiconductor substrate, that is, the otp memory cell may be integrated on a side of the first insulating layer away from the semiconductor substrate. On the one hand, the one-time programmable memory unit does not occupy the area of the semiconductor substrate, so that the one-time programmable memory device has smaller size, meets the layout requirement in a narrow space, and can reduce the cost of the one-time programmable memory device; on the other hand, the one-time programmable memory cell can be formed in a Back-End of Line (BEOL) of an integrated circuit manufacturing process, can be compatible with the integrated circuit manufacturing process, has the performance advantage of high integration level, and enables the preparation process and the process flow of the one-time programmable memory cell to be simpler.
In the one-time programmable memory cell, the resistance of the dielectric layer in the initial state is in a high resistance state, and after a programming voltage is applied between the first electrode and the second electrode, the programming voltage breaks down the dielectric layer, namely the breakdown voltage of the dielectric layer, at this time, a plurality of conductive channels which are mainly formed by oxygen ion vacancies are formed in the dielectric layer, and the conductive channels are also called conductive filaments (Conductive Filament, CF), and the existence of the conductive filaments changes the resistance state of the dielectric layer from the initial high resistance state to the low resistance state. Then, after the reverse programming voltage is applied between the first electrode and the second electrode, the conductive filaments of the dielectric layer are not fused, and at the moment, the conductive filaments of the dielectric layer are not fused under the action of the forward electric field and the reverse electric field with different intensities. Thus, the otp memory cell can no longer be erased to the initial high resistance state after the otp memory cell is programmed once into the low resistance state, and the otp memory cell can be programmed once. The one-time programmable memory cell is in a low-resistance state after one-time programming, so that the one-time programmable memory device has the performance advantages of low power consumption, high speed, difficult cracking and the like.
Hereinafter, a one-time programmable memory device and a method of manufacturing the same according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Embodiments of the present disclosure provide a one-time programmable memory device. Fig. 1 is a schematic structural diagram of a one-time programmable memory device according to an embodiment of the disclosure. As shown in fig. 1, the one-time programmable memory device 100 includes a semiconductor substrate 110, a first insulating layer 120, and one-time programmable memory cells 130. The semiconductor substrate 110 includes a first doped region 111, a first insulating layer 120 is disposed on the semiconductor substrate 110, and the otp memory cell 130 is disposed on a side of the first insulating layer 120 away from the semiconductor substrate 110. The otp memory cell 130 includes a first electrode 131, a second electrode 133 located at a side of the first electrode 131 remote from the semiconductor substrate 110, and a dielectric layer 132 located between the first electrode 131 and the second electrode 133. The dielectric layer 132 is in direct contact with the first electrode 131 and the second electrode 133, respectively, and the first electrode 131 is electrically connected to the first doped region 111. The resistive state of the dielectric layer 132 includes an initial high-resistance state and a low-resistance state, the dielectric layer 132 is configured to form a conductive filament after a programming voltage is applied between the first electrode 131 and the second electrode 133, the conductive filament causes the resistive state of the dielectric layer 132 to change from the initial high-resistance state to the low-resistance state, and then the conductive filament causes the resistive state of the dielectric layer 132 to remain in the low-resistance state after a reverse programming voltage is applied between the first electrode 131 and the second electrode 133.
In the otp memory device 100 provided in the embodiments of the present disclosure, the otp memory cell 130 is disposed on a side of the first insulating layer 120 away from the semiconductor substrate 110, that is, the otp memory cell 130 may be integrated on a side of the first insulating layer 120 away from the semiconductor substrate 110. By such arrangement, on the one hand, the otp memory cell 130 does not occupy the area of the semiconductor substrate 110, so that the otp memory device 100 has a smaller size, meets the layout requirement in a narrow space, and reduces the cost of the otp memory device 100; on the other hand, the otp memory 130 may be formed in a Back-End of Line (BEOL) process of an integrated circuit manufacturing process, may be compatible with the integrated circuit manufacturing process, has a performance advantage of high integration, and makes a manufacturing process and a process flow of the otp memory 130 simpler.
In the otp memory cell 130, the resistance of the dielectric layer 132 in the initial state is in a high resistance state, and after a programming voltage is applied between the first electrode 131 and the second electrode 133, the dielectric layer 132 is broken down by the programming voltage, that is, the breakdown voltage of the dielectric layer 132, at this time, a plurality of conductive channels dominated by oxygen ion vacancies, which are also called conductive filaments (Conductive Filament, CF), are formed in the dielectric layer 132, and the presence of the conductive filaments changes the resistance state of the dielectric layer 132 from the initial high resistance state to the low resistance state. Then, after the reverse programming voltage is applied between the first electrode 131 and the second electrode 133, the conductive filaments of the dielectric layer 132 are not fused, and at this time, the conductive filaments of the dielectric layer 132 are not fused under the action of the forward electric field and the reverse electric field of different intensities. Thus, the otp memory 130 can no longer be erased to the initial high-resistance state after the otp memory 130 is programmed to the low-resistance state, and the otp memory 130 can be programmed once. The otp memory cell 130 is in a low resistance state after a single program, so the otp memory device 100 has the performance advantage of low power consumption, and in addition, the otp memory device 100 has the performance advantages of high speed and not easy to crack.
In some examples, the ratio of the oxygen binding capacity of the first electrode 131 to the oxygen binding capacity of the second electrode 133 ranges from 1.0 to 1.2. The close or more approximate oxygen binding capacity of the first electrode 131 and the oxygen binding capacity of the second electrode 133 may make the formed conductive filament more stable, so that the conductive filament may not be fused under the action of the forward electric field and the reverse electric field with different intensities, and further, the otp memory 130 may implement otp. For example, the oxygen binding capacity of the first electrode 131 may be the same as the oxygen binding capacity of the second electrode 133.
In some examples, the material of the second electrode 133 includes a metal a, and the material of the first electrode 131 includes a nitride of the metal a. When the material of the second electrode 133 is metal, the oxygen binding capacity of the second electrode 133 is relatively strong, and thus, the conductive filaments formed by the dielectric layer 132 may be more stable after a program voltage is applied between the first electrode 131 and the second electrode 133. In addition, when the material of the second electrode 133 is metal, since the oxygen binding capacity of the second electrode 133 is relatively strong, the programming voltage may be lower, and on the one hand, the lower programming voltage may reduce the influence on the transistor formed in the semiconductor substrate 110, improving the reliability of the otp memory device 100. On the other hand, lower programming voltages may allow the otp memory cell 130 to be compatible with more advanced logic process platforms.
For example, the one-time programmable memory cell 130 has a programming voltage less than 4V. For example, the one-time programmable memory cell 130 has a programming voltage less than 3V. For example, the one-time programmable memory cell 130 has a programming voltage less than 2V.
In some examples, the metal a includes one or more of hafnium (Hf), titanium (Ti), zirconium (Zr), lanthanum (La), tantalum (Ta), aluminum (Al). The metals hafnium (Hf), titanium (Ti), zirconium (Zr), lanthanum (La), tantalum (Ta), aluminum (Al) have a strong oxygen binding capability, so that not only the conductive filaments formed by the dielectric layer 132 may be more stable, but also the programming voltage may be lower, and the reliability of the one-time programmable memory device 100 is improved. Of course, the metal material of the second electrode 133 is not particularly limited in the embodiment of the present disclosure, and may be other metals having a high oxygen binding ability.
For example, the second electrode 133 may be tantalum (Ta), and the first electrode 131 is tantalum nitride (TaN). For example, the second electrode 133 may be titanium (Ti), and the first electrode 131 is titanium nitride (TiN).
In some examples, the material of the dielectric layer 132 may be hafnium oxide (HfOx), tantalum oxide (TaOx), zirconium oxide (ZrOx).
In some examples, as shown in fig. 1, the first electrode 131 may be tantalum nitride (TaN), the dielectric layer 132 may be hafnium oxide (HfOx), and the second electrode 133 may be tantalum (Ta). In this example, it was verified through experiments that since the second electrode 133 and the first electrode 131 have high and similar oxygen binding capacity, after the second electrode 133 and the first electrode 131 are in direct contact with the dielectric layer 132 and a program voltage is applied, stable conductive filaments are formed in the dielectric layer 132, and the formed conductive filaments are not fused with a change in a voltage state, and a resistance state of the dielectric layer 132 is maintained in a low resistance state, whereby one-time programmable can be realized.
In some examples, as shown in fig. 1, the thickness of the dielectric layer 132 is less than or equal to 5nm. For example, the thickness of the dielectric layer 132 is less than or equal to 4nm. For example, the thickness of the dielectric layer 132 is less than or equal to 3nm. The thinner the dielectric layer 132, the lower the programming voltage, so that the otp memory cell 130 can not only be programmed at the lower supply voltage required for advanced logic process platforms with better advanced process compatibility, but the lower programming voltage can also reduce the voltage stress on the transistor electrically connected to the otp memory cell 130, improving the reliability of the otp memory device 100.
In some examples, as shown in fig. 1, the ratio of the thickness of the second electrode 133 to the thickness of the dielectric layer 132 is greater than or equal to 10. For example, a ratio of the thickness of the second electrode 133 to the thickness of the dielectric layer 132 is greater than or equal to 15. The ratio of the thickness of the second electrode 133 to the thickness of the dielectric layer 132 is greater than or equal to 20.
In some examples, as shown in fig. 1, the thickness of the second electrode 133 is the same as or substantially the same as the thickness of the first electrode 131.
In some examples, as shown in fig. 1, the one-time programmable memory device 100 further includes a control transistor TFT. The semiconductor substrate 110 further includes a second doped region 112, and the one-time programmable memory device 100 further includes a gate 140 between the semiconductor substrate 110 and the first insulating layer 120, and the control transistor TFT includes the first doped region 111, the second doped region 112, and the gate 140. For example, a control transistor TFT is electrically connected to a one-time programmable memory cell 130 to form a one-time programmable memory device cell. Of course, the embodiments of the present disclosure are not limited in this regard and other configurations may be employed. The otp memory cell 130 has a low programming voltage, which reduces the voltage stress on the control transistor TFT electrically connected to the otp memory cell 130 and improves the reliability of the otp memory device 100.
For example, the otp memory device 100 may include a plurality of control transistors TFT, each of which is electrically connected to one otp memory cell 130, so that the otp memory device 100 may include a plurality of otp memory device cells arranged in an array.
For example, the first doped region 111 of the control transistor TFT may be the drain and the second doped region 112 may be the source, or vice versa. For example, the control transistor TFT may be a thin film transistor or a field effect transistor.
In some examples, as shown in fig. 1, the one-time programmable memory device 100 further includes an nth metal interconnect layer M (n) and an n+1th insulating layer IMD (n+1). The n-th metal interconnection layer M (n) is located at a side of the first insulating layer 120 remote from the semiconductor substrate 110, and the n+1th insulating layer IMD (n+1) is located at a side of the n-th metal interconnection layer M (n) remote from the semiconductor substrate 110. The otp memory 130 is located in the n+1th insulating layer IMD (n+1), and the first electrode 131 of the otp memory 130 is in contact with the n-th metal interconnection layer M (n) and is electrically connected to the first doped region 111 through the n-th metal interconnection layer M (n), where n is a positive integer greater than or equal to 1. The otp memory 130 can be connected to any metal interconnect layer in a subsequent process, and has a simple process flow and high process compatibility.
Note that fig. 1 schematically illustrates the first insulating layer 120 and the n-th metal interconnection layer M (n) located on the first insulating layer 120. For example, when n is equal to 1, the first insulating layer 120, i.e., IMD (1), the nth metal interconnect layer M (n) is the first metal interconnect layer. For example, when n is greater than 1, the metal interconnection layer between the first insulating layer 120 and the n-th metal interconnection layer M (n) is omitted, which is not shown, and the structure of the omitted metal interconnection layer is the same as that of the n-th metal interconnection layer M (n).
In some examples, as shown in fig. 1, the n+1th insulating layer IMD (n+1) includes a dielectric barrier layer 161, the dielectric barrier layer 161 being in contact with the n-th metal interconnect layer M (n). The n-th metal interconnect layer M (n) includes a connection structure 151, and the dielectric barrier 161 includes a via V1, the front projection of the via V1 on the semiconductor substrate 110 being located within the front projection of the connection structure 151 on the semiconductor substrate 110, i.e., the via V1 exposing the connection structure 151. The first electrode 131 is located in the via hole V1 to be in contact connection with the connection structure 151 of the n-th metal interconnection layer M (n). The contact connection of the first electrode 131 and the n-th metal interconnection layer M (n) can be achieved by the via hole V1 to the dielectric barrier 161.
For example, as shown in fig. 1, a surface of a side of the first electrode 131 away from the semiconductor substrate 110 is flush with a surface of a side of the dielectric barrier 161 away from the semiconductor substrate 110.
For example, as shown in fig. 1, the n+1th insulating layer IMD (n+1) further includes an isolation layer 162, where the isolation layer 162 is located on a side of the dielectric barrier layer 161 away from the n-th metal interconnection layer M (n), for example, the dielectric barrier layer 161 in the insulating layer is used to block diffusion of metal in the metal interconnection layer, and the isolation layer 162 is located between the two metal interconnection layers to play an isolated supporting role.
In some examples, as shown in fig. 1, the front projection of the first electrode 131 onto the semiconductor substrate 110 is located within the front projection of the dielectric layer 132 onto the semiconductor substrate 110. Of course, the embodiments of the present disclosure are not limited in this regard.
In some examples, as shown in fig. 1, metal connection lines are also included in each insulating layer for making electrical connection to conductive structures on both sides of the insulating layer.
For example, as shown in fig. 1, the metal connection line L1 in the first insulating layer 120 may realize an electrical connection between the first doped region 111 of the semiconductor substrate 110 and the first metal interconnection layer. For example, the metal connection line L2 in the n+1-th insulating layer IMD (n+1) may realize an electrical connection between the second electrode 133 of the one-time programmable memory cell 130 and the connection structure 151 of the n+1-th metal interconnection layer M (n+1).
In some examples, as shown in fig. 1, the one-time programmable memory device 100 further includes a Hard Mask (Hard Mask) layer 170, the Hard Mask layer 170 being located on a side of the second electrode 133 remote from the dielectric layer 132. The connection of the metal connection line L2 with the second electrode 133 may be achieved by etching the via hole V2 to the hard mask layer 170. In this example, the hard mask layer 170 may prevent the second electrode 133 from being over-etched in the etching process.
FIG. 2 is a programming graph of a one-time programmable memory device provided in an embodiment of the present disclosure. Fig. 2 (a) is a programming graph of the otp memory 100 according to an embodiment of the disclosure, and fig. 2 (b) is a programming graph of a resistive random access memory, as a comparison. As shown in fig. 2 (a), the resistance state of the dielectric layer 132 of the otp memory device 100 is in a low resistance state after the program voltage is applied, and the resistance of the dielectric layer 132 is not changed under the action of the forward electric field and the reverse electric field with different intensities. Thus, the otp memory 130 may be one-time programmable. As shown in fig. 2 (b), the resistance state of the resistive layer of the resistive memory is reversible after the voltage is changed, and the resistive memory can be repeatedly read and written for a plurality of times.
As shown in fig. 2 (a), the otp memory cell 130 has a programming voltage less than 3V and a lower programming voltage, so that the otp memory device 100 has better reliability and is compatible with more advanced logic process platforms.
Fig. 3 is a schematic structural diagram of another one-time programmable memory device according to an embodiment of the present disclosure. As shown in fig. 3, this embodiment differs from the embodiment shown in fig. 1 in that the side of the second electrode 133 remote from the dielectric layer 132 may also be provided with a third electrode 134. This embodiment has the same technical effects as the embodiment shown in fig. 1 and will not be described again here.
For example, the one-time programmable memory cell 130 includes a first electrode 131, a dielectric layer 132, a second electrode 133, and a third electrode 134. By applying a programming voltage between the third electrode 134 and the first electrode 131, a number of conductive channels, also called conductive filaments, dominated by oxygen ion vacancies are formed in the dielectric layer 132, the presence of which causes the resistive state of the dielectric layer 132 to change from an initial high-resistance state to a low-resistance state. Then, after the reverse programming voltage is applied between the first electrode 131 and the third electrode 134, the conductive filaments of the dielectric layer 132 are not fused, and at this time, the conductive filaments of the dielectric layer 132 are not fused under the action of the forward electric field and the reverse electric field with different intensities. Thus, the otp memory 130 can no longer be erased to the initial high-resistance state after the otp memory 130 is programmed to the low-resistance state, and the otp memory 130 can be programmed once.
The material, thickness, oxygen binding capacity, and other technical features or parameters of the first electrode, the dielectric layer, or the second electrode in this embodiment are the same as those described above, and will not be described in detail here.
For example, as shown in fig. 3, the first electrode 131 may be tantalum nitride (TaN), the dielectric layer 132 may be hafnium oxide (HfOx), the second electrode 133 may be tantalum (Ta), and the third electrode 134 may be titanium nitride (TiN). In this example, since the second electrode 133 and the first electrode 131 have high and similar oxygen binding capacity, the second electrode 133 and the first electrode 131 are in direct contact with the dielectric layer 132 and a program voltage is applied, stable conductive filaments are formed in the dielectric layer 132, and the formed conductive filaments are not fused with a change in a voltage state, and a resistance state of the dielectric layer 132 is maintained in a low resistance state, whereby one-time programmable can be realized.
The embodiment of the disclosure also provides a single-time editable storage unit. Fig. 4 is a schematic structural diagram of a one-time programmable memory cell according to an embodiment of the disclosure. As shown in fig. 4, the otp memory cell 130 includes a first electrode 131, a second electrode 133, and a dielectric layer 132 between the first electrode 131 and the second electrode 133, the dielectric layer 132 being in direct contact with the first electrode 131 and the second electrode 133, respectively. The resistive state of the dielectric layer 132 includes an initial high-resistance state and a low-resistance state, the dielectric layer 132 is configured to form a conductive filament after a programming voltage is applied between the first electrode 131 and the second electrode 133, the conductive filament causes the resistive state of the dielectric layer 132 to change from the initial high-resistance state to the low-resistance state, and then the conductive filament causes the resistive state of the dielectric layer 132 to remain in the low-resistance state after a reverse programming voltage is applied between the first electrode 131 and the second electrode 133.
In the otp memory cell 130, the resistance of the dielectric layer 132 in the initial state is in a high resistance state, and after a programming voltage is applied between the first electrode 131 and the second electrode 133, the dielectric layer 132 is broken down by the programming voltage, that is, the breakdown voltage of the dielectric layer 132, at this time, a plurality of conductive channels dominated by oxygen ion vacancies, which are also called conductive filaments (Conductive Filament, CF), are formed in the dielectric layer 132, and the presence of the conductive filaments changes the resistance state of the dielectric layer 132 from the initial high resistance state to the low resistance state. Then, after the reverse programming voltage is applied between the first electrode 131 and the second electrode 133, the conductive filaments of the dielectric layer 132 are not fused, and at this time, the conductive filaments of the dielectric layer 132 are not fused under the action of the forward electric field and the reverse electric field of different intensities. Thus, the otp memory 130 cannot be erased to the initial high-resistance state after the otp memory 130 is programmed to the low-resistance state once, and thus the otp memory 130 can be programmed once.
For example, the materials, thicknesses, oxygen binding capacities and other technical features or parameters of the first electrode 131, the dielectric layer 132 or the second electrode 133 of the otp memory 130 are described in detail above, and are not described in detail herein.
The embodiment of the disclosure also provides a preparation method of the one-time programmable memory device. Fig. 5 is a flowchart of a method for manufacturing a one-time programmable memory device according to an embodiment of the present disclosure. As shown in fig. 5, the preparation method comprises the following steps:
s01: providing a semiconductor substrate;
s02: forming a first insulating layer on a semiconductor substrate; and
S03: one-time programmable memory cells are formed on a side of the first insulating layer remote from the semiconductor substrate.
In the method of manufacturing, the one-time programmable memory cell includes a first electrode, a second electrode located at a side of the first electrode away from the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode, a resistance state of the dielectric layer including an initial high resistance state and a low resistance state, the semiconductor substrate including a first doped region, the first electrode being electrically connected to the first doped region, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistance state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causing the resistance state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
In the otp memory device provided in the embodiments of the present disclosure, the otp memory cell is disposed on a side of the first insulating layer away from the semiconductor substrate, that is, the otp memory cell may be integrated on a side of the first insulating layer away from the semiconductor substrate. On the one hand, the one-time programmable memory unit does not occupy the area of the semiconductor substrate, so that the one-time programmable memory device has smaller size, meets the layout requirement in a narrow space, and can reduce the cost of the one-time programmable memory device; on the other hand, the otp memory cell may be formed in a Back-End of Line (BEOL) process of an integrated circuit manufacturing process, and may be compatible with the integrated circuit manufacturing process, thereby making a process for manufacturing the otp memory cell and a process flow simpler.
The principles and performance advantages of otp memory cells are described in detail above and are not further described herein.
For example, the ratio of the oxygen binding capacity of the first electrode to the oxygen binding capacity of the second electrode can range from 1.0 to 1.2. For example, the material of the second electrode includes a metal a, the material of the first electrode includes a nitride of the metal a, and the metal a includes one or more of hafnium, titanium, zirconium, lanthanum, tantalum, and aluminum. The materials, thicknesses, oxygen binding capacities and other technical characteristics or parameters of the first electrode, the dielectric layer or the second electrode of the otp memory are the same as those described above, and are not described in detail herein.
In some examples, the method of preparing further comprises: an n-th metal interconnection layer is formed on a side of the first insulating layer remote from the semiconductor substrate. Forming the one-time programmable memory cell on a side of the first insulating layer away from the semiconductor substrate includes: and forming a one-time programmable memory cell on one side of the n-th metal interconnection layer away from the semiconductor substrate. The first electrode of the one-time programmable memory cell is in contact connection with the nth metal interconnection layer and is electrically connected with the first doped region through the nth metal interconnection layer, and n is a positive integer greater than or equal to 1. Therefore, the one-time programmable memory unit can be connected with any metal interconnection layer in the subsequent process, the process flow is simple, and the process compatibility is high.
In some examples, the method of preparing further comprises: an n+1-th insulating layer is formed on a side of the n-th metal interconnection layer remote from the semiconductor substrate. The n+1 insulating layer comprises a dielectric barrier layer, the dielectric barrier layer is in contact with the n metal interconnection layer, the n metal interconnection layer comprises a connection structure, the dielectric barrier layer comprises a via hole, and the orthographic projection of the via hole on the semiconductor substrate is positioned in the orthographic projection of the connection structure on the semiconductor substrate.
Forming the one-time programmable memory cell on a side of the nth metal interconnect layer remote from the semiconductor substrate includes: a first electrode is formed within the via.
In some examples, forming the one-time programmable memory cell on a side of the nth metal interconnect layer remote from the semiconductor substrate further comprises: forming a dielectric material layer on one side of the first electrode away from the connection structure; forming a second electrode material layer on one side of the dielectric material layer away from the first electrode; the dielectric material layer and the second electrode material layer are patterned to form a dielectric layer and a second electrode.
Fig. 6 to 9 are flowcharts of a method for manufacturing an otp memory cell of an otp memory device according to an embodiment of the disclosure. Fig. 6 to 9 omit the process steps before the nth metal interconnection layer M (n) and the structure thereof, and the integrated circuit manufacturing process at least includes a Front-End of Line (FEOL) and a Back-End of Line (BEOL), and fig. 6 to 9 are flowcharts for fabricating the one-time programmable memory cell in the Back-End of Line (BEOL).
As shown in fig. 6, a via hole V1 is formed in the dielectric barrier 161 using a patterning process to expose the connection structure 151 of the n-th metal interconnection layer M (n), and then the first electrode 131 is formed in the via hole V1.
For example, the primary patterning process may include photoresist formation, exposure, development, etching, etc., and will not be described herein.
For example, forming the first electrode 131 within the via hole V1 includes: a first electrode material layer is formed in the via hole V1 by a deposition method such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or sputtering, and the like, the first electrode material in the via hole V1 is retained by etching and/or mechanical polishing, such as Chemical Mechanical Polishing (CMP), and the like, and the material in other positions of the first electrode material layer is removed, and the first electrode material layer is planarized, thereby forming the first electrode 131 shown in the drawing. The surface of the side of the first electrode 131 remote from the semiconductor substrate 110 is flush with the surface of the side of the dielectric barrier 161 remote from the semiconductor substrate 110.
For example, as shown in fig. 7, after the first electrode 131 is formed, the manufacturing method further includes: a dielectric material layer 1320 is formed on a side of the first electrode 131 away from the connection structure 151 by deposition or sputtering; a second electrode material layer 1330 is formed on a side of the dielectric material layer 1320 away from the first electrode 131 by deposition or sputtering; a hard mask material layer 1700 is formed on a layer of the second electrode material layer 1330 remote from the dielectric material layer 1320 by deposition or sputtering, etc.
For example, as shown in fig. 8, the preparation method further includes: the dielectric material layer 1320, the second electrode material layer 1330, and the hard mask material layer 1700 are patterned to form the dielectric layer 132, the second electrode 133, and the hard mask layer 170. The otp memory cell 130 includes a first electrode 131, a dielectric layer 132, and a second electrode 133.
For example, the manufacturing method may not include forming the hard mask material layer 1700 and forming the hard mask layer 170.
For example, the dielectric material layer 1320, the second electrode material layer 1330, or the hard mask material layer 1700 may be formed by a deposition method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering, and the method for forming each material layer is not particularly limited in the embodiments of the present disclosure.
For example, as shown in fig. 9, after the one-time programmable memory cell 130 is formed, the method further includes: the isolation layer 162 and the metal connection line L2 are formed, and the n+1th metal interconnection layer M (n+1) is formed. For example, the metal connection line L2 may electrically connect the second electrode 133 with the n+1th metal interconnection layer M (n+1) of the upper layer. For example, the isolation layer 162 and the metal connection line L2 may be formed on the otp memory cell 130 using a damascene process.
The following points need to be described:
(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.
(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.
The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (16)
1. A one-time programmable memory device comprising:
A semiconductor substrate including a first doped region;
a first insulating layer disposed on the semiconductor substrate; and
One-time programmable memory unit arranged on one side of the first insulating layer away from the semiconductor substrate,
Wherein the one-time programmable memory cell comprises a first electrode, a second electrode positioned on one side of the first electrode far away from the semiconductor substrate, and a dielectric layer positioned between the first electrode and the second electrode, the dielectric layer is respectively in direct contact with the first electrode and the second electrode, the first electrode is electrically connected with the first doped region,
The resistive state of the dielectric layer includes an initial high-resistance state and a low-resistance state, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high-resistance state to the low-resistance state, and then the conductive filament causing the resistive state of the dielectric layer to remain in the low-resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
2. The one time programmable memory device of claim 1, wherein a ratio of the oxygen binding capacity of the first electrode to the oxygen binding capacity of the second electrode has a value in a range of 1.0-1.2.
3. The one-time programmable memory device of claim 2, wherein the material of the second electrode comprises metal a and the material of the first electrode comprises a nitride of metal a.
4. The one time programmable memory device of claim 3, wherein the metal a comprises one or more of hafnium, titanium, zirconium, lanthanum, tantalum, aluminum.
5. The one-time programmable memory device of any of claims 1-4, wherein a thickness of the dielectric layer is less than or equal to 5nm, and a ratio of a thickness of the second electrode to a thickness of the dielectric layer is greater than or equal to 10.
6. The one-time programmable memory device of any of claims 1-4, further comprising a control transistor,
Wherein the semiconductor substrate further comprises a second doped region, the otp memory device further comprises a gate electrode between the semiconductor substrate and the first insulating layer, and the control transistor comprises a first doped region, a second doped region, and a gate electrode.
7. The one-time programmable memory device of any of claims 1-4, further comprising:
an n-th metal interconnection layer positioned on one side of the first insulating layer away from the semiconductor substrate; and
An n+1 insulating layer located on a side of the n metal interconnection layer away from the semiconductor substrate,
The one-time programmable memory cell is located in the n+1th insulating layer, a first electrode of the one-time programmable memory cell is in contact connection with the n-th metal interconnection layer and is electrically connected with the first doped region through the n-th metal interconnection layer, and n is a positive integer greater than or equal to 1.
8. The one time programmable memory device of claim 7, wherein the n+1-th insulating layer comprises a dielectric barrier layer in contact with the n-th metal interconnect layer,
The n-th metal interconnection layer comprises a connection structure, the dielectric barrier layer comprises a via hole, the orthographic projection of the via hole on the semiconductor substrate is positioned in the orthographic projection of the connection structure on the semiconductor substrate, the first electrode is positioned in the via hole to be in contact connection with the connection structure,
The surface of the side, away from the semiconductor substrate, of the first electrode is flush with the surface of the side, away from the semiconductor substrate, of the dielectric barrier layer.
9. The one time programmable memory device of claim 8, wherein an orthographic projection of the first electrode on the semiconductor substrate is within an orthographic projection of the dielectric layer on the semiconductor substrate.
10. A method of fabricating a one-time programmable memory device, comprising:
Providing a semiconductor substrate;
forming a first insulating layer on the semiconductor substrate; and
A one-time programmable memory cell is formed on a side of the first insulating layer remote from the semiconductor substrate,
Wherein the one-time programmable memory cell comprises a first electrode, a second electrode positioned on one side of the first electrode far away from the semiconductor substrate, and a dielectric layer positioned between the first electrode and the second electrode, the resistance state of the dielectric layer comprises an initial high resistance state and a low resistance state, the semiconductor substrate comprises a first doped region, the first electrode is electrically connected with the first doped region,
The dielectric layer is configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high resistance state to the low resistance state, and then the conductive filament causing the resistive state of the dielectric layer to remain in the low resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
11. The production method according to claim 10, wherein a ratio of the oxygen binding capacity of the first electrode to the oxygen binding capacity of the second electrode ranges from 1.0 to 1.2.
12. The method of manufacturing of claim 10, wherein the material of the second electrode comprises a metal a and the material of the first electrode comprises a nitride of metal a, the metal a comprising one or more of hafnium, titanium, zirconium, lanthanum, tantalum, aluminum.
13. The production method according to any one of claims 10 to 12, further comprising:
An n-th metal interconnection layer is formed on a side of the first insulating layer away from the semiconductor substrate,
Wherein the forming the one-time programmable memory cell on the side of the first insulating layer away from the semiconductor substrate comprises:
forming the one-time programmable memory cell on a side of the nth metal interconnection layer away from the semiconductor substrate,
The first electrode of the one-time programmable memory cell is in contact connection with the n-th metal interconnection layer and is electrically connected with the first doped region through the n-th metal interconnection layer, and n is a positive integer greater than or equal to 1.
14. The method of manufacturing of claim 13, further comprising:
an n+1-th insulating layer is formed on a side of the n-th metal interconnection layer remote from the semiconductor substrate,
Wherein the n+1 insulating layer comprises a dielectric barrier layer, the dielectric barrier layer is contacted with the n metal interconnection layer, the n metal interconnection layer comprises a connection structure, the dielectric barrier layer comprises a via hole, the orthographic projection of the via hole on the semiconductor substrate is positioned in the orthographic projection of the connection structure on the semiconductor substrate,
The forming the one-time programmable memory cell on the side of the nth metal interconnection layer away from the semiconductor substrate comprises:
A first electrode is formed within the via.
15. The method of manufacturing of claim 14, wherein the forming the one-time programmable memory cell on a side of the nth metal interconnect layer remote from the semiconductor substrate further comprises:
forming the dielectric material layer on one side of the first electrode away from the connection structure;
forming the second electrode material layer on one side of the dielectric material layer away from the first electrode; and
The dielectric material layer and the second electrode material layer are patterned to form the dielectric layer and the second electrode.
16. A one-time programmable memory cell comprising: a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, the dielectric layer being in direct contact with the first electrode and the second electrode, respectively,
Wherein the resistive state of the dielectric layer comprises an initial high-resistance state and a low-resistance state, the dielectric layer being configured to form a conductive filament upon application of a programming voltage between the first electrode and the second electrode, the conductive filament causing the resistive state of the dielectric layer to change from the initial high-resistance state to the low-resistance state, and then the conductive filament causing the resistive state of the dielectric layer to remain in the low-resistance state upon application of a reverse programming voltage between the first electrode and the second electrode.
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