CN117998837A - Semiconductor structure, forming method thereof and memory - Google Patents

Abstract

The embodiment of the disclosure provides a semiconductor structure, a forming method thereof and a memory; wherein the method comprises the following steps: the device comprises first active areas arranged in an array along a first direction and a second direction, and second active areas positioned on at least one side of the periphery of each first active area; wherein one of the first active regions and an adjacent one of the second active regions form an active region group; in each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides; the first direction and the second direction intersect in a plane, and a plurality of active area groups are arrayed along the first direction and the second direction.

Description

Semiconductor structure, forming method thereof and memory

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a method of forming the same, and a memory.

Background

Currently, semiconductor structures are typically formed on the surface of the active region. In the prior art, the active regions are mostly arranged in a 6F ² or 4F ² arrangement mode, however, the arrangement mode can cause that the semiconductor structure formed on the surface of the active region is very difficult to be miniaturized, so that the formed semiconductor structure occupies a large area and has low integration level.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory.

In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising: the device comprises first active areas arranged in an array along a first direction and a second direction, and second active areas positioned on at least one side of the periphery of each first active area; wherein one of the first active regions and an adjacent one of the second active regions form an active region group; in each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides; the first direction and the second direction intersect in a plane; and a plurality of active area groups are arranged in an array along the first direction and the second direction.

In some embodiments, the second active region is located between two adjacent first active regions in an ith column of the first active regions arranged along the first direction, and the second active region is located between every two adjacent first active regions in the second direction, i is a positive even number or a positive odd number different from 0.

In some embodiments, along the first direction, a second active region located between two adjacent first active regions extends along the second direction or the first direction; along the second direction, a second active region located between each adjacent two of the first active regions extends along the first direction or the second direction.

In some embodiments, the second active regions extending in the first direction and/or the second direction are staggered in the first direction.

In some embodiments, the second active region in one of the active region groups is located on one side of the first active region along the first direction; the second active region extends in the first direction or the second direction.

In some embodiments, a plurality of rows of the first active regions arranged along the second direction are staggered in the first direction; the second active region in one of the active region groups is located on one side of the first active region along the first direction, and the second active region extends along the second direction or the first direction.

In some embodiments, the first active region in one of the active region groups and the second active region in the other active region group are disposed adjacent in the second direction in two of the active region groups adjacent in the second direction.

In some embodiments, a second active region in the active region group is located at one side of a first active region along the second direction, and the second active regions in two adjacent active region groups are adjacently arranged along the second direction; the second active region extends in the first direction or the second direction.

In some embodiments, the second active regions are staggered in the first direction.

In some embodiments, the second active region is L-shaped; the first active region in one of the active region groups is located within an overlapping region of projection regions of the second active region along the first direction and the second direction.

In some embodiments, in a row of the active granules sequentially arranged along the second direction, any two adjacent active granules are axisymmetric, centrosymmetric or identical in structure; and in a column of active granules sequentially arranged along the first direction, any two adjacent active granules are axisymmetric, centrosymmetric or identical in structure.

In some embodiments, any two adjacent rows of the active area groups sequentially arranged along the second direction are axisymmetric, centrosymmetric or identical in structure; any two adjacent columns of active area groups which are sequentially arranged along the first direction are axisymmetric, centrosymmetric or identical in structure.

In some embodiments, the semiconductor structure further comprises: a first transistor located in the first active region; the first transistor comprises a first source electrode, a first channel, a first drain electrode and a first grid electrode which are sequentially stacked from bottom to top along a third direction, wherein the first grid electrode surrounds the first channel; the first channel extends along the third direction; a first conductive line electrically connected to the first source electrode; a second conductive line electrically connected to the first gate electrode; the third direction intersects a plane in which the first direction and the second direction are located.

In some embodiments, the semiconductor structure further comprises: a second transistor located on a surface of the second active region; the second transistor comprises a second source electrode, a second drain electrode and a second grid electrode; the second grid electrode is electrically connected with the first drain electrode; a third conductive line electrically connected to the second source electrode; and a fourth conductive wire electrically connected to the second drain electrode.

In some embodiments, the semiconductor structure further comprises a first conductive pillar and a second conductive pillar; the first conductive post is connected between the second source electrode and the third conductive line; the second conductive pillar is connected between the second drain and the fourth conductive line.

In some embodiments, one of the active granules is used to form one memory cell; two adjacent memory cells can share the first conductive pillar and/or the second conductive pillar.

In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising:

Providing a substrate; forming first active areas arranged in an array along a first direction and a second direction and second active areas positioned on at least one side of the periphery of each first active area on the surface of the substrate; wherein one of the first active regions and an adjacent one of the second active regions form an active region group; in each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides; the first direction and the second direction intersect in a plane; and a plurality of active area groups are arranged in an array along the first direction and the second direction.

In a third aspect, embodiments of the present disclosure provide a memory, comprising: the semiconductor structure in the above embodiment.

In some embodiments, the memory comprises dynamic random access memory.

The embodiment of the disclosure provides a semiconductor structure, a forming method thereof and a memory, wherein the semiconductor structure comprises first active areas arranged in an array along a first direction and a second direction, and second active areas positioned on at least one side of the periphery of each first active area, and one first active area and one adjacent second active area form an active area group. Because one active area group can be used for forming one memory cell of the semiconductor structure, the space in the semiconductor structure is effectively utilized by reasonably arranging the position relation of the first active area and the second active area in the active area group, so that the occupied area of a plurality of formed memory cells can be reduced, and the integration level of the semiconductor structure is further improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 to 27 are schematic structural views of a semiconductor structure according to an embodiment of the present disclosure;

Fig. 28 is a schematic structural diagram of a memory cell according to an embodiment of the disclosure;

Fig. 29 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 30 to 34 are schematic structural views of a semiconductor structure in the process of forming the semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the substrate is defined as the third direction, ignoring the flatness of the top and bottom surfaces. In the directions of the top surface and the bottom surface of the substrate (i.e., the plane in which the substrate is located), two directions intersecting each other (e.g., perpendicular to each other) are defined, for example, the directions in which the first active region array is arranged may be defined as a first direction and a second direction, respectively, and the plane direction of the substrate may be determined based on the first direction and the second direction. In the embodiment of the disclosure, the first direction, the second direction and the third direction may be perpendicular to each other, and in other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiment of the disclosure, the first direction is defined as an X-axis direction, the second direction is defined as a Y-axis direction, and the third direction is defined as a Z-axis direction.

Embodiments of the present disclosure provide a semiconductor structure, comprising: the device comprises first active areas arranged in an array along a first direction and a second direction, and second active areas positioned on at least one side of the periphery of each first active area; wherein a first active region and an adjacent second active region form an active region group; in each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides.

In an embodiment of the present disclosure, the second active area being located on at least one side around the first active area means: the second active region may be located at one side of the first active region in the first direction or in the second direction, or the second active region may be located at both sides of the first active region in the first direction and the second direction.

It should be noted that, in other embodiments, the second active region may also be located on three sides of the first active region along the first direction and the second direction, or the second active region may also be located on four sides of the first active region along the first direction and the second direction.

In some embodiments, the shape of the projected area of the first active region along the third direction may be circular or elliptical, and the shape of the projected area of the second active region along the third direction may be elliptical, rectangular, L-shaped, arcuate, or other suitable shape.

In some embodiments, in each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides means that: the first active region has a dimension in the first direction that is smaller than a dimension in the first direction of the second active region, or the first active region has a dimension in the second direction that is smaller than a dimension in the second direction of the second active region.

In some embodiments, an active region group formed by the first active region and the second active region is used to form a memory cell of a semiconductor structure, and the first active region and the second active region may be used to form a transistor structure, respectively. The material of the first and second active regions may include a metal Oxide material, such as Indium gallium zinc Oxide (Indium Gallium Zinc Oxide, IGZO), indium Tin Oxide (ITO), tungsten Tin Oxide (Tungsten Tin Oxide, TTO), zinc Oxide, indium Oxide, titanium Oxide, tin Oxide, and the like. Because of the inherent characteristics (lower electron mobility) of the metal oxide semiconductor, when the materials of the first active region and the second active region are metal oxides, leakage currents of the first transistor and the second transistor which are positioned in the first active region and on the surface of the second active region can be reduced, so that the loss speed of charges on the storage capacitor is reduced, the data storage time of the semiconductor structure is prolonged, and the power consumption of the semiconductor structure is reduced.

According to the semiconductor structure provided by the embodiment of the disclosure, since one active area group can be used for forming one memory cell of the semiconductor structure, the space in the semiconductor structure is effectively utilized by reasonably distributing the position relation of the first active area and the second active area in the active area group, so that the occupied area of a plurality of formed memory cells can be reduced, and the integration level of the semiconductor structure is improved.

Fig. 1 to 27 are schematic structural views of a semiconductor structure according to an embodiment of the present disclosure, and the following describes the semiconductor structure according to the embodiment of the present disclosure in detail with reference to fig. 1 to 27.

In some embodiments, the second active region is located between two adjacent first active regions in an ith column of first active regions arranged along the first direction, and the second active region is located between each adjacent two first active regions in sequence along the second direction, i being a positive even number or a positive odd number other than 0.

As shown in fig. 1 to 6, the semiconductor structure 100 includes first active regions 101 arrayed in the X-axis direction and the Y-axis direction, a second active region 102 is located between two adjacent first active regions 101 in the 2 nd and 4 th columns of the first active regions 101 arrayed in the X-axis direction, and the second active region 102 is located between each adjacent two first active regions 101 in the Y-axis direction in turn, that is, the second active region 102 is located on one side of the first active regions 101 in the X-axis direction or in the Y-axis direction. A first active region 101 and an adjacent second active region 102 form an active area group 10; in each active area group 10, the projections of the first active area 101 and the second active area 102 in the X-axis direction or the Y-axis direction at least partially coincide.

In some embodiments, a second active region located between two adjacent first active regions extends in a second direction or first direction along the first direction; along the second direction, the second active region located between each adjacent two of the first active regions extends along the first direction or the second direction.

With continued reference to fig. 1-4, along the X-axis direction, the second active region 102 located between two adjacent first active regions 101 extends along the Y-axis direction (as shown in fig. 1 and 4) or along the X-axis direction (as shown in fig. 2 and 3); along the Y-axis direction, the second active regions 102 located between every adjacent two of the first active regions 101 extend along the X-axis direction (as shown in fig. 1 and 3) or along the Y-axis direction (as shown in fig. 2 and 4).

Next, the extending direction of the second active region 102 is described with reference to fig. 1. As shown in fig. 1, if the dimension D1 of the second active region 102 in the Y-axis direction in one active region group 10 is greater than the dimension D2 of the first active region 101 in the Y-axis direction, then the Y-axis direction is taken as the extending direction of the second active region 102. If the dimension D3 of the second active region 102 in the X-axis direction in one active region group 10 is greater than the dimension D4 of the first active region 101 in the X-axis direction, the X-axis direction is taken as the extending direction of the second active region 102. That is, in the embodiment of the present disclosure, the dimension of the second active region 102 in the extending direction thereof is larger than the dimension of the first active region 101 in the extending direction thereof, and thus, the extending direction of the second active region 102 is the direction in which it has the largest dimension, that is, the direction in which the second active region 102 has the largest dimension is the extending direction thereof.

It should be noted that, in fig. 2 to 19 in the embodiments of the present disclosure, it is understood that the second active region has the direction of the maximum size as the extending direction thereof, and the explanation will not be further described.

In some embodiments, the second active regions extending in the first direction and/or the second direction are staggered in the first direction.

With continued reference to fig. 1, the second active regions 102 extending along the X-axis direction are staggered in the X-axis direction to form the semiconductor structure 100 shown in fig. 5. With continued reference to fig. 2, the second active regions 102 extending along the Y-axis direction are staggered in the X-axis direction to form the semiconductor structure 100 shown in fig. 6.

In some embodiments, as shown in fig. 7, the semiconductor structure 100 includes a first active region 101 arranged in an array along an X-axis direction and a Y-axis direction, and a second active region 102 located at one side of the first active region 101 along the X-axis direction and the Y-axis direction; the second active region 102 is located between each adjacent two of the first active regions 101 in sequence along the X-axis direction, and the second active region 102 is located between each adjacent two of the first active regions 101 in sequence along the Y-axis direction. Along the X-axis direction, the second active regions 102 located between every two adjacent first active regions 101 extend along the Y-axis direction; along the Y-axis direction, the second active regions 102 located between every adjacent two of the first active regions 101 extend along the X-axis direction.

With continued reference to fig. 7, a first active area 101 and an adjacent second active area 102 form an active area set 10; in each active area group 10, the projections of the first active area 101 and the second active area 102 in the X-axis direction or the Y-axis direction at least partially coincide.

With continued reference to fig. 1, the second active regions 102 extending along the X-axis direction and the Y-axis direction are staggered in the Y-axis direction and the X-axis direction, so as to form the semiconductor structure 100 shown in fig. 7.

In some embodiments, the second active region in one active region group is located on one side of the first active region in the first direction; the second active region extends in the first direction or the second direction.

As shown in fig. 8 and 9, the semiconductor structure 100 includes a first active region 101 arranged in an array along an X-axis direction and a Y-axis direction, and a second active region 102 is located at one side of the first active region 101 along the X-axis direction. A first active region 101 and a second active region 102 adjacent in the X-axis direction constitute an active area group 10, and the second active region 102 extends in the X-axis direction (as shown in fig. 9) or the Y-axis direction (as shown in fig. 8).

With continued reference to fig. 8 and 9, in each active area group 10, the projections of the first active area 101 and the second active area 102 along the X-axis direction at least partially coincide.

In some embodiments, a plurality of rows of the first active regions arranged along the second direction are staggered in the first direction; the second active region in one active region group is positioned at one side of the first active region along the first direction, and the second active region extends along the second direction or the first direction.

As shown in fig. 10 to 13, the semiconductor structure 100 includes first active regions 101 arranged in an array along an X-axis direction and a Y-axis direction, wherein a plurality of rows of the first active regions 101 are arranged along the Y-axis direction to be staggered in the X-axis direction. The second active region 102 is located at one side of the first active region 101 in the X-axis direction. A first active region 101 and a second active region 102 adjacent in the X-axis direction constitute an active area group 10. The plurality of active area groups 10 are arrayed in the X-axis direction and the Y-axis direction.

The second active region 102 extends in the X-axis direction (as shown in fig. 13) or the Y-axis direction (as shown in fig. 10 to 12).

With continued reference to fig. 10-13, in each active area group 10, the projections of the first active area 101 and the second active area 102 in the X-axis direction at least partially overlap.

In some embodiments, a first active region in one active region group is disposed adjacent to a second active region in the other active region group in a second direction in two active region groups adjacent in the second direction.

As shown in fig. 14 and 15, the semiconductor structure 100 includes first active regions 101 arranged in an array along an X-axis direction and a Y-axis direction, wherein a plurality of rows of the first active regions 101 are arranged along the Y-axis direction to be staggered in the X-axis direction. The second active region 102 is located at one side of the first active region 101 in the X-axis direction. A first active region 101 and a second active region 102 adjacent in the X-axis direction constitute an active area group 10. The plurality of active area groups 10 are arrayed in the X-axis direction and the Y-axis direction. Of the two active area groups 10 adjacent in the Y-axis direction, a first active area 101 in one active area group 10 is disposed adjacent to a second active area 102 in the other active area group 10 in the Y-axis direction. The second active region 102 extends in the X-axis direction (as shown in fig. 15) or the Y-axis direction (as shown in fig. 14).

With continued reference to fig. 14 and 15, in each active area group 10, the projections of the first active area 101 and the second active area 102 in the X-axis direction at least partially coincide.

In some embodiments, the second active region in the active region group is located at one side of the first active region along the second direction, and the second active regions in each adjacent two active region groups in turn along the second direction are adjacently disposed; the second active region extends in the first direction or the second direction.

As shown in fig. 16 and 17, the semiconductor structure 100 includes a first active region 101 arranged in an array along an X-axis direction and a Y-axis direction, and a second active region 102 is located at one side of the first active region 101 along the Y-axis direction. A first active region 101 and a second active region 102 adjacent in the Y-axis direction constitute an active area group 10. The plurality of active area groups 10 are arrayed in the X-axis direction and the Y-axis direction. The second active area 102 in the active area group 10 is positioned at one side of the first active area 101 along the Y-axis direction, and the second active areas 102 in every two adjacent active area groups 10 in turn along the Y-axis direction are adjacently arranged; the second active region 102 extends in the X-axis direction (as shown in fig. 16) or the Y-axis direction (as shown in fig. 17).

With continued reference to fig. 16 and 17, in each active area group 10, the projections of the first active area 101 and the second active area 102 in the Y-axis direction at least partially coincide.

In some embodiments, the second active regions are staggered in the first direction.

As shown in fig. 18 and 19, the semiconductor structure 100 includes a first active region 101 arranged in an array along an X-axis direction and a Y-axis direction, and a second active region 102 is located at one side of the first active region 101 along the Y-axis direction. A first active region 101 and a second active region 102 adjacent in the Y-axis direction constitute an active area group 10. The second active area 102 in the active area group 10 is positioned at one side of the first active area 101 along the Y-axis direction, and the second active areas 102 in every two adjacent active area groups 10 in turn along the Y-axis direction are adjacently arranged; the second active region 102 extends in the X-axis direction (as shown in fig. 18) or the Y-axis direction (as shown in fig. 19). The second active regions 102 are staggered in the X-axis direction.

With continued reference to fig. 18 and 19, in each active area group 10, the projections of the first active area 101 and the second active area 102 in the Y-axis direction at least partially coincide.

In some embodiments, the second active region is L-shaped; the first active region in one active region group is located within an overlapping region of projection regions of the second active region in the first direction and the second direction.

As shown in fig. 20 to 25, the semiconductor structure 100 includes first active regions 101 arrayed in the X-axis direction and the Y-axis direction, and second active regions 102 are located on both sides of the first active regions 101 in the Y-axis direction and the X-axis direction. One first active region 101 and one second active region 102 adjacent thereto constitute one active set 10. The second active region 102 is L-shaped, and the first active region 101 in one active region group 10 is located in an overlapping region of projection regions of the second active region 102 in the X-axis direction and the Y-axis direction.

In some embodiments, the active area groups are arranged in an array along a first direction and a second direction; in a row of active granules sequentially arranged along the second direction, any two adjacent active granules are axisymmetric, centrosymmetric or identical in structure; in a column of active granules sequentially arranged along the first direction, any two adjacent active granules are axisymmetric, centrosymmetric or identical in structure.

As shown in fig. 20 and 21, the active area groups 10 are arrayed in the X-axis direction and the Y-axis direction.

With continued reference to fig. 20, in a row of active granules 10 sequentially arranged along the Y-axis direction in the X-axis direction, any two adjacent active granules 10 are centrosymmetric; it should be noted that, the arrangement along the Y-axis direction refers to the arrangement direction of the active granules in one row of active granules, and not the arrangement direction of the active granules in multiple rows.

With continued reference to fig. 20, in a row of active granules 10 sequentially arranged along the X-axis direction, any two adjacent active granules 10 are centrosymmetric. It should be noted that, the arrangement along the X-axis direction refers to the arrangement direction of a plurality of active granules in one active granule, and not the arrangement direction of a plurality of active granules. The understanding of "arranged in the X-axis direction" and "arranged in the Y-axis direction" in subsequent fig. 21 to 25 is the same as that of fig. 20, and the description thereof will not be repeated.

With continued reference to fig. 21, in the odd-numbered active granules 10 sequentially arranged along the Y-axis direction, any two adjacent active granules 10 are centrosymmetric, and in the even-numbered active granules 10 sequentially arranged along the Y-axis direction, any two adjacent active granules 10 have the same structure; in the active area groups 10 of even columns sequentially arranged along the X-axis direction in the Y-axis direction, any two adjacent active area groups 10 are centrosymmetric, and in the active area groups 10 of odd columns sequentially arranged along the X-axis direction, any two adjacent active area groups 10 have the same structure.

In some embodiments, any two adjacent rows of active area groups sequentially arranged along the second direction are axisymmetric, centrosymmetric or identical in structure; any two adjacent active area groups sequentially arranged along the first direction are axisymmetric, centrosymmetric or identical in structure.

As shown in fig. 22 to 25, the active matrix groups 10 are arrayed in the X-axis direction and the Y-axis direction.

With continued reference to fig. 22, in the X-axis direction, the structures of any two rows of active area groups 10 sequentially arranged along the Y-axis direction are the same; in the Y-axis direction, any two adjacent active area groups 10 arranged along the X-axis direction are axisymmetric.

With continued reference to fig. 23, in the X-axis direction, any two rows of active area groups 10 sequentially arranged along the Y-axis direction are axisymmetric; in the Y-axis direction, any two adjacent active area groups 10 arranged along the X-axis direction are axisymmetric.

With continued reference to fig. 24, in the X-axis direction, any two rows of active area groups 10 sequentially arranged along the Y-axis direction have the same structure; in the Y-axis direction, any two adjacent rows of active area groups 10 arranged in the X-axis direction have the same structure.

With continued reference to fig. 25, in the X-axis direction, any two rows of active area groups 10 sequentially arranged along the Y-axis direction have the same structure; in the Y-axis direction, any two adjacent columns of active area groups 10 arranged in the X-axis direction are centrosymmetric.

In the embodiment of the disclosure, the space in the semiconductor structure is effectively utilized by reasonably distributing the position relation of the first active region and the second active region in the active region group, so that the occupied area of a plurality of formed memory cells can be reduced, and the integration level of the semiconductor structure is improved.

It should be noted that, in the embodiment of the present disclosure, only some typical layout structures of the first active area and the second active area are exemplified, and the layout structures of the first active area and the second active area in the embodiment of the present disclosure are not limited thereto, and are not exemplified herein.

In some embodiments, the semiconductor structure further comprises: a first transistor located in the first active region; the first transistor comprises a first source electrode, a first channel, a first drain electrode and a first grid electrode which are sequentially stacked from bottom to top along a third direction; the first channel extends in a third direction; a first conductive line electrically connected to the first source electrode; and the second conductive wire is electrically connected with the first grid electrode. Next, the semiconductor structure in the embodiments of the present disclosure may be described in further detail with reference to fig. 26 and 27.

Note that, in fig. 27, the first active region and the second active region are shown in a cross-sectional view, and only to illustrate specific structures of the first transistor and the second transistor and connection structures between the first transistor and the second transistor, with respect to the extending directions of the respective structures in fig. 27, please understand with reference to fig. 26, and fig. 27 is not used to explain the directions of the second transistor of the first transistor and the connection structures thereof.

Referring to fig. 26 and 27, the semiconductor structure 100 further includes: a first transistor 103 located in the first active region 101; the first transistor 103 includes a first source electrode 1031, a first channel 1032, a first drain electrode 1033, and a first gate electrode surrounding the first channel 1032, which are stacked in this order from bottom to top in the Z-axis direction; the first channel 1032 extends in the Z-axis direction.

In an embodiment of the present disclosure, the first gate includes a first gate dielectric layer 1034 surrounding the first channel 1032, and a first gate conductive layer (not shown) located on a surface of the first gate dielectric layer 1034.

With continued reference to fig. 26 and 27, the semiconductor structure 100 further includes: a first conductive line 105, the first conductive line 105 being electrically connected to the first source electrode 1031; the first conductive Line 105 may be a Write Bit Line (WBL) of a DRAM memory cell.

With continued reference to fig. 26 and 27, the semiconductor structure 100 further includes: and a second conductive line 106, the second conductive line 106 being electrically connected to the first gate electrode. In the disclosed embodiment, the second conductive Line 106 may be a Write Word Line (WWL) of a DRAM memory cell.

In some embodiments, the semiconductor structure further comprises: a second transistor located on the surface of the second active region; the second transistor comprises a second source electrode, a second drain electrode and a second grid electrode; the second grid electrode is electrically connected with the first drain electrode; a third conductive line electrically connected to the second source electrode; and the fourth conductive wire is electrically connected with the second drain electrode.

With continued reference to fig. 26 and 27, the semiconductor structure 100 further includes: a second transistor 104 located on the surface of the second active region 102; the second transistor 104 includes a second source (not shown), a second drain (not shown), and a second gate; the second gate is electrically connected to the first drain 1033. In other embodiments, the second gate may not be electrically connected to the first drain electrode 1033, and both the first transistor and the second transistor may form one storage unit separately.

With continued reference to fig. 26 and 27, the second gate includes a second gate dielectric layer 1041 disposed in the middle of the surface of the second active region 102, and a second gate conductive layer 1042 disposed on the surface of the second gate dielectric layer 1041. Wherein the second gate conductive layer 1042 extends along the X-axis direction.

In the embodiment of the present disclosure, the second gate conductive layer 1042 is electrically connected to the first drain electrode 1033, that is, the electrical connection between the first transistor 103 and the second transistor 104 is achieved through the second gate conductive layer. The second gate conductive layer 1042 may serve as a storage node contact (Storage Node Contact, SNC) of the DRAM memory cell.

With continued reference to fig. 26 and 27, the semiconductor structure 100 further includes: a third conductive line 107 and a fourth conductive line 108, a second source electrode is electrically connected to the third conductive line 107, and a second drain electrode is electrically connected to the fourth conductive line 108.

It should be noted that, for ease of understanding, only one first conductive structure 105, only one second conductive line 106, only one third conductive line 107, and only one fourth conductive line 108 are shown in fig. 26, and in fact, the first conductive structure 105, the second conductive line 106, the third conductive line 107, and the fourth conductive line 108 are formed in plural.

In the embodiment of the present disclosure, the third conductive Line 107 may be used as a Read Bit Line (RBL) of a DRAM memory cell, and the fourth conductive Line 108 may be used as a Read Word Line (RWL) of a DRAM memory cell.

In some embodiments, the material of the first gate dielectric layer 1034 and the second gate dielectric layer 1041 may be silicon oxide or other suitable material; the material of the first gate conductive layer and the second gate conductive layer 1042 may be any material with good conductivity, for example, any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu), or a combination thereof. The materials of the first conductive line 105, the second conductive line 106, the third conductive line 107, and the fourth conductive line 108 may include any one of tungsten, cobalt, copper, titanium, platinum, palladium, ruthenium, titanium nitride, tungsten nitride, or a combination thereof.

In the embodiment of the present disclosure, the first conductive line 105, the second conductive line 106, the second gate conductive layer 1042, the third conductive line 107, and the fourth conductive line 108 may be located at different layers in the Z-axis direction. Therefore, the coupling among the first conductive wire, the second grid electrode conductive layer, the third conductive wire and the fourth conductive wire can be reduced, the signal crosstalk is reduced, and the performance of the semiconductor structure is improved.

In the embodiment of the disclosure, since the first transistor is located inside the active region and the second transistor is located on the surface of the active region, the semiconductor structure formed by the first transistor and the second transistor in the embodiment of the disclosure has smaller area and higher integration.

In addition, in the embodiment of the present disclosure, one first transistor is electrically connected to one second transistor adjacent in the X-axis direction, and may constitute one memory cell, for example, a DRAM memory cell. Since the first transistor 103 is electrically connected to the second transistor 104 adjacent in the X-axis direction, the layout area of each memory cell can be further reduced, and the integration of the semiconductor structure can be further improved.

In some embodiments, referring to fig. 26 and 27, the semiconductor structure 100 further includes: a first conductive post 109 and a second conductive post 110; the first conductive pillar 109 is connected between the second source and the third conductive line 107; the second conductive pillar 110 is connected between the second drain and the fourth conductive line 108.

In the embodiment of the disclosure, the first conductive pillar 109 and the second conductive pillar 110 may be disposed in a staggered manner, so that a distance between the first conductive pillar 109 and the second gate conductive layer may be increased, and a coupling effect between the first conductive pillar and the second gate conductive layer may be reduced.

In some embodiments, two adjacent memory cells (i.e., two adjacent active area groups 10) can share a first conductive pillar and/or a second conductive pillar. Thus, the integration level of the semiconductor structure can be further improved.

With continued reference to fig. 26, the semiconductor structure 100 may further include a substrate 200. The first active region 101 and the second active region 102 are located on the surface of the substrate 200, wherein the substrate 200 may be a silicon substrate; the substrate 200 may also include other semiconductor elements, such as: germanium (Ge); or include semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), and the like; or include other semiconductor alloys such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or a combination thereof. The substrate may also be Silicon-on-insulator (Silicon On Insulator, SOI), silicon-germanium-on-insulator (Silicon-Germanium On Insulator, SGOI), or germanium-on-insulator (Germanium On Insulator, GOI).

With continued reference to fig. 26 and 27, the semiconductor structure 100 may further include an isolation layer 206 located on a surface of the substrate 200, where the first active region 101 and the second active region 102 are located on a surface of the isolation layer 206. The isolation layer 206 serves to prevent leakage of the first transistor 103 located in the first active region 101.

With continued reference to fig. 26, the semiconductor structure 100 further includes a first dielectric layer 209 between the first conductive pillars 109 and between the third conductive lines 107; and a second dielectric layer 210 located on the surface of the first dielectric layer 209 and between the second conductive pillars 110 and between the fourth conductive lines 108. The first dielectric layer 209 and the second dielectric layer 210 may be any kind of insulating layer, for example, a silicon oxide layer or a silicon oxynitride layer.

In some embodiments, the semiconductor structure may further include a first ohmic contact layer (not shown) between the first conductive pillar 109 and the second source electrode, and a second ohmic contact layer (not shown) between the second conductive pillar 110 and the second drain electrode, and the first ohmic contact layer and the second ohmic contact layer may be metal silicide layers.

In the embodiment of the disclosure, the first ohmic contact layer and the second ohmic contact layer are respectively used for reducing the contact resistance between the first conductive pillar and the second source electrode and between the second conductive pillar and the second drain electrode, so that the power consumption of the semiconductor structure is reduced.

Fig. 28 illustrates a schematic structure of a memory cell, which is only used to explain the working principle of the memory cell in the embodiments of the present disclosure. The first transistor 103 may be used as a writing transistor, the second transistor 104 may be used as a reading transistor, the gate of the second transistor 104 is connected to the drain of the first transistor 103, and the charge in the gate capacitor of the second transistor 104 is changed by the first transistor 103, so that the resistance state between the source and the drain of the second transistor 104 is affected, and the specific principle is as follows.

The write "1" process turns on the first transistor 103 and charges are injected into the gate capacitance of the second transistor 104 at the positive voltage applied to the first source of the first transistor 103 (i.e., the write bit line WBL). The gate and source voltages of the first transistor 103 are removed after the charge injection, preserving the "1" state.

In the process of reading "1", a read voltage is applied to the second drain electrode (i.e. the read bit line RBL) of the second transistor 104, and since a certain charge exists in the gate capacitor, the second transistor 104 is in a lower resistance state, a larger current is obtained, and the process of reading "1" is completed after the peripheral circuit is amplified and identified.

The write "0" process turns on the first transistor 103 and applies a negative voltage to the first source of the first transistor 103 (i.e., the write bit line WBL) to draw charge from the gate capacitance of the second transistor 104. The gate and source voltages of the first transistor 103 are removed after charge extraction, preserving the "0" state.

In the process of reading "0", a read voltage is applied to the second drain electrode (i.e. the read bit line RBL) of the second transistor 104, and since there is no charge in the gate capacitor, the second transistor 104 is in a higher resistance state, so as to obtain a smaller current, and then the process of reading "0" is completed after the peripheral circuit amplifies and recognizes.

In addition, an embodiment of the present disclosure further provides a method for forming a semiconductor structure, and fig. 29 is a schematic flow chart of the method for forming a semiconductor structure according to the embodiment of the present disclosure, as shown in fig. 29, the method for forming a semiconductor structure includes the following steps:

step S101, providing a substrate.

In step S102, first active regions arranged in an array along a first direction and a second direction and second active regions located on at least one side around each first active region are formed on the surface of the substrate.

Wherein a first active region and an adjacent second active region form an active region group; in each active area group, the projection of the first active area and the projection of the second active area in the first direction or the second direction at least partially coincide; the plurality of active area groups are arranged in an array along a first direction and a second direction.

Next, a specific formation process of the semiconductor structure (including the first active region and the second active region) will be described taking the semiconductor structure shown in fig. 14 as an example of the above embodiment.

Fig. 30 to 34 are schematic structural views during the formation of a semiconductor structure according to an embodiment of the present disclosure, and the formation of the semiconductor structure according to the embodiment of the present disclosure will be described in detail with reference to fig. 30 to 34. The left side of fig. 30 to 34 is a top view during the formation of the semiconductor structure, and the right side of fig. 30 to 34 is a cross-sectional view along b-b' of the left side of fig. 30 to 34.

In some embodiments, the active area group formed by the first active area and the second active area may be formed by two methods:

first kind: providing a substrate; a first isolation layer and an initial active region are formed on the surface of the substrate; patterning the initial active region to form an active stripe; and etching the active strips to form a first active region and a second active region.

As shown in fig. 30 and 31, the surface of the substrate 200 is formed with a first isolation layer 201 and an initial active region 203; patterning the initial active regions 203 to form active regions 204 arranged at intervals along the Y-axis direction, and first etching trenches 205 between two adjacent active regions 204; the active region 204 extends in the Y-axis direction. In practice, a photoresist layer is formed on the surface of the initial active region 203, and a photolithography process is performed to form an active region 204 and a first etching trench 205.

In the disclosed embodiment, the material of the initial active region 203 may be a metal oxide, for example, IGZO, ITO, and TTO.

As shown in fig. 30 and 31, the initial active region 203 is patterned to form active regions 204 arranged at intervals in the Y-axis direction, and first etched trenches 205 between adjacent two of the active regions 204; the active region 204 extends in the Y-axis direction. In practice, a photoresist layer is formed on the surface of the initial active region 203, and a photolithography process is performed to form an active region 204 and a first etching trench 205.

As shown in fig. 31 and 34, the active region 204 is etched to form a first active region 101 and a second active region 102, and a second etched trench (not shown) between the first active region 101 and the second active region 102. The dimension d1 of the first active region 101 in the Y-axis direction is smaller than the dimension d2 of the second active region 102 in the Y-axis direction.

In some embodiments, after forming the first active region 101 and the second active region 102, the method of forming a semiconductor structure further includes: an initial isolation structure 206a as shown in fig. 34 is formed in the first etched trench 205 and the second etched trench, wherein the initial isolation structure 206a includes a first isolation layer 201 on the surface of the substrate.

Second kind: providing a substrate; a first isolation layer and a second isolation layer are formed on the surface of the substrate; patterning the second isolation layer to form first grooves and second grooves alternately arranged at intervals along the first direction or the second direction; the size of the second groove in the first direction is larger than that of the first groove in the first direction, and the second groove extends along the first direction; and filling channel materials in the first groove and the second groove to form a first active region and a second active region respectively.

As shown in fig. 32 and 33, the substrate 200 is formed with a first isolation layer 201 and a second isolation layer 202 on the surface, the second isolation layer 202 is patterned, and first grooves 207 and second grooves 208 alternately arranged at intervals along the Y-axis direction are formed, wherein a dimension d4 of the second grooves 208 in the Y-axis direction is larger than a dimension d3 of the first grooves 207 in the Y-axis direction, and the second grooves 208 extend along the Y-axis direction. The remaining second isolation layer 202 and the first isolation layer 201 together constitute an initial isolation structure 206a.

Next, the first recess 207 and the second recess 208 are filled with a channel material, forming a first active region 101 located in the first recess 207 and a second active region 102 located in the second recess 208 as shown in fig. 34.

In embodiments of the present disclosure, the channel material may be a metal oxide, such as IGZO, ITO, and TTO. In the embodiments of the present disclosure, the first active region 101 and the second active region 102 may be formed by any suitable process.

In the embodiment of the present disclosure, as shown in fig. 34, the first active region 101 and the second active region 102 on one side in the X-axis direction form one active area group 10. According to the embodiment of the disclosure, the first active region and the second active region which are reasonably arranged are formed, so that the space in the semiconductor structure can be effectively utilized, and the integration level of the semiconductor structure is improved.

In some embodiments, after forming the first active region and the second active region, a method of forming a semiconductor structure includes: respectively carrying out ion implantation on the bottom and the top of the first active region to form a first source electrode and a first drain electrode; a region between the first source and the first drain forms a first channel; and sequentially forming a first gate dielectric layer and a first gate conductive layer on the surface of the first channel to form a first gate.

In some embodiments, after forming the first source electrode and before forming the first gate electrode, the method of forming the semiconductor structure further comprises: a first conductive line is formed to be connected to the first source electrode and to extend in a third direction.

In some embodiments, after forming the first channel, the method of forming the semiconductor structure further comprises: a second conductive line is formed to be connected to the first gate electrode and to extend in a fourth direction.

In some embodiments, after forming the second conductive line, the method of forming the semiconductor structure further comprises: an isolation structure is formed in the gap between the first active region and the second active region, wherein a top surface of the isolation structure is flush with a top surface of the second active region and the top surface of the isolation structure exceeds the top surface of the first active region.

In some embodiments, after forming the isolation structure, the method of forming the semiconductor structure further comprises: ion implantation is carried out on two ends of the second active region along the first direction, so that a second source electrode and a second drain electrode are formed; forming a second gate dielectric layer in the surface center of the second active region; and forming a second gate conductive layer connecting the first drain electrode and the second gate dielectric layer to form a second gate.

In some embodiments, the method of forming a semiconductor structure further comprises: forming a first dielectric layer on the surfaces of the second grid electrode conductive layer and the second grid electrode conductive layer; etching the first dielectric layer and the second grid dielectric layer until the second source electrode is exposed, and forming a first etching hole; forming a first conductive post in the first etching hole; and forming a third conductive line connected with the first conductive post. In other embodiments, the first etching hole may expose the sources of two adjacent active area groups at the same time, so that the two adjacent active area groups share the third conductive line, which may improve the integration of the semiconductor structure.

In some embodiments, the method of forming a semiconductor structure further comprises: forming a second dielectric layer on the surfaces of the third conductive wire and the first dielectric layer; etching the second dielectric layer and the first dielectric layer until the second drain electrode is exposed, and forming a second etching hole; forming a second conductive post in the second etching hole; fourth conductive lines connected to the second conductive pillars are formed. In other embodiments, the second etching hole may simultaneously expose the drains of two adjacent active area groups, so that the two adjacent active area groups share the fourth conductive line, which may improve the integration of the semiconductor structure.

It should be noted that, in the embodiment of the disclosure, the first etching hole and the second etching hole may be arranged in a staggered manner, and the sizes of the first etching hole and the second etching hole are larger than those of the second source electrode and the second drain electrode, so that the second source electrode and the second drain electrode are fully exposed, contact areas of the formed first conductive column and second conductive column with the second source electrode and the second drain electrode are increased, contact resistance is reduced, and performance of the semiconductor structure is improved.

The method for forming a semiconductor structure according to the embodiments of the present disclosure is similar to the semiconductor structure according to the above embodiments, and for technical features that are not disclosed in detail in the embodiments of the present disclosure, reference should be made to the above embodiments for understanding.

In addition, the embodiment of the disclosure further provides a memory, which may be a dynamic random access memory DRAM, and please refer to fig. 26 and 27, wherein the memory includes the semiconductor structure in the above embodiment, and the semiconductor structure includes a plurality of DRAM memory cells, each memory cell includes a first transistor 103 and a second transistor 104, and the first drain of the first transistor 103 and the second gate dielectric layer of the second transistor 104 are electrically connected through the second gate conductive layer of the second transistor 104.

In the disclosed embodiment, the first transistor 103 in the DRAM memory cell may be a write transistor and the second transistor 104 may be a read transistor. The first source of the first transistor 103 is connected to the write bit line (i.e., the first conductive line 105), the first gate of the first transistor 103 is connected to the write word line (i.e., the second conductive line 106), the second source of the second transistor 104 is connected to the read bit line (i.e., the third conductive line 107), the second drain of the second transistor 104 is connected to the read word line (i.e., the fourth conductive line 108), and the processes of reading and writing "0" and "1" are realized by applying different voltages to the first conductive line 105, the second conductive line 106, the third conductive line 107, and the fourth conductive line 108 to control the on or off of the first transistor 103, and controlling the gate capacitance of the second transistor to assume a high resistance state or a low resistance state.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (19)

1. A semiconductor structure, comprising: the device comprises first active areas arranged in an array along a first direction and a second direction, and second active areas positioned on at least one side of the periphery of each first active area; wherein one of the first active regions and an adjacent one of the second active regions form an active region group;

In each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides;

The first direction and the second direction intersect in a plane;

and a plurality of active area groups are arranged in an array along the first direction and the second direction.

2. The semiconductor structure of claim 1, wherein the second active region is located between two adjacent ones of the first active regions in an ith column of the first active regions aligned in the first direction, and the second active region is located between two adjacent ones of the first active regions each in turn in the second direction, i being either a positive even number or a positive odd number.

3. The semiconductor structure of claim 2, wherein along the first direction, a second active region located between two adjacent first active regions extends along the second direction or the first direction; along the second direction, a second active region located between each adjacent two of the first active regions extends along the first direction or the second direction.

4. The semiconductor structure of claim 3, wherein the second active regions extending in the first direction and/or the second direction are staggered in the first direction.

5. The semiconductor structure of claim 1, wherein the second active region in one of the active region groups is located on one side of the first active region along the first direction; the second active region extends in the first direction or the second direction.

6. The semiconductor structure of claim 1, wherein a plurality of rows of the first active regions arranged along the second direction are staggered in the first direction;

The second active region in one of the active region groups is located on one side of the first active region along the first direction, and the second active region extends along the second direction or the first direction.

7. The semiconductor structure of claim 6, wherein the first active region in one of the active region groups is disposed adjacent to the second active region in the other active region group in the second direction in two of the active region groups adjacent in the second direction.

8. The semiconductor structure of claim 1, wherein a second active region in the active region group is located on one side of a first active region along the second direction, and the second active regions in each adjacent two of the active region groups in turn along the second direction are disposed adjacent to each other; the second active region extends in the first direction or the second direction.

9. The semiconductor structure of claim 8, wherein the second active regions are staggered in the first direction.

10. The semiconductor structure of claim 1, wherein the second active region is L-shaped; the first active region in one of the active region groups is located within an overlapping region of projection regions of the second active region along the first direction and the second direction.

11. The semiconductor structure of claim 10, wherein any adjacent two of the active area groups in a row of the active area groups sequentially arranged along the second direction are axisymmetric, centrosymmetric, or identical in structure;

And in a column of active granules sequentially arranged along the first direction, any two adjacent active granules are axisymmetric, centrosymmetric or identical in structure.

12. The semiconductor structure of claim 11, wherein any two adjacent rows of the active area groups arranged in sequence along the second direction are axisymmetric, centrosymmetric, or structurally identical;

Any two adjacent columns of active area groups which are sequentially arranged along the first direction are axisymmetric, centrosymmetric or identical in structure.

13. The semiconductor structure of any one of claims 1 to 12, further comprising:

a first transistor located in the first active region; the first transistor comprises a first source electrode, a first channel, a first drain electrode and a first grid electrode which are sequentially stacked from bottom to top along a third direction, wherein the first grid electrode surrounds the first channel; the first channel extends along the third direction;

a first conductive line electrically connected to the first source electrode;

A second conductive line electrically connected to the first gate electrode; the third direction intersects a plane in which the first direction and the second direction are located.

14. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises:

A second transistor located on a surface of the second active region; the second transistor comprises a second source electrode, a second drain electrode and a second grid electrode; the second grid electrode is electrically connected with the first drain electrode;

A third conductive line electrically connected to the second source electrode;

and a fourth conductive wire electrically connected to the second drain electrode.

15. The semiconductor structure of claim 14, further comprising a first conductive pillar and a second conductive pillar;

The first conductive post is connected between the second source electrode and the third conductive line; the second conductive pillar is connected between the second drain and the fourth conductive line.

16. The semiconductor structure of claim 15, wherein one of said active set is used to form one memory cell; two adjacent memory cells can share the first conductive pillar and/or the second conductive pillar.

17. A method of forming a semiconductor structure, the method comprising:

Providing a substrate;

Forming first active areas arranged in an array along a first direction and a second direction and second active areas positioned on at least one side of the periphery of each first active area on the surface of the substrate; wherein one of the first active regions and an adjacent one of the second active regions form an active region group;

In each active area group, the projection of the first active area and the second active area in the first direction or the second direction at least partially coincides;

The first direction and the second direction intersect in a plane;

and a plurality of active area groups are arranged in an array along the first direction and the second direction.

18. A memory comprising the semiconductor structure of any of claims 1-16.

19. The memory of claim 18, wherein the memory comprises dynamic random access memory.