CN117998729A

CN117998729A - Embedded device packaging substrate and manufacturing method thereof

Info

Publication number: CN117998729A
Application number: CN202410144763.7A
Authority: CN
Inventors: 陈先明; 黄本霞; 林文健
Original assignee: Nantong Yueya Semiconductor Co ltd
Current assignee: Nantong Yueya Semiconductor Co ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-05-07

Abstract

The present disclosure provides a buried device package substrate and a method of fabrication. The embedded device packaging substrate comprises a first dielectric layer, two second dielectric layers symmetrically arranged on the upper surface and the lower surface of the first dielectric layer, a component on each second dielectric layer, a third dielectric layer and a fourth dielectric layer embedded with the component, and a first circuit layer and a second circuit layer respectively arranged on the two fourth dielectric layers; the first circuit layer and the second circuit layer are respectively connected with terminals of components positioned on the upper surface and the lower surface in a conducting mode, and the first circuit layer is connected with the second circuit layer in a conducting mode. The packaging substrate has a symmetrical layer structure, and can effectively avoid the problem of substrate deformation caused by stress unbalance.

Description

Embedded device packaging substrate and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of device packaging, in particular to a buried device packaging substrate and a manufacturing method thereof.

Background

Emerging electronic products continuously present high functionality, high integration and miniaturization requirements for packaging substrates and printed circuit boards. Embedding electronic components inside a package substrate or a printed circuit board, realizing high integration and miniaturization of electronic products is a current trend of electronic products.

Disclosure of Invention

In view of the above, an object of the present disclosure is to provide a substrate for embedded device package and a method for manufacturing the same.

Based on the above object, in a first aspect, the present disclosure provides a method for manufacturing a package substrate of an embedded device, including:

(a) Preparing an intermediate layer, wherein the intermediate layer comprises a first dielectric layer and two second dielectric layers covering the upper surface and the lower surface of the first dielectric layer;

(b) Respectively attaching components on the surfaces of the two second medium layers, and curing or incompletely curing the second medium layers;

(c) Sequentially stacking an incompletely cured third dielectric layer, a incompletely cured fourth dielectric layer and a copper foil on the two second dielectric layers respectively; wherein the third dielectric layer includes a preset opening such that the component is received within the opening;

(d) Pressing and curing the second dielectric layer, the third dielectric layer and the fourth dielectric layer, and bonding the copper foil on the surface of the fourth dielectric layer, thereby obtaining a core layer of the embedded component;

(e) Respectively manufacturing a first circuit layer and a second circuit layer on two surfaces of the core layer; the first circuit layer is connected with the components on the upper surface in a conducting manner, the second circuit layer is connected with the components on the lower surface in a conducting manner, and the first circuit layer is connected with the second circuit layer in a conducting manner.

In some embodiments, step (a) comprises:

(a1) Preparing a core plate; the core board comprises a first dielectric layer and copper foils symmetrically arranged on the upper surface and the lower surface of the first dielectric layer;

(a2) Manufacturing the copper foil as an alignment target and exposing the upper surface and the lower surface of the first dielectric layer;

(a3) Applying the second dielectric layer on the upper surface and the lower surface respectively; the second dielectric layer covers the first dielectric layer and the alignment target.

In a second aspect, an embodiment of the present disclosure further provides a method for manufacturing a packaging substrate of an embedded device, including:

(b) Stacking and laminating solidified third dielectric layers on the surfaces of the two second dielectric layers respectively; wherein the third dielectric layer comprises a preset opening; mounting components at the positions of the two second dielectric layers exposed by the openings, and curing or incompletely curing the second dielectric layers;

(c) Sequentially stacking an uncured fourth dielectric layer and copper foil on the two third dielectric layers respectively;

In some embodiments, step (a) comprises:

(a2) Removing the copper foil of the upper surface and the lower surface;

(a3) And forming a second dielectric layer covering the first dielectric layer on the upper surface and the lower surface.

In some embodiments, the method further includes a step of preparing a third dielectric layer, specifically including:

Preparing a copper-clad plate; the copper-clad plate comprises a third dielectric layer, and a first copper foil and a second copper foil which are symmetrically arranged on the upper surface and the lower surface of the third dielectric layer; and

Removing the first copper foil to expose the upper surface of the third dielectric layer; and manufacturing the second copper foil as an alignment target and exposing the lower surface of the third dielectric layer.

In some embodiments, the materials of the first dielectric layer, the third dielectric layer and the fourth dielectric layer are glass fiber-containing resin materials; and/or

The second dielectric layer is made of a glass fiber-free resin material.

In some embodiments, the third dielectric layer has a height greater than the height of the component; and/or

The size of the opening is larger than the size of the component.

In some embodiments, the difference between the size of the opening and the size of the component is greater than 0.1mm.

In some embodiments, step (e) comprises:

(e1) Manufacturing a terminal of the component exposed by the blind hole, and manufacturing a through hole penetrating through the core layer;

(e2) Two metal seed layers are manufactured on the two surfaces of the core layer, the blind holes and the hole walls of the through holes;

(e3) Forming a first circuit layer and a second circuit layer on the surfaces of the two metal seed layers respectively, and forming a blind hole column and a through hole column; the terminal of the component is connected with the first circuit layer or the second circuit layer through the blind hole column in a conducting mode, and the first circuit layer is connected with the second circuit layer through the through hole column in a conducting mode.

In some embodiments, the thickness of the two second dielectric layers is the same; the thickness of the two third dielectric layers is the same; the thicknesses of the two fourth dielectric layers are the same.

In a third aspect, an embodiment of the present disclosure further provides an embedded device package substrate, where the embedded device package substrate includes a first dielectric layer, two second dielectric layers symmetrically disposed on an upper surface and a lower surface of the first dielectric layer, a component on each of the second dielectric layers, a third dielectric layer and a fourth dielectric layer embedded with the component, and a first circuit layer and a second circuit layer respectively disposed on the two fourth dielectric layers; the first circuit layer and the second circuit layer are respectively connected with terminals of components positioned on the upper surface and the lower surface in a conducting mode, and the first circuit layer is connected with the second circuit layer in a conducting mode.

In some embodiments, the materials of the first dielectric layer, the third dielectric layer and the fourth dielectric layer are glass fiber-containing resin materials.

In some embodiments, the material of the second dielectric layer is a fiberglass-free resin material.

In some embodiments, the third dielectric layer has a height that is greater than the height of the component.

In some embodiments, an alignment target is further included, the alignment target being embedded between the first dielectric layer and the second dielectric layer or between the third dielectric layer and the fourth dielectric layer.

As can be seen from the above, according to the embedded device packaging substrate and the manufacturing method provided by the present disclosure, through preparing the intermediate layer including two second dielectric layers, component parts are respectively attached to the surfaces of the two second dielectric layers, and the third dielectric layer, the fourth dielectric layer and the circuit layer are respectively arranged, so as to obtain the packaging substrate with a symmetrical layer structure, which can effectively avoid the substrate deformation problem caused by stress unbalance.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure or related art, the drawings required for the embodiments or related art description will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a package structure according to the related art;

FIG. 2 is a schematic diagram of still another package structure according to the related art;

fig. 3 (a) -3 (g) are schematic cross-sectional views of intermediate structures of steps of a method for manufacturing a package substrate of an embedded device according to an embodiment of the disclosure;

Fig. 4 (a) -4 (i) are schematic cross-sectional views of intermediate structures of steps of a method for fabricating a package substrate of a further embedded device according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a package substrate of an embedded device according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of yet another embedded device package substrate provided in an embodiment of the present disclosure.

Detailed Description

For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.

It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed. When terms such as "upper," lower, "and" beside "are used to describe a positional relationship between two components, one or more components may be located between the two components unless these terms are used in conjunction with the terms" immediately below "or" directly on. When an element or layer is disposed "on" another element or layer, the other layer or element may be directly interposed on or between the other elements.

In the drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of description.

As described in the background art, embedding electronic components inside a package substrate or a printed circuit board, realizing high integration and miniaturization of electronic products is a current trend of electronic products. Fig. 1 is a schematic diagram of a package structure according to the related art. As shown in fig. 1, a groove (dotted line frame pointed by arrow in the figure) is made in a core layer 1012', then an adhesive material is applied to the bottom of the groove and the component is attached to the adhesive material in the groove, then a dielectric material is pressed to embed the component, and finally a packaging substrate is obtained through drilling and build-up wiring. However, the production tolerance of the groove depth can only be controlled to be + -75 μm, which means that the depth difference between different grooves is large, resulting in different depths of the embedded components, and when the terminals of the components need to be drilled for subsequent electrical interconnection, some holes are not drilled through because the components are embedded deeply, resulting in subsequent electrical open circuits, and some holes are excessively drilled because the components are embedded shallowly, resulting in burning out the components. That is, the tolerance of the groove depth is large, which is not beneficial to process control and directly affects the quality of the product.

Based on this, emerging embedding techniques have been developed, such as embedding components at non-core layers. Fig. 2 is a schematic diagram of still another package structure provided in the related art. As shown in fig. 2, an adhesive medium layer 201 is firstly applied on the surface of a semi-finished substrate, then a component 203 is attached on the surface of the adhesive medium layer 201, then the component 203 and the adhesive medium layer 101 are wrapped by a pressing medium 202, and finally holes and wirings are drilled and electrically interconnected. With such embedding technique, it is not necessary to make a groove to embed the component, but the component is not embedded in the core layer of the substrate, and thus the structure is asymmetric. Because of the different thermal expansion coefficients of different materials, stress is generated by heating or cooling, and the substrate with an asymmetric structure is deformed due to the fact that stress balance is damaged.

In view of this, the embodiments of the present disclosure provide a method for manufacturing a packaging substrate of an embedded device, which can avoid quality and process problems caused by different depths of grooves, and solve the problem of substrate deformation caused by substrate stress imbalance.

Fig. 3 (a) to 3 (g) are schematic cross-sectional views of intermediate structures of steps of a method for manufacturing a package substrate of an embedded device according to an embodiment of the disclosure. The manufacturing method comprises the following steps:

A core 1011 is prepared. Here, the core board 1011 includes a first dielectric layer 101 and copper foils 102 symmetrically disposed on the upper surface a and the lower surface B of the first dielectric layer 101-step (a 1), as shown in fig. 3 (a).

It should be noted that the material of the first dielectric layer 101 may be a glass fiber-containing resin material, for example, one selected from the group consisting of a liquid crystal polymer, BT (bismaleimide triazine bismaleimide triazine) resin, a prepreg (Prepreg), an ABF (Ajinomoto Build-up) film, an epoxy resin (expoxy) and a polyimide (polyimide) resin, but the disclosure is not limited thereto. The thickness of the copper foil 102 is not particularly limited and required in the present disclosure, and may be selected according to actual needs.

Next, the copper foil 102 is fabricated as the alignment target 103-step (a 2), as shown in fig. 3 (b). Here, the alignment targets 103 may be provided in two for the subsequent process of pasting, blind hole fabrication, and circuit layer alignment.

In some embodiments, the alignment targets 103 may be formed by pattern transfer. Illustratively, applying a photoresist layer to the copper foil 102, patterning the photoresist layer to form a registration target pattern; copper foil 102 is etched and the photoresist layer is removed.

The alignment target 103 is formed while exposing the upper and lower surfaces of the first dielectric layer 101.

Then, a second dielectric layer 104 is formed on the upper surface and the lower surface, respectively, as shown in fig. 3 (c), to obtain an intermediate layer 1041. The intermediate layer 1041 includes a first dielectric layer 101 and two second dielectric layers 104 covering the upper surface a and the lower surface B of the first dielectric layer 101. Optionally, the second dielectric layer 101 covers the first dielectric layer 101 and the alignment targets 103.

Optionally, the material of the second dielectric layer 104 is a glass fiber-free resin material. For example, one selected from the group consisting of a liquid crystal polymer, BT (bismaleimide triazine) resin, a prepreg (Prepreg), an ABF (Ajinomoto Build-up) film, an epoxy resin (expoxy), and a polyimide (polyimide) resin, but the present disclosure is not limited thereto.

Next, the components 105 are respectively mounted on the surfaces of the two second dielectric layers 104, and the second dielectric layers 104 are cured or incompletely cured, as shown in fig. 3 (d).

The component 105 may be an active element (e.g., a transistor, an IC chip, a logic circuit element, a power amplifier), a passive element (e.g., a capacitor, an inductor, a resistor), or a combination thereof. The number of embedded components in the same layer is not limited to only one, and the components 105 on the upper surface and the components 105 on the lower surface may be the same or different, which is not limited in the present disclosure.

Here, the partial curing of the second dielectric layer 104 refers to curing to a different degree, such as half-curing.

Then, a third dielectric layer 106, a fourth dielectric layer 107 and a copper foil 108 which are not completely cured are sequentially stacked on the two second dielectric layers 104, respectively; wherein the third dielectric layer 106 includes a pre-formed opening 1061, the opening 1061 is capable of receiving the component 105—step (c), as shown in fig. 3 (e).

It should be noted that the size of the opening 1061 is larger than the size of the component. In some embodiments, the difference in the size of opening 1061 and the size of component 105 is greater than 0.10mm. For example, the length and width of the opening 1061 are each 0.12mm greater than the length and width of the component 105.

Optionally, the height of the third dielectric layer 106 is greater than the height of the component 105.

Alternatively, the opening 1061 may be formed by laser drilling, mechanical milling, ultraviolet cutting, or the like.

By defining the height of the third dielectric layer 106 and the size of the opening 1061, it may be ensured that the component 105 may be surrounded by the third dielectric layer 106, reducing direct stress on the component 105 during subsequent lamination.

In some embodiments, the material of the third dielectric layer 106 and the fourth dielectric layer 107 is a glass fiber-containing resin material, such as one selected from the group consisting of liquid crystal high molecular polymer, BT (bismaleimide triazine) resin, prepreg (Prepreg), ABF (Ajinomoto Build-up) film, epoxy (expoxy) and polyimide (polyimide) resin, but the disclosure is not limited thereto.

It should be noted that the materials of the first dielectric layer 101, the third dielectric layer 106, and the fourth dielectric layer 107 may be glass fiber-containing resin materials of the same or different materials, which is not limited in the present invention.

Next, the second dielectric layer 104, the third dielectric layer 106, and the fourth dielectric layer 107 are laminated and cured, and the copper foil 108 is adhered to the surface of the fourth dielectric layer 107, so as to obtain a core layer 1012, as shown in fig. 3 (f).

By adopting the technical scheme, the component 105 can be embedded in the core layer (core layer) 1012 without depending on grooving, and the core layer has a symmetrical structure, so that the substrate deformation caused by stress unbalance can be effectively avoided.

In some embodiments, the thickness of the two second dielectric layers 104 is the same; the thickness of the two third dielectric layers 106 is the same; the thickness of the two fourth dielectric layers 107 is the same. By providing the thickness of the two second dielectric layers 104, the thickness of the two third dielectric layers 106, and the thickness of the two fourth dielectric layers 107 are the same, the symmetry and the stress balance of the core layer 1012 can be improved.

Then, a first wiring layer 109 and a second wiring layer 110 are respectively formed on both surfaces of the core layer; the first circuit layer 109 is connected to the component 105 on the upper surface a in a conductive manner, the second circuit layer 110 is connected to the component 105 on the lower surface B in a conductive manner, and the first circuit layer 109 is connected to the second circuit layer 110 in a conductive manner, as shown in fig. 3 (g).

In some embodiments, step (e) may comprise:

First, terminals 1051 and 1052 of the component 105 are exposed by the blind via, and a via hole penetrating through the core layer 1012 is formed (step (e 1).

Optionally, the blind holes are made by laser drilling. Optionally, the through hole is made by mechanical drilling.

Next, two metal seed layers are fabricated on the two surfaces of the core layer 1012, the walls of the blind holes and the through holes-step (e 2). It should be noted that the metal seed layer may be manufactured by a sputtering process, which is not limited in this disclosure.

Finally, a first circuit layer 109 and a second circuit layer 110 are formed on the surfaces of the two metal seed layers, and blind via posts 1091, 1092 and via post 1093 are formed. Here, the terminals 1051, 1052 of the component 105 are connected to the first wiring layer 109 or the second wiring layer 110 via the blind via 1091, 1092, and the first wiring layer 109 and the second wiring layer 110 are connected to each other via the via 1093 (step (e 3).

Illustratively, the first wiring layer 109 is electrically connected to the terminals 1051 of the component 105 on the upper surface a through the blind via posts 1091; the second wiring layer 110 is conductively connected to the terminal 1052 of the component 105 on the lower surface B through the blind via 1092.

It should be noted that, according to the product requirement, the layers can be further increased and the blind holes can be drilled to realize the connection of the lines between different circuit layers, which is not limited by the disclosure.

Fig. 4 (a) to 4 (i) are schematic cross-sectional views of intermediate structures of steps of a method for manufacturing a package substrate of a further embedded device according to an embodiment of the disclosure. The manufacturing method comprises the following steps:

Preparing a core 1011; the core board 1011 includes a first dielectric layer 101 and copper foils 102 symmetrically disposed on the upper surface a and the lower surface B of the first dielectric layer 101-step (a 1), as shown in fig. 4 (a).

Here, the first dielectric layer 101 and the copper foil 102 are defined as described above, and will not be described in detail.

Next, the copper foil 102 on the upper surface a and the lower surface B is removed-step (a 2), as shown in fig. 4 (B). Note that the copper foil 102 may be removed by etching the copper foil 102.

Then, a second dielectric layer 104 is formed on the upper surface a and the lower surface B to cover the first dielectric layer 101, step (a 3), to obtain an intermediate layer 1041, as shown in fig. 4 (c). The intermediate layer 1041 includes a first dielectric layer 101 and two second dielectric layers 104 covering the upper surface a and the lower surface B of the first dielectric layer 101.

Here, the definition of the second dielectric layer 104 is as described above, and will not be described in detail.

Next, a third dielectric layer 106 is prepared, specifically including:

Preparing a copper-clad plate; the copper-clad plate comprises a third dielectric layer 106, and a first copper foil and a second copper foil which are symmetrically arranged on the upper surface and the lower surface of the third dielectric layer 106; and

Removing the first copper foil to expose the upper surface of the third dielectric layer 103; etching the second copper foil to form alignment targets 103.

The first copper foil may be removed by etching. The step of forming the alignment target 103 may refer to the foregoing, and will not be described again.

Here, the third dielectric layer 106 is a dielectric layer that has been cured. The definition of the third dielectric layer may refer to the foregoing, and will not be repeated.

In some embodiments, the ultraviolet light cut forms openings 1061 in the third dielectric layer 106 by laser drilling, mechanical milling, or drilling. For the description of the opening 1061, reference is made to the foregoing, and no further description is given.

Then, stacking and laminating the cured third dielectric layers 106 on the surfaces of the two second dielectric layers 104 respectively; wherein, the third dielectric layer 106 includes preset openings 1061, as shown in fig. 4 (d) and fig. 4 (e); the component 105 is mounted on the positions where the two second dielectric layers 104 are exposed through the openings 1061, and the second dielectric layers 104 are cured or incompletely cured, as shown in fig. 4 (f).

Here, referring to fig. 4 (e), pressing the third dielectric layer 106 may bond the third dielectric layer 106 and the second dielectric layer 104, and the third dielectric layer 106 may be embedded in the second dielectric layer 104 to a certain depth. The second dielectric layer 104 is now in an uncured state.

Next, an uncured fourth dielectric layer 107 and a copper foil 108 are stacked in this order on the two third dielectric layers 106, respectively, step (c), as shown in fig. 4 (g). Note that, the description of the fourth dielectric layer 107 refers to the foregoing description, and will not be repeated.

Then, the second dielectric layer 104, the third dielectric layer 106, the fourth dielectric layer 107 and the copper foil 108 are bonded to the surface of the fourth dielectric layer 107 by lamination and curing, so as to obtain a core layer 1012, as shown in fig. 4 (h).

It should be noted that, bonding between the second dielectric layer 104, the third dielectric layer 106, and the fourth dielectric layer 107 can be achieved by pressing and curing, and the opening 1061 is filled to achieve encapsulation of the component 105. Here, the second dielectric layer 104 not only plays a role of bonding the component 105 but also bonds the third dielectric layer 106 and the first dielectric layer 101.

In addition, before the fourth dielectric layer 107 is laminated, the third dielectric layer 106 is cured to have a certain rigidity, so that the vertical extrusion of the fourth dielectric layer 107 to the component 105 can be buffered and avoided in the lamination process of the step (d), and the damage problem of the component 105 is avoided; and at the same time, the position movement of the component 105 caused by the thrust of the resin flowing in the horizontal direction in the lamination process can be avoided.

Finally, a first circuit layer 109 and a second circuit layer 110 are respectively manufactured on two surfaces of the core layer 1012; the first circuit layer 109 is connected to the component 105 on the upper surface a in a conductive manner, the second circuit layer 110 is connected to the component 105 on the lower surface B in a conductive manner, and the first circuit layer 109 is connected to the second circuit layer 110 in a conductive manner, as shown in fig. 4 (i).

For the specific step of step (e), reference may be made to the foregoing, and no further description is given.

Fig. 5 is a schematic structural diagram of a package substrate of an embedded device according to an embodiment of the disclosure; specifically, fig. 5 shows the embedded device package substrate obtained by the manufacturing method shown in fig. 3 (a) to 3 (g). FIG. 6 is a schematic diagram of yet another embedded device package substrate provided by an embodiment of the present disclosure; specifically, fig. 6 shows the embedded device package substrate obtained by the manufacturing method shown in fig. 4 (a) to 4 (i). The embedded device package substrate includes: the semiconductor device comprises a first dielectric layer 101, two second dielectric layers 104 symmetrically arranged on the upper surface A and the lower surface B of the first dielectric layer 101, a third dielectric layer 106 and a fourth dielectric layer 107 of a component 105 and a buried 105 component on each second dielectric layer 104, and a first circuit layer 109 and a second circuit layer 110 respectively arranged on the two fourth dielectric layers 107; the first wiring layer 109 and the second wiring layer 110 are connected to terminals 1051 and 1052 of the devices on the upper surface a and the lower surface B, respectively, and the first wiring layer 109 is connected to the second wiring layer 110. Illustratively, the first wiring layer 109 conducts terminals 1051 of components connected to the upper surface a, and the second wiring layer 110 conducts terminals 1052 of components connected to the lower surface B.

In some embodiments, the materials of the first dielectric layer 101, the third dielectric layer 106, and the fourth dielectric layer 107 are fiberglass-containing resin materials.

In some embodiments, the material of the second dielectric layer 104 is a fiberglass-free resin material.

In some embodiments, the height of the third dielectric layer 106 is greater than the height of the component 105.

In some embodiments, the alignment targets 103 are further included, and the alignment targets 103 are embedded between the first dielectric layer 101 and the second dielectric layer 104 (as shown in fig. 5) or between the third dielectric layer 106 and the fourth dielectric layer 107 (as shown in fig. 6).

In some embodiments, the thickness of the two second dielectric layers 104 is the same; the thickness of the two third dielectric layers 106 is the same; the thickness of the two fourth dielectric layers 107 is the same.

By directly pasting the component 105 on the second dielectric layer 104, the embedded height error of the component can be greatly reduced, thereby effectively avoiding damage to the component in the subsequent process.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present disclosure, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in details for the sake of brevity.

The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the embodiments of the disclosure, are intended to be included within the scope of the disclosure.

Claims

1. The manufacturing method of the embedded device packaging substrate is characterized by comprising the following steps of:

2. The method of claim 1, wherein step (a) comprises:

3. The manufacturing method of the embedded device packaging substrate is characterized by comprising the following steps of:

4. A method of manufacturing as claimed in claim 3, wherein step (a) comprises:

(a2) Removing the copper foil of the upper surface and the lower surface;

5. The method of claim 3, further comprising the step of preparing a third dielectric layer, comprising:

6. The method according to any one of claims 1 to 5, wherein the materials of the first dielectric layer, the third dielectric layer, and the fourth dielectric layer are glass fiber-containing resin materials; and/or

The second dielectric layer is made of a glass fiber-free resin material.

7. The method of any one of claims 1-5, wherein the third dielectric layer has a height greater than the height of the component; and/or

The size of the opening is larger than the size of the component.

8. The method of claim 7, wherein the difference between the size of the opening and the size of the component is greater than 0.1mm.

9. The method according to any one of claims 1 to 5, wherein step (e) comprises:

10. The method according to any one of claims 1 to 5, wherein the thicknesses of the two second dielectric layers are the same; the thickness of the two third dielectric layers is the same; the thicknesses of the two fourth dielectric layers are the same.

11. The embedded device packaging substrate is characterized by comprising a first dielectric layer, two second dielectric layers symmetrically arranged on the upper surface and the lower surface of the first dielectric layer, a third dielectric layer and a fourth dielectric layer of a component and an embedded component on each second dielectric layer, and a first circuit layer and a second circuit layer respectively arranged on the two fourth dielectric layers; the first circuit layer and the second circuit layer are respectively connected with terminals of components positioned on the upper surface and the lower surface in a conducting mode, and the first circuit layer is connected with the second circuit layer in a conducting mode.

12. The embedded device package substrate of claim 11, wherein the first, third and fourth dielectric layers are of a fiberglass-containing resin material; and/or

The second dielectric layer is made of a glass fiber-free resin material.

13. The embedded device package substrate of claim 11, wherein the third dielectric layer has a height greater than a height of the component.

14. The embedded device package substrate of claim 11, further comprising an alignment target embedded between the first dielectric layer and the second dielectric layer or between the third dielectric layer and the fourth dielectric layer.

15. The embedded device package substrate of claim 11, wherein the thickness of the two second dielectric layers is the same; the thickness of the two third dielectric layers is the same; the thicknesses of the two fourth dielectric layers are the same.