CN117998561A

CN117998561A - Clock adjustment method, device, equipment, medium and vehicle

Info

Publication number: CN117998561A
Application number: CN202211354717.7A
Authority: CN
Inventors: 迟蕾
Original assignee: Beijing Rockwell Technology Co Ltd
Current assignee: Beijing Rockwell Technology Co Ltd
Priority date: 2022-11-01
Filing date: 2022-11-01
Publication date: 2024-05-07

Abstract

The application discloses a clock adjustment method, a clock adjustment device, clock adjustment equipment, a clock adjustment medium and a vehicle. The clock adjustment method comprises the following steps: acquiring a clock frequency adjustment value corresponding to the first module; setting the time of the second module as the target time in the case that the time of the first module reaches the target time; under the condition that the slave device generates a target event, acquiring a first time stamp of the first module for recording the generation time of the target event and a second time stamp of the second module for recording the generation time of the target event; calculating the difference between the second time stamp and the first time stamp to obtain a first time difference, and multiplying the difference between the first time stamp and the target time by the clock frequency adjustment value to obtain a second time difference; and under the condition that the first time difference is not equal to the second time difference, performing clock adjustment on the first module in the slave device according to the clock of the master device so as to synchronize the slave device with the clock of the master device. According to the embodiment of the application, the clock synchronization precision can be improved.

Description

Clock adjustment method, device, equipment, medium and vehicle

Technical Field

The application belongs to the technical field of control, and particularly relates to a clock adjustment method, a clock adjustment device, clock adjustment equipment, a clock adjustment medium and a vehicle.

Background

The time synchronization of many existing application systems is not separated, and particularly for a distributed control system, the time synchronization among all control nodes has important significance for the normal processing of the service.

Typically, after the clock adjustment algorithm is used to adjust the clock of the slave device to be synchronized with the clock of the master device, the clock adjustment algorithm is used again to clock the slave device waiting for the next clock adjustment cycle.

As such, since the clock adjustment algorithm requires that the path delays of the master and slave devices in the network are symmetrical, in real-world networks, it is often the case that the network delays of the master to slave devices and the slave to master devices are unequal, that is, the network delays between the master and slave devices are asymmetrical in both directions. Therefore, the clock of the slave device after clock synchronization adjustment by the clock adjustment algorithm may still have a relatively long time difference from the clock of the master device, so that the clock synchronization accuracy is relatively low.

Disclosure of Invention

The embodiment of the application provides a clock adjustment method, a device, equipment, a medium and a vehicle, which can improve the clock synchronization precision.

In a first aspect, an embodiment of the present application provides a clock adjustment method, applied to a slave device, where the slave device includes a first module and a second module, the first module is a module after clock adjustment according to a clock of a master device, the clock adjustment includes at least frequency adjustment, and the second module is a module without clock frequency adjustment, and the method includes:

Acquiring a clock frequency adjustment value corresponding to the first module, wherein the clock frequency adjustment value is a difference value between the clock frequency adjusted by the first module and the original clock frequency before adjustment;

Setting the time of the second module as the target time under the condition that the time of the first module reaches the target time, wherein the target time is any time of the first module after clock adjustment;

Under the condition that the slave equipment generates a target event, acquiring a first time stamp of the first module for recording the occurrence time of the target event and a second time stamp of the second module for recording the occurrence time of the target event;

calculating the difference between the second timestamp and the first timestamp to obtain a first time difference, and multiplying the difference between the first timestamp and the target time by the clock frequency adjustment value to obtain a second time difference;

and under the condition that the first time difference is not equal to the second time difference, performing clock adjustment on the first module in the slave device according to the clock of the master device so as to synchronize the slave device with the clock of the master device.

In a second aspect, an embodiment of the present application provides a clock adjustment device configured in a slave device, where the slave device includes a first module and a second module, the first module is a module after clock adjustment according to a clock of a master device, the clock adjustment includes at least frequency adjustment, and the second module is a module without clock frequency adjustment, and the device includes:

The frequency acquisition module is used for acquiring a clock frequency adjustment value corresponding to the first module, wherein the clock frequency adjustment value is a difference value between the clock frequency adjusted by the first module and the original clock frequency before adjustment;

the time setting module is used for setting the time of the second module as the target time under the condition that the time of the first module reaches the target time, wherein the target time is any time of the first module after clock adjustment;

The time acquisition module is used for acquiring a first time stamp of the target event occurrence time recorded by the first module and a second time stamp of the target event occurrence time recorded by the second module under the condition that the target event occurs by the slave equipment;

the time calculation module is used for calculating the difference between the second time stamp and the first time stamp to obtain a first time difference, and multiplying the difference between the first time stamp and the target time by the clock frequency adjustment value to obtain a second time difference;

And the clock adjustment module is used for adjusting the clock of the first module in the slave equipment according to the clock of the master equipment under the condition that the first time difference is unequal to the second time difference so as to synchronize the clocks of the slave equipment and the master equipment.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory storing computer program instructions;

The processor when executing the computer program instructions implements the steps of the clock adjustment method as described in any of the embodiments of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the steps of the clock adjustment method as described in any of the embodiments of the first aspect.

In a fifth aspect, an embodiment of the present application provides a vehicle including at least one of:

a clock adjustment device as in any one of the embodiments of the second aspect;

an electronic device as in any of the embodiments of the third aspect;

a computer readable storage medium as in any one of the embodiments of the fourth aspect.

According to the clock adjustment method, the device, the equipment, the medium and the vehicle, when the first module after clock adjustment reaches the target time, the second module which is not subjected to clock frequency adjustment is subjected to time alignment, namely, the time of the second module is set to be the target time, then when the slave equipment generates the target event, the first time stamp recorded by the first module and the second time stamp recorded by the second module are acquired, the difference value between the second time stamp and the first time stamp is calculated to obtain the first time difference, the difference between the first time stamp and the target time is obtained, the clock frequency adjustment value corresponding to the first module is multiplied to obtain the second time difference, whether the first time difference is equal to the second time is further judged, and when the first time difference is not equal to the second time, the clock of the slave equipment is not synchronous with the clock of the master equipment, and then the clock adjustment is performed on the first module in the slave equipment according to the clock of the master equipment, so that the slave equipment and the clock of the master equipment is synchronous with the clock of the slave equipment. Therefore, the accuracy of the clock adjustment algorithm is verified by comparing the time length recorded by the second module which is not subjected to clock adjustment with the time length recorded by the first module which is subjected to clock adjustment in the same time period, and the clock adjustment is performed on the slave device in time under the condition of inaccuracy, so that the accuracy of clock synchronization can be improved.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

FIG. 1 is a flow chart of a clock adjustment method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a time stamp recording process provided by the present application;

FIG. 3 is a schematic diagram of a clock adjustment device according to an embodiment of the present application;

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

At present, for a clock adjustment algorithm adopted when clock synchronization is performed among all control nodes in a distributed system, an IEEE1588 standard defines a clock adjustment algorithm applied to the distributed system and based on PTP (Precision Time Protocol, accurate clock synchronization protocol), the protocol is applicable to any distributed control system meeting multipoint communication, high-precision clock synchronization can be realized for terminal equipment adopting a multicast technology, and the synchronization precision can reach nanosecond level.

The basic operation principle of PTP is that synchronous messages are transmitted and exchanged between nodes, time deviation between master and slave devices and transmission delay of the messages in a network are determined, and then local clocks of slave devices are corrected, so that synchronous precision between master and slave devices can reach sub microsecond level. PTP defines the message type, message format, etc., while the key clock adjustment algorithm implementation varies from device to device. The clock adjustment algorithm determines the final synchronization accuracy. Since the premise of the PTP clock adjustment algorithm is that the path delays of the master and slave devices in the network are symmetrical, in a real network, the network delays of the master and slave devices are often unequal to the network delays of the slave and master devices, that is, the network delays between the master and slave devices are asymmetrical in two directions. Therefore, the clock of the slave device after clock synchronization adjustment by the PTP clock adjustment algorithm may still have a relatively long time difference from the clock of the master device, thereby resulting in lower precision of clock synchronization.

It should be noted that, the slave device according to the embodiment of the present application may be, for example, a PTP slave clock device, and the master device may be, for example, a PTP master clock device.

In order to solve the problems in the prior art, the embodiment of the application provides a clock adjustment method, a device, equipment, a medium and a vehicle, wherein the clock adjustment method can be applied to a scene of adjusting a clock of slave equipment. The following first describes a clock adjustment method provided by an embodiment of the present application.

Fig. 1 is a flowchart of a clock adjustment method according to an embodiment of the present application. The clock adjustment method can be applied to the slave equipment, and the slave equipment can comprise a first module and a second module, wherein the first module is a module after clock adjustment according to the clock of the master equipment, the clock adjustment at least comprises frequency adjustment, and the second module is a module without clock frequency adjustment.

As shown in fig. 1, the clock adjustment method specifically includes the following steps:

s110, acquiring a clock frequency adjustment value corresponding to the first module, wherein the clock frequency adjustment value is a difference value between the clock frequency adjusted by the first module and the original clock frequency before adjustment;

s120, setting the time of the second module as target time under the condition that the time of the first module reaches the target time, wherein the target time is any time of the first module after clock adjustment;

S130, under the condition that a target event occurs in the slave device, acquiring a first time stamp of the first module for recording the occurrence time of the target event and a second time stamp of the second module for recording the occurrence time of the target event;

s140, calculating the difference between the second time stamp and the first time stamp to obtain a first time difference, and multiplying the difference between the first time stamp and the target time by the clock frequency adjustment value to obtain a second time difference;

And S150, under the condition that the first time difference is not equal to the second time difference, performing clock adjustment on the first module in the slave device according to the clock of the master device so as to synchronize the clocks of the slave device and the master device.

In this way, when the first module after clock adjustment reaches the target time, the second module without clock frequency adjustment is time aligned, that is, the time of the second module is set as the target time, then when the slave device generates the target event, the first time stamp recorded by the first module and the second time stamp recorded by the second module are acquired, the difference between the second time stamp and the first time stamp is calculated, the first time difference and the difference between the first time stamp and the target time are obtained, the clock frequency adjustment value corresponding to the first module is multiplied to obtain the second time difference, whether the first time difference and the second time are equal is further judged, and in the case of inequality, it is stated that the clock of the slave device and the clock of the master device are not synchronous at this time, and then the clock adjustment is performed on the slave device according to the clock of the master device, so that the clock of the slave device and the master device is synchronous. Therefore, the accuracy of the clock adjustment algorithm is verified by comparing the time length recorded by the second module which is not subjected to clock adjustment with the time length recorded by the first module which is subjected to clock adjustment in the same time period, and the clock adjustment is performed on the slave device in time under the condition of inaccuracy, so that the accuracy of clock synchronization can be improved.

A specific implementation of each of the above steps is described below.

In some embodiments, in S110, the first module may be a module in the slave device that needs to perform clock adjustment synchronously when performing clock adjustment according to the clock of the master device. The clock adjustment may include frequency adjustment, and time adjustment.

In some examples, the first module may be, for example, a PHY (Port PHYSICAL LAYER ) module PHY module may be a module for operating a physical layer in an OSI (Open System Interconnection Reference Model, open communication system interconnection reference model) seven-layer protocol model, and one ethernet PHY may be a chip for transmitting and receiving data frames of ethernet.

For example, after the first module in the slave device performs clock adjustment according to the clock of the master device and determines that the slave device is in time synchronization with the master device according to the clock adjustment algorithm, a difference between the clock frequency adjusted by the first module and the original clock frequency before adjustment is obtained, that is, a clock frequency adjustment value, which is also a clock frequency adjustment value corresponding to the entire slave device.

Based on this, in some possible embodiments, the S110 may specifically include:

Based on a PTP clock adjustment algorithm, performing clock adjustment on the slave device according to the clock of the master device;

And acquiring a clock frequency adjustment value corresponding to the first module under the condition that the clock synchronization of the slave device and the master device is determined.

Here, the clock adjustment may include frequency adjustment, and time adjustment, and is not limited thereto.

For example, other modules in the slave device except the second module may adjust the time and frequency of the own clock based on the PTP clock adjustment algorithm, and after synchronization is adjusted, the clock frequency adjustment value corresponding to the first module may be obtained.

In addition, in some embodiments, before the clock frequency adjustment value corresponding to the first module is obtained in the case where it is determined that the slave device is synchronous with the clock of the master device, the clock adjustment method provided by the embodiment of the present application may further include:

And after the clock is adjusted for a preset duration, determining that the slave device is synchronous with the clock of the master device.

In some specific examples, the slave device may adjust the time and frequency of its own clock based on a PTP clock adjustment algorithm, and continuously run for a preset period of time, and after the clock adjustment algorithm is running stably, it may be determined that the clocks of the slave device and the master device are synchronized. It should be noted that, during the clock adjustment process of the slave device, the clock frequency of the first module may be adjusted synchronously, without adjusting the clock frequency of the second module, that is, the second module is kept running according to the original clock frequency.

In some embodiments, in S120, the second module may be a module in the slave device that is not adjusted in clock frequency, that is, when the first module in the slave device performs clock frequency adjustment and time adjustment according to the clock of the master device, only the time of the second module may be adjusted, and the clock frequency of the second module is not adjusted, so that the original clock frequency of the slave device is kept unchanged. Of course, the time of the second module may be neither adjusted nor the clock frequency of the second module, which is not limited herein.

In some examples, the second module may be, for example, a MAC (MEDIA ACCESS Control, medium access Control) module, which may be located at a data link layer in the OSI seven-layer protocol model, for controlling and interfacing with a physical medium of the physical layer.

For example, the time of the second module may be adjusted to align the time of the second module with the time of the first module in the case where the first module, which is adjusted by the clock, operates according to the adjusted clock and reaches the target time. Specifically, the time of the second module may be set as the target time, and the clock frequency of the second module is still not adjusted. The target time may be any time after the slave device adjusts the clock, which is not limited herein. For example, the slave device completes the clock adjustment at 7 points, the target time may be set to 7:05.

In some specific examples, taking the first module as a PHY module and taking the second module as an MAC module as an example, after the clock adjustment algorithm runs stably, that is, when it is determined that clocks of the slave device and the master device are synchronous based on the clock adjustment algorithm, a self-checking process of the clock adjustment algorithm may be started, and at S time (that is, a target time), the slave device may set the time of the MAC to be the same as the time of the PHY, so as to align the time of the MAC and the PHY.

In some embodiments, in S130, both the first module and the second module in the slave device may record a timestamp, and the target event may be an event, such as a message reception event, capable of triggering the first module and the second module to record the timestamp at the same time.

In some possible embodiments, the target event may specifically include receiving a target packet sent by the master device. Illustratively, in the PTP clock adjustment algorithm, the target message may be a PTP message, such as a sync message.

In some specific examples, the master device may send a sync message to the slave device, and when the slave device receives the sync message, the PHY may record a message reception timestamp T2p, that is, a first timestamp, and at the same time, the MAC may record a message reception timestamp T2m, that is, a second timestamp.

In some embodiments, in S140, the first time difference t1 may be calculated according to the following equation (1):

t1＝T2m-T2p (1)

Wherein T2m is a second timestamp, and T2p is a first timestamp. The first time difference may be a positive value or a negative value, and may be specifically related to the clock adjustment direction, which is not limited herein.

In addition, the second time difference t2 may also be calculated according to the following formula (2):

t2＝(T2p-S)*A (2)

wherein S is a target time, a is a clock frequency adjustment value corresponding to the first module, and T2p is a first timestamp.

In the case that the target event includes receiving a target message sent by the master device, the target message may include a message sending timestamp recorded when the master device sends the target message.

Based on this, in some possible embodiments, the step of calculating the second time difference in S140 may specifically include:

calculating the difference between the message sending time stamp and the first time stamp to obtain network delay time;

Subtracting the target time from the sum of the message sending time stamp and the network delay time to obtain a third time difference;

and multiplying the third time difference by the clock frequency adjustment value to obtain a second time difference.

Here, the network delay time Dms may be calculated according to the following equation (3):

Dms＝T1-T2p (3)

Wherein T1 is a message sending timestamp, and T2p is a first timestamp.

Based on this, the third time difference t3 can also be calculated according to the following formula (4):

t3＝T1+Dms-S (4)

wherein T1 is a message sending timestamp, S is a target time, and Dms is a network delay time.

Thus, the second time difference t2 may be calculated according to equation (5):

t2＝t3*A (5)

wherein T3 is a third time difference, and a is a clock frequency adjustment value corresponding to the first module.

As shown in fig. 2, when the MAC reaches S, the PHY time may be set to be the same as the MAC, and then the master device may send a sync message to the slave device and carry a message sending timestamp T1 recorded by the master device, and when the slave device receives the sync message, the PHY records a first timestamp T2p and the MAC records a second timestamp T2m. And then according to the formula (1) and the formulas (3) to (5), the first time difference t1 and the second time difference t2 can be calculated.

In some embodiments, in S150, since the second module does not make the adjustment of the clock frequency, the second module still operates at the original clock frequency in this period T3 from the target time to the time when the target event occurs, and if the master and slave devices are clocked synchronously, the second timestamp T2m recorded by the second module should be different from the first timestamp T2p recorded by the first module, that is, the difference between the two should be equal to T3 times the clock frequency adjustment value a, that is, the first time difference should be equal to the second time difference.

Based on the above, it can be determined whether the first time difference is equal to the second time difference, if so, the clocks of the master device and the slave device can be considered to be already synchronized, otherwise, the clocks of the master device and the slave device are considered to be not synchronized, and further clock adjustment needs to be continued. The clock adjustment is performed by, but not limited to, performing clock adjustment on the first module in the slave device according to the clock of the master device based on the PTP clock adjustment algorithm, where the clock adjustment may include frequency adjustment, and may also include frequency adjustment and time adjustment.

In some possible embodiments, the clock adjustment method may further include:

In the case where the first time difference and the second time difference are equal, it is determined that the clocks of the slave device and the master device are synchronized.

In addition, it should be noted that the above-mentioned verification process of clock synchronization may be performed periodically, that is, after S150 is performed, S110 may be performed back in the next verification period, and so on.

In this way, in the embodiment of the application, after the clock of the slave device is adjusted by using the existing PTP clock adjustment algorithm, the self-checking process of clock synchronization is also periodically performed to verify the accuracy of the clock adjustment algorithm, so that the improvement of the clock synchronization accuracy of PTP can be facilitated, and the effect is more obvious especially in the environment of asymmetric path delay.

Based on the same inventive concept, the application also provides a clock adjusting device. This is described in detail with reference to fig. 3.

Fig. 3 is a schematic structural diagram of a clock adjustment device according to an embodiment of the present application. The clock adjustment device can be configured in the slave device, the first module is a module which is subjected to clock adjustment according to the clock of the master device, the clock adjustment at least comprises frequency adjustment, and the second module is a module which is not subjected to clock frequency adjustment.

As shown in fig. 3, the clock adjustment device 300 may include:

A frequency obtaining module 301, configured to obtain a clock frequency adjustment value corresponding to the first module, where the clock frequency adjustment value is a difference between a clock frequency adjusted by the first module and an original clock frequency before adjustment;

A time setting module 302, configured to set, when the time of the first module reaches a target time, the time of the second module as the target time, where the target time is any time after the first module is adjusted by a clock;

A time obtaining module 303, configured to obtain, when the slave device generates a target event, a first timestamp that the first module records the occurrence time of the target event, and a second timestamp that the second module records the occurrence time of the target event;

A time calculation module 304, configured to calculate a difference between the second timestamp and the first timestamp to obtain a first time difference, and multiply the difference between the first timestamp and the target time with the clock frequency adjustment value to obtain a second time difference;

and the clock adjustment module 305 is configured to perform clock adjustment on the first module in the slave device according to the clock of the master device, so as to synchronize the clocks of the slave device and the master device, when the first time difference and the second time difference are not equal.

The following describes the clock adjustment device 300 in detail, and is specifically described as follows:

in some embodiments, the clock adjustment device 300 may further include:

and the synchronization determining module is used for determining that the slave device is synchronous with the clock of the master device under the condition that the first time difference is equal to the second time difference.

In some embodiments, the target event includes receiving a target message sent by the master device.

In some embodiments, the target message includes a message sending timestamp recorded when the master device sends the target message;

The time calculation module 304 includes:

The first calculation sub-module is used for calculating the difference between the message sending time stamp and the first time stamp to obtain network delay time;

the second calculation sub-module is used for subtracting the target time from the sum of the message sending time stamp and the network delay time to obtain a third time difference;

And the third calculation sub-module is used for multiplying the third time difference by the clock frequency adjustment value to obtain the second time difference.

In some embodiments, the frequency acquisition module 301 may specifically include:

the adjusting submodule is used for adjusting the clock of the slave equipment according to the clock of the master equipment based on a precision clock synchronization protocol PTP clock adjusting algorithm;

And the acquisition sub-module is used for acquiring the clock frequency adjustment value corresponding to the first module under the condition that the clock synchronization of the slave equipment and the master equipment is determined.

In some embodiments, the frequency acquisition module 301 may further include:

And the determining submodule is used for determining clock synchronization of the slave equipment and the master equipment after the clock adjustment lasts for a preset duration.

In some of these embodiments, the first module is a port physical layer PHY module and the second module is a medium access control MAC module.

Therefore, when the first module after clock adjustment reaches the target time, the second module which is not subjected to clock frequency adjustment is subjected to time alignment, namely, the time of the second module is set to be the target time, then when the slave device generates the target event, the first time stamp recorded by the first module and the second time stamp recorded by the second module are acquired, the difference value between the second time stamp and the first time stamp is calculated, the first time difference is obtained, the difference value between the first time stamp and the target time is obtained, the clock frequency adjustment value corresponding to the first module is multiplied to obtain the second time difference, whether the first time difference and the second time are equal or not is further judged, and in the case of inequality, the clock of the slave device and the clock of the master device are not synchronous at the moment, and then the clock adjustment is performed on the slave device according to the clock of the master device, so that the clock of the slave device and the master device is synchronous. Therefore, the accuracy of the clock adjustment algorithm is verified by comparing the time length recorded by the second module which is not subjected to clock adjustment with the time length recorded by the first module which is subjected to clock adjustment in the same time period, and the clock adjustment is performed on the slave device in time under the condition of inaccuracy, so that the accuracy of clock synchronization can be improved.

A processor 401 and a memory 402 in which computer program instructions are stored may be included in the electronic device 400.

In particular, the processor 401 may include a Central Processing Unit (CPU), or an Application SPECIFIC INTEGRATED Circuit (ASIC), or may be configured as one or more integrated circuits that implement embodiments of the present application.

Memory 402 may include mass storage for data or instructions. By way of example, and not limitation, memory 402 may comprise a hard disk drive (HARD DISK DRIVE, HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a universal serial bus (Universal Serial Bus, USB) drive, or a combination of two or more of the foregoing. Memory 402 may include removable or non-removable (or fixed) media, where appropriate. Memory 402 may be internal or external to the integrated gateway disaster recovery device, where appropriate. In a particular embodiment, the memory 402 is a non-volatile solid state memory.

In particular embodiments, the memory may include Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors) it is operable to perform the operations described with reference to a method in accordance with an aspect of the application.

The processor 401 implements any of the clock adjustment methods of the above embodiments by reading and executing computer program instructions stored in the memory 402.

In some examples, electronic device 400 may also include communication interface 403 and bus 410. As shown in fig. 4, the processor 401, the memory 402, and the communication interface 403 are connected by a bus 410 and perform communication with each other.

The communication interface 403 is mainly used to implement communication between modules, apparatuses, units and/or devices in the embodiment of the present application.

Bus 410 includes hardware, software, or both, coupling components of the online data flow billing device to each other. By way of example, and not limitation, bus 410 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a micro channel architecture (MCa) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus, or a combination of two or more of the above. Bus 410 may include one or more buses, where appropriate. Although embodiments of the application have been described and illustrated with respect to a particular bus, the application contemplates any suitable bus or interconnect.

By way of example, the electronic device 400 may be a cell phone, tablet computer, notebook computer, palm computer, vehicle mounted electronic device, ultra-mobile personal computer (UMPC), netbook or Personal Digital Assistant (PDA), or the like.

The electronic device 400 may perform the clock adjustment method in the embodiment of the present application, thereby implementing the clock adjustment method and apparatus described in connection with fig. 1 and 3.

In addition, in combination with the clock adjustment method in the above embodiment, the embodiment of the present application may be implemented by providing a computer readable storage medium. The computer readable storage medium has stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement any of the clock adjustment methods of the above embodiments. Examples of computer readable storage media include non-transitory computer readable storage media such as portable disks, hard disks, random Access Memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROM or flash memories), portable compact disk read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, and the like.

In addition, the embodiment of the application also provides a vehicle, which can comprise at least one of the following components:

an electronic device as in any of the embodiments of the third aspect;

a computer readable storage medium as in any one of the embodiments of the fourth aspect. And will not be described in detail herein.

It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. The method processes of the present application are not limited to the specific steps described and shown, but various changes, modifications and additions, or the order between steps may be made by those skilled in the art after appreciating the spirit of the present application.

The functional blocks shown in the above-described structural block diagrams may be implemented in hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave. A "machine-readable medium" may include any medium that can store or transfer information. Examples of machine-readable media include electronic circuitry, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. The present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.

Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to being, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware which performs the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present application, and they should be included in the scope of the present application.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. The clock adjustment method is applied to the slave device, and is characterized in that the slave device comprises a first module and a second module, the first module is a module after clock adjustment according to the clock of the master device, the clock adjustment at least comprises frequency adjustment, and the second module is a module without clock frequency adjustment, and the method comprises the following steps:

2. The method of claim 1, wherein the target event comprises receiving a target message sent by the master device.

3. The method of claim 2, wherein the target message includes a message transmission timestamp recorded when the master device transmitted the target message;

multiplying the difference between the first timestamp and the target time by the clock frequency adjustment value to obtain a second time difference, including:

And multiplying the third time difference by the clock frequency adjustment value to obtain the second time difference.

4. The method of claim 1, wherein the obtaining the clock frequency adjustment value corresponding to the first module comprises:

And acquiring a clock frequency adjustment value corresponding to the first module under the condition that the slave device and the clock of the master device are synchronous.

5. The method of claim 4, wherein, in the event that it is determined that the slave device is synchronized with the clock of the master device, prior to obtaining the clock frequency adjustment value corresponding to the first module, the method further comprises:

6. The method of any of claims 1-5, wherein the first module is a port physical layer PHY module and the second module is a medium access control MAC module.

7. A clock adjustment device configured in a slave device, wherein the slave device includes a first module and a second module, the first module is a module after clock adjustment according to a clock of a master device, the clock adjustment includes at least frequency adjustment, and the second module is a module without clock frequency adjustment, the device includes:

8. An electronic device, the electronic device comprising: a processor and a memory storing computer program instructions;

The processor, when executing the computer program instructions, implements the steps of the clock adjustment method according to any one of claims 1-6.

9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon computer program instructions, which when executed by a processor, implement the steps of the clock adjustment method according to any of claims 1-6.

10. A vehicle, comprising at least one of:

the clock adjustment device of claim 7;

The electronic device of claim 8;

The computer readable storage medium of claim 9.