CN117995091A - Pixel circuit, driving method thereof, display panel and display device - Google Patents

Abstract

The invention discloses a pixel circuit and a driving method thereof, a display panel and a display device, wherein the pixel circuit comprises a driving transistor, a light emitting element, an initialization module, a writing module, an isolation module, a storage module and a light emitting control module; the isolation module is used for disconnecting the passage between the first node and the second node in the initialization stage and the threshold compensation stage, and conducting the passage between the second node and the first node in the data writing stage and the light-emitting stage; the storage module is used for storing the data signals written into the second node in the initialization stage and the threshold compensation stage, storing the threshold voltage of the driving transistor in the threshold compensation stage, and controlling the potential of the second node to have the same variation as the potential of the third node in the light-emitting stage; the light emitting control module is used for transmitting a first power signal to the third node in an initialization stage and controlling the time for the driving transistor to provide driving current for the light emitting element in a light emitting stage. By adopting the scheme, the light-emitting element can emit light accurately and stably.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

With the continuous development and improvement of display technology, the requirements of people on display are also increasing. Wherein the organic light emitting display device realizes image display by a plurality of pixels arranged in a matrix form, each pixel including a light emitting element and a driving transistor driving the light emitting element to emit light. The luminance of the light emitting element is controlled by a driving current flowing through the driving transistor, and the driving current is affected by a gate-source voltage and a threshold voltage of the driving transistor.

In the conventional pixel circuit, due to the influence of the manufacturing process and the degradation of the driving transistor, the threshold voltages of the driving transistors in different pixels drift, thereby influencing the light emitting stability of the light emitting element.

Disclosure of Invention

The invention provides a pixel circuit, a driving method thereof, a display panel and a display device, which are used for compensating the threshold voltage of a driving transistor and improving the luminous stability of a luminous element.

In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving transistor, a light-emitting element, an initialization module, a writing module, an isolation module, a storage module and a light-emitting control module;

the initialization module and the grid electrode of the driving transistor are electrically connected to a first node; the writing module is used for writing an initialization signal to the first node in an initialization stage and a threshold compensation stage;

The writing module is electrically connected with the storage module and the second node, and the storage module is also electrically connected with the first electrode of the driving transistor and the third node; the writing module is used for writing a data signal to the second node in the initialization stage and the threshold compensation stage; the storage module is used for storing the data signals written into the second node in the initialization stage and the threshold compensation stage, storing the threshold voltage of the driving transistor in the threshold compensation stage, and controlling the potential of the second node to have the same variation with the potential of the third node in the light-emitting stage;

The isolation module is electrically connected between the first node and the second node; the isolation module is used for disconnecting the passage between the first node and the second node in the initialization stage and the threshold compensation stage, and conducting the passage between the second node and the first node in the data writing stage and the light-emitting stage;

The light-emitting control module is electrically connected to the third node; the light-emitting control module is used for transmitting a first power supply signal to the third node in the initialization stage and controlling the time for the driving transistor to provide driving current for the light-emitting element in the light-emitting stage;

The anode of the light emitting element is electrically connected with the second electrode of the driving transistor, and the cathode of the light emitting element is electrically connected with the second power supply terminal. ,

In a second aspect, an embodiment of the present invention further provides a driving method of a pixel circuit, for driving the pixel circuit according to the first aspect, including:

An initialization stage, wherein the initialization module provides an initialization signal for the first node; the writing module writes the data signal into the second node and stores the data signal in the storage module; the light-emitting control module provides a first power supply signal to the third node;

A threshold compensation stage, wherein the initialization module controls the potential of the first node to be kept as the initialization signal, the writing module controls the second node to be kept as the data signal, the light-emitting control module stops providing a first power supply signal to the third node, and the threshold voltage of the driving transistor is compensated into the storage module;

a data writing stage, wherein the isolation module conducts a passage between the second node and the first node;

The light-emitting stage, the light-emitting control module controls the first power supply signal to be transmitted to the third node; the storage module controls the potential of the second node to have the same variation as the potential of the third node; the isolation module controls the second node and the first node to keep a conducting state; the driving transistor supplies a driving current to the light emitting element according to a potential difference between the first node and the third node.

In a third aspect, an embodiment of the present invention further provides a display panel, including a plurality of pixel circuits as described in the first aspect arranged in an array.

In a fourth aspect, an embodiment of the present invention further provides a display apparatus, including the display panel in the third aspect.

According to the technical scheme, the initializing module, the isolation module and the grid electrode of the driving transistor are electrically connected to the first node, the writing module, the isolation module and the storage module are electrically connected to the second node, the storage module, the light-emitting control module and the first electrode of the driving transistor are electrically connected to the third node, the second electrode of the driving transistor is electrically connected with the anode of the light-emitting element, the cathode of the light-emitting element is electrically connected with the second power end, so that the pixel circuit is provided with an initializing signal by the initializing module to the first node in an initializing stage, the writing module writes a data signal into the second node and stores the data signal in the storage module, and the light-emitting control module provides a first power signal to the third node, and can control the driving transistor to be conducted under the control of the initializing signal and the first power signal. In the threshold compensation stage, the light-emitting control module stops providing the first power supply signal to the third node, so that the threshold voltage of the driving transistor is compensated into the memory module. In the data writing stage, the isolation module conducts the path between the second node and the first node, so that the data signal written by the second node is transmitted to the first node, namely, is written into the grid electrode of the driving transistor. In the light emitting stage, the light emitting control module controls the first power supply signal to be transmitted to the third node, and under the action that the storage module controls the potential of the second node to have the same variation as the potential of the third node, the first node also has the same variation as the potential of the third node. Therefore, the threshold voltage of the driving transistor can be compensated, the threshold drift of the driving transistor caused by aging of the driving transistor, process and the like can not be caused, the magnitude of the driving current generated by the driving transistor is not influenced, and the light-emitting stability of the light-emitting element is further improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

Fig. 5 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

fig. 7 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention;

FIG. 8 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

Fig. 9 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural diagram of a pixel circuit provided by an example of the present invention, and as shown in fig. 1, the pixel circuit includes a driving transistor DTFT, a light emitting element 10, an initialization module 20, a writing module 30, an isolation module 40, a storage module 50, and a light emitting control module 60. The initialization module 20 and the gate of the driving transistor DTFT are electrically connected to the first node N1; the initialization module 20 is configured to write an initialization signal to the first node N1 during an initialization phase and a threshold compensation phase. The writing module 30 and the memory module 50 are electrically connected to the second node N2, and the memory module 50 is also electrically connected to the third node N3 with the first pole of the driving transistor DTFT; the writing module 30 is configured to write the data signal to the second node N2 in the initialization phase and the threshold compensation phase. The storage module 50 is used for storing the data signal written into the second node N2 in the initialization phase and the threshold compensation phase, storing the threshold voltage of the driving transistor DTFT in the threshold compensation phase, and controlling the potential of the second node N2 to have the same variation as the potential of the third node N3 in the light emitting phase. The isolation module 40 is electrically connected between the first node N1 and the second node N2; the isolation module 40 is used for disconnecting the path between the first node N1 and the second node N2 in the initialization phase and the threshold compensation phase, and conducting the path between the second node N2 and the first node N1 in the data writing phase and the light emitting phase. The light-emitting control module 60 is electrically connected to the third node N3; the light-emitting control module 60 is configured to transmit the first power signal to the third node N3 during the initialization phase, and to control the time for the driving transistor DTFT to supply the driving current to the light-emitting element 10 during the light-emitting phase. The anode of the light emitting element 10 is electrically connected to the second electrode of the driving transistor DTFT, and the cathode of the light emitting element 10 is electrically connected to the second power supply terminal ELVSS.

The light-emitting element includes, but is not limited to, an OLED, a Micro LED, a Mini LED, and other current-type driving elements. The driving transistor DTFT may be a P-channel transistor, and when a voltage difference between a gate of the driving transistor DTFT and a source S thereof is smaller than a threshold voltage thereof, the driving transistor DTFT is turned on; the driving transistor DTFT may be an N-channel transistor, and in this case, the driving transistor DTFT is turned on when a voltage difference between the gate and the source S of the driving transistor DTFT is greater than a threshold voltage thereof. For convenience of description, the embodiment of the present invention is exemplified by taking the driving transistor DTFT as a P-channel transistor.

In an alternative embodiment, the pixel circuit may sequentially perform an initialization phase, a threshold compensation phase, a data writing phase, and a light emitting phase in one driving period.

In the initialization stage, the initialization module 20 writes the initialization signal Vref to the first node N1 to initialize the gate of the driving transistor DTFT, and the light-emitting control module 60 transmits the first power signal Elvdd to the third node N3, so that the difference between the initialization signal Vref and the first power signal Elvdd is smaller than the threshold voltage Vth of the driving transistor DTFT, i.e. Vref-Elvdd < Vth, so as to ensure that the driving transistor DTFT is in a conductive state in preparation for the subsequent threshold compensation stage. In addition, in the initialization stage, the writing module 30 writes the data signal Vdata to the second node N2, and the storage module 50 stores the data signal Vdata written by the second node N2.

In the threshold compensation stage, the initialization module 20 continues to write the initialization signal Vref to the first node N1, and the potential of the third node N3 changes over time until the driving transistor DTFT is in the on critical state, i.e. the potential difference between the first node N1 and the third node N3 is the threshold voltage Vth of the driving transistor DTFT, and the potential of the third node N3 does not change any more; and, since the potential of the first node N1 is the initialization signal Vref, the potential of the third node N3 is kept at Vref-Vth when the driving transistor DTFT is in the on critical state, so that the threshold voltage can be stored in the memory module 50. Meanwhile, the writing module 30 continues to write the data signal Vdata to the second node N2 to maintain the stability of the potential of the second node N2.

In the data writing stage, the isolation module 40 turns on the path between the first node N1 and the second node N2, and the initialization module 20 does not write the initialization signal Vref to the first node N1 any more, so that the data signal Vdata of the second node N2 stored in the storage module 50 is transmitted to the first node N1, and the potential of the first node N1 is changed from Vref to Vdata.

In the light emitting stage, the light emitting control module 60 transmits the first power signal Elvdd to the third node N3 again, and at this time, the variation of the third node N3 is Elvdd-vref+vth, and since the memory module 50 controls the potential of the second node N2 to have the same variation as the potential of the third node N3, the potential of the second node N2 increases Elvdd-vref+vth along with the increase of the third node N3, and the potential of the second node N2 becomes vdata+ Elvdd-vref+vth. The isolation module 40 continues to turn on the path between the first node N1 and the second node N2, so that the potential of the first node N1 becomes Vdata+ Elvdd-Vref+Vth, i.e. the gate potential of the driving transistor DTFT is Vdata+ Elvdd-Vref+Vth. Because the potential of the third node N3 is the first power signal Elvdd, that is, the potential of the first pole of the driving transistor DTFT becomes Elvdd, the potential difference between the gate and the first pole of the driving transistor DTFT is smaller than the threshold voltage Vth thereof, so that the driving transistor DTFT is in the on state again, and generates the driving current Id according to the potential difference between the gate and the first pole thereof, at this time, the driving transistor DTFT is in the saturated state, and the working current is id=k ((vdata+ Elvdd-vref+vth) -Vdd-Vth) ², where k is a coefficient, that is, the generated driving current id=k (Vdata-Vref) ², so that the pixel circuit can realize compensation of the threshold voltage of any magnitude of the driving transistor DTFT, and the threshold drift of the driving transistor DTFT cannot occur due to aging and process steps of the driving transistor DTFT, thereby further improving the light emitting stability of the light emitting element. It can be understood that, in general, the first power signal Elvdd provided by the light-emitting control module 60 is a positive power signal, the second power terminal ELVSS provides the second power signal Elvss as a negative power signal, and when the first power signal Elvdd to the second power signal Elvss form a conductive path, the driving transistor DTFT generates a driving current according to the voltage difference between the data signal Vdata written into the gate thereof and the initialization signal Vref, so as to drive the light-emitting element 10 to emit light.

Specifically, in the initialization phase and the threshold compensation phase, the isolation module 40 breaks the path between the first node N1 and the second node N2, so that the data signal Vdata written by the second node N2 is not transmitted to the first node N1, i.e. not transmitted to the gate of the driving transistor DTFT, and thus the driving transistor DTFT is not caused to generate the driving current for controlling the light emitting element 10 to emit light. In the data writing stage and the light emitting stage, the isolation module 40 turns on the path between the first node N1 and the second node N2, so that the data signal Vdata written by the second node N2 is transmitted to the first node N1, the data signal Vdata is provided to the gate of the driving transistor DTFT, and when the light emitting control module 60 provides the first power signal Elvdd to the first pole of the driving transistor DTFT, the driving transistor DTFT is enabled to generate the driving current, so as to control the light emitting element 10 to emit light, in other words, the isolation module 60 plays a role of light emitting control.

In the embodiment of the invention, by arranging the initializing module, the isolating module and the grid electrode of the driving transistor to be electrically connected with the first node, the writing module, the isolating module and the storage module to be electrically connected with the second node, the storage module, the light-emitting control module and the first electrode of the driving transistor to be electrically connected with the third node, and the second electrode of the driving transistor to be electrically connected with the anode of the light-emitting element, the cathode of the light-emitting element is electrically connected with the second power end, so that the pixel circuit provides initializing signals for the first node in the initializing stage, the writing module writes data signals into the second node and stores the data signals in the storage module, and the light-emitting control module provides first power signals for the third node, and can control the driving transistor to be conducted under the control of the initializing signals and the first power signals. In the threshold compensation stage, the light-emitting control module stops providing the first power supply signal to the third node, so that the threshold voltage of the driving transistor is compensated into the memory module. In the data writing stage, the isolation module conducts the path between the second node and the first node, so that the data signal written by the second node is transmitted to the first node, namely, is written into the grid electrode of the driving transistor. In the light emitting stage, the light emitting control module controls the first power supply signal to be transmitted to the third node, and under the action that the storage module controls the potential of the second node to have the same variation as the potential of the third node, the first node also has the same variation as the potential of the third node. Therefore, the compensation of the threshold voltage of the drive transistor with any size can be realized, the threshold drift of the drive transistor caused by the aging of the drive transistor, the process and the like can not be caused, the size of the drive current generated by the drive transistor is not influenced, and the light-emitting stability of the light-emitting element is further improved.

Optionally, fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 2, the initialization module 20 includes a first transistor M1, a first signal terminal VREF, and a first scan terminal S1; the gate of the first transistor M1 is electrically connected to the first scan terminal S1, the first pole of the first transistor M1 is electrically connected to the first signal terminal VREF, and the second pole of the first transistor M1 is electrically connected to the first node N1.

The first transistor M1 is exemplified as a P-channel transistor. In the initialization phase and the threshold compensation phase, the first scan signal S1 provided by the first scan terminal S1 may be a low level signal, and the first transistor M1 is controlled to be in a conductive state, so that the initialization signal VREF provided by the first signal terminal VREF is written into the first node N1 through the first transistor M1. In the data writing stage and the light emitting stage, the first scan signal S1 provided by the first scan terminal S1 may be a high level signal, so as to control the first transistor M1 to be in an off state, and at this time, the first signal terminal VREF no longer provides the initialization signal VREF for the first node N1.

It should be noted that, the first transistor M1 may also be an N-channel transistor, at this time, when the first scanning signal S1 of the first scanning end S1 is at a high level, the first transistor M1 is controlled to be turned on, and when the first scanning signal S1 of the first scanning end S1 is at a low level, the first transistor M1 is controlled to be turned off, which is not described in detail herein, and may be set according to actual requirements.

Optionally, with continued reference to fig. 2, the writing module 30 includes a writing transistor M2, a DATA signal terminal DATA, and a second scanning terminal S2; the gate of the write transistor M2 is electrically connected to the second scan terminal S2, the first pole of the write transistor M2 is electrically connected to the DATA signal terminal DATA, and the second pole of the write transistor M2 is electrically connected to the second node N2.

The write transistor M2 is exemplified as a P-channel transistor. In the initialization phase and the threshold compensation phase, the second scan signal S2 provided by the second scan terminal S2 may be a low level signal, and the write transistor M2 is controlled to be in a conductive state, so that the DATA signal Vdata provided by the DATA signal terminal DATA is written into the second node N2 through the write transistor M2, and the DATA signal Vdata written in the second node N2 is stored by the memory module 50. In the data writing stage and the light emitting stage, the second scan signal S2 provided by the second scan terminal S2 may be a high level signal, so as to control the writing transistor M2 to be in an off state.

It should be noted that, the writing transistor M2 may be an N-channel transistor, and at this time, when the second scanning signal S2 of the second scanning end S2 is at a high level, the writing transistor M2 is controlled to be turned on, and when the second scanning signal S2 of the second scanning end S2 is at a low level, the writing transistor M2 is controlled to be turned off, which will not be described in detail herein, and may be set according to practical requirements.

In an alternative embodiment, fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 3, the channel types of the first transistor M1 and the writing transistor M2 are the same, and the first scan S1 end is multiplexed to the second scan end S2.

Specifically, since the first transistor M1 and the writing transistor M2 are both in an on state in the initialization stage and the threshold compensation stage, and are both in an off state in the data writing stage and the light emitting stage, the first transistor M1 and the writing transistor M2 have the same on or off state, so that the first transistor M1 and the writing transistor M2 may be P-channel transistors or N-channel transistors, and the first scan S1 end may be multiplexed to the second scan end S2, so as to reduce the number of scan signals provided to the pixel circuit, simplify the structure of the circuit generating the scan signals, thereby reducing the occupied area of the circuit generating the scan signals, and generally, the circuit generating the scan signals is disposed in the non-display area, which is beneficial to narrow frame of the display panel including the pixel circuit when the occupied area of the circuit generating the scan signals is reduced.

Optionally, fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, as shown in fig. 4, the isolation module 40 includes an isolation transistor M3 and a third scan terminal S3, a gate of the isolation transistor M3 is electrically connected to the third scan terminal S3, a first pole of the isolation transistor M3 is electrically connected to the first node N1, and a second pole of the isolation transistor M3 is electrically connected to the second node N2.

The isolation transistor M3 is exemplified as a P-channel transistor. In the initialization stage and the threshold compensation stage, the third scan signal S3 provided by the third scan terminal S3 is a high level signal, and controls the isolation transistor M3 to be in an off state, so that a path between the first node N1 and the second node N2 is disconnected, and thus the data signal Vdata written by the second node N2 is not transmitted to the first node N1, i.e. is not written into the gate of the driving transistor DTFT, and the grabbing of the threshold of the driving transistor DTFT in the threshold compensation stage is avoided. In the data writing stage and the light emitting stage, the third scan signal S3 provided by the third scan terminal S3 is a low level signal, at this time, the isolation transistor M3 is in a conducting state, i.e. the path between the first node N1 and the second node N2 is conducting, the first node N1 and the second node N2 have the same voltage, i.e. the data signal Vdata written by the second node N2 is transmitted to the first node N1, the data signal Vdata is provided for the gate of the driving transistor DTFT, and when the light emitting control module 60 provides the first power signal Elvdd for the first pole of the driving transistor DTFT, the driving transistor DTFT generates the driving current, so as to control the light emitting element 10 to emit light. It can be understood that the on-time of the isolation transistor M3 can control the light emitting time of the light emitting element 10, and since the luminance of the light emitting element 10 is related to the integral of the light emitting luminance thereof with respect to time, the light emitting luminance of the light emitting element 10 can also be precisely controlled by controlling the on-time of the isolation transistor M3.

It should be noted that, the isolation transistor M3 may also be an N-channel transistor, and at this time, when the third scanning signal S3 of the third scanning end S3 is at a high level, the isolation transistor M3 is controlled to be turned on, and when the third scanning signal S3 of the third scanning end S3 is at a low level, the writing transistor M2 is controlled to be turned off, which is not described in detail herein, and may be set according to practical requirements.

In an alternative embodiment, fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 5, channel types of the first transistor M1 and the isolation transistor M3 are different, and the first scan end S1 is multiplexed to be the third scan end S3.

Specifically, since the first transistor M1 is in an on state in both the initialization phase and the threshold compensation phase, is in an off state in both the data writing phase and the light emission phase, and the isolation transistor M3 is in an off state in both the initialization phase and the threshold compensation phase, and is in an on state in both the data writing phase and the light emission phase, the first transistor M1 and the isolation transistor M3 have opposite on or off conditions. In this way, fig. 5 illustrates that the first transistor M1 may be an N-channel transistor, for example, an oxide transistor, the isolation transistor M3 may be a P-channel transistor, for example, a low-temperature polysilicon transistor, and since the duration of the light emitting period is longer, the first transistor M1 is set to be an oxide transistor, and the oxide transistor has a lower turn-off characteristic and a smaller leakage current, the stability and accuracy can be continuously maintained after the data signal Vdata of the second node N2 is transmitted to the first node N1 in the light emitting control period, the stable light emission of the light emitting element 10 is prevented from being affected due to the fluctuation of the potential of the gate electrode of the driving transistor DTFT, the display effect of the display panel including the pixel circuit is improved, and meanwhile, the display with a lower frequency can be realized, and the power consumption of the display panel is reduced.

Further, with continued reference to fig. 5, the first scan terminal S1 is multiplexed to the third scan terminal S3, so that the number of scan signals provided to the pixel circuit can be reduced, and the structure of the circuit for generating the scan signals can be simplified, so that the occupied area of the circuit for generating the scan signals can be reduced.

It should be understood that, without any specific explanation, the pixel circuits provided in the following embodiments are all exemplified by, but not limited to, the first transistor M1 may be an N-channel transistor, the isolation transistor M3 may be a P-channel transistor, and the first scan terminal S1 is multiplexed to the third scan terminal S3.

Optionally, fig. 6 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present invention, as shown in fig. 6, the light-emitting control module 60 includes a light-emitting control transistor M4, a first power supply terminal ELVDD and a light-emitting control terminal EM; the gate of the light emission control transistor M4 is electrically connected to the light emission control terminal EM, the first electrode of the light emission control transistor M4 is electrically connected to the first power supply terminal ELVDD, and the second electrode of the light emission control transistor M4 is electrically connected to the third node N3.

The light emission control transistor M4 is exemplified as a P-channel transistor. In the initialization phase and the light emitting phase, the light emitting control signal EM provided by the light emitting control terminal EM may be a low level signal, controlling the light emitting control transistor M4 to be in an on state, so that the first power signal Elvdd of the first power terminal ELVDD is written into the third node N3 through the light emitting control transistor M4, and in the threshold compensation phase and the data writing phase, the light emitting control signal EM provided by the light emitting control terminal EM may be a high level signal, controlling the light emitting control transistor M4 to be in an off state.

It should be noted that, the light emitting control transistor M4 may be an N-channel transistor, at this time, when the light emitting control signal EM of the light emitting control terminal EM is at a high level, the light emitting control transistor M4 is controlled to be turned on, and when the light emitting control signal EM of the light emitting control terminal EM is at a low level, the light emitting control transistor M4 is controlled to be turned off, which is not described in detail herein, and may be set according to actual requirements.

Optionally, fig. 7 is a schematic structural diagram of a pixel circuit according to another embodiment of the present invention, as shown in fig. 7, further including a reset module 70, where the reset module 70 and an anode of the light emitting element 10 are coupled to a fourth node N4; the Reset module 70 is configured to write a Reset signal Reset to the fourth node N4 during a Reset phase.

It will be appreciated that, before the light-emitting stage, the Reset stage may also be entered, where the Reset module 70 can write a Reset signal Reset into the anode of the light-emitting element 10 to Reset the light-emitting element 10, and clear the potential written into the anode of the light-emitting element 10 in the previous driving period, so as to prevent the potential written into the anode of the light-emitting element 10 in the previous driving period from affecting the display light-emitting brightness of the light-emitting element 10 in the current driving period, so that the light-emitting element 10 can emit light accurately in each driving period.

It should be noted that, the reset phase may be located at any time period before the light-emitting phase of the current driving period, for example, the reset phase T0 may be performed simultaneously with any one of the initialization phase, the threshold compensation phase, or the data writing phase, so as to shorten the duration of the non-light-emitting phase in one driving period, and prevent the overall display light-emitting brightness of the light-emitting element 10 from being affected due to the longer time of the non-light-emitting phase in one driving period.

Optionally, with continued reference to fig. 7, the RESET module 70 includes a RESET transistor M5, a RESET signal terminal RESET, and a RESET control terminal S4, where a gate of the RESET transistor M5 is electrically connected to the RESET control terminal S4, a first pole of the RESET transistor M5 is electrically connected to the RESET signal terminal RESET, and a second pole of the RESET transistor M5 is electrically connected to the fourth node N4.

The reset transistor M5 is exemplified as a P-channel transistor. In the RESET phase, the RESET control signal S4 provided by the RESET control terminal S4 may be at a low level, and controls the RESET transistor M5 to be in an on state, so that the RESET signal RESET provided by the RESET signal terminal RESET is written into the fourth node N4 to RESET the light emitting element 10, and in the light emitting phase, the RESET control signal S4 provided by the RESET control terminal S4 may be at a high level, and controls the RESET transistor M5 to be in an off state, so that the light emitting element 10 emits light according to the driving current generated by the driving transistor DTFT.

It should be noted that, the reset transistor M5 may also be an N-channel transistor, and at this time, when the reset control signal S4 of the reset control terminal S4 is at a high level, the reset transistor M5 is controlled to be turned on, and when the reset control signal S4 of the reset control terminal S4 is at a low level, the reset transistor M5 is controlled to be turned off, which is not described in detail herein, and may be set according to actual requirements.

Fig. 8 is a driving timing chart of a pixel circuit according to an embodiment of the present invention, and in conjunction with fig. 7 and 8, an initialization phase is multiplexed as a reset phase.

In the reset phase T0 and the initialization phase T1, the first scan signal S1 (high level) provided by the first scan terminal S1 controls the first transistor M1 to be turned on, and simultaneously controls the isolation transistor M3 to be turned off, the initialization signal VREF of the first signal terminal VREF is written into the first node N1, the light emission control signal EM (low level) of the light emission control terminal EM controls the light emission control transistor M4 to be turned on, so that the first power signal Elvdd of the first power terminal ELVDD is written into the third node N3, and thus, by making the difference between the initialization signal VREF and the first power signal Elvdd smaller than the threshold voltage Vth of the driving transistor DTFT, the driving transistor DTFT can be ensured to be in an on state to prepare for the subsequent threshold compensation phase. Meanwhile, the second scan signal S2 (low level) provided by the second scan terminal S2 controls the write transistor M2 to be turned on, writes the DATA signal Vdata of the DATA signal terminal DATA to the second node N2, and stores the DATA signal Vdata written by the second node N2 by the storage module 50. The RESET control signal S4 (low level) of the RESET control terminal S4 controls the RESET transistor M5 to be in a conductive state, so that the RESET signal RESET supplied from the RESET signal terminal RESET is written to the fourth node N4 to RESET the light emitting element 10.

In the threshold compensation phase T2, the first scan signal S1 (high level) provided by the first scan terminal S1 continuously controls the first transistor M1 to be turned on, and controls the isolation transistor M3 to be turned off, and the first scan signal S2 (low level) provided by the second scan terminal S2 continuously controls the write transistor M2 to be turned on. The reset control signal S4 (high level) of the reset control terminal S4 controls the reset transistor M5 to be in a conductive state. The emission control signal EM (high level) of the emission control terminal EM controls the emission control transistor M4 to be turned off. Over time, the third bit of the third node N3 gradually decreases until the driving transistor DTFT is in a critical state of being turned on, that is, when the potential difference between the first node N1 and the third node N3 is the threshold voltage Vth of the driving transistor DTFT, the potential of the third node N3 is no longer changed; and because the potential of the first node N1 is the initialization signal Vref, the potential of the third node N3 is kept at Vref-Vth when the driving transistor DTFT is in the on critical state.

In the data writing stage T3, the first scan signal S1 (low level) provided by the first scan terminal S1 controls the first transistor M1 to be turned off, and simultaneously controls the isolation transistor M3 to be turned on, so that the data signal Vdata of the second node N2 stored in the memory module 50 is transmitted to the first node N1, and the potential of the first node N1 is changed from Vref to Vdata. Meanwhile, the second scan signal S2 (high level) provided by the second scan terminal S2 controls the write transistor M2 to be turned off.

In the light emitting stage T4, the light emission control signal EM (low level) of the light emission control terminal EM controls the light emission control transistor M4 to be turned on, so that the first power signal Elvdd of the first power terminal ELVDD is written into the third node N3, at this time, the variation of the third node N3 is Elvdd-vref+vth, and since the storage module 50 controls the potential of the second node N2 to have the same variation as the potential of the third node N3, the potential of the second node N2 increases Elvdd-vref+vth along with the third node N3, the potential of the second node N2 becomes vdata+ Elvdd-vref+vth, and the potential of the first node N1 becomes vdata+ Elvdd-vref+vth, and the potential of the third node N3 is the first power signal Elvdd, so that the driving current Id, i.e., id=k (Vdata-Vref) ², can be generated between the gate and the first electrode of the driving transistor DTFT, and the driving current DTFT is independent of the threshold voltage thereof.

Based on the same concept, the embodiment of the present invention further provides a method for driving a pixel circuit, which is used for driving the pixel circuit in any of the above embodiments, and fig. 9 is a flowchart of a method for driving a pixel circuit according to the embodiment of the present invention, as shown in fig. 9, where the method includes:

S101, in an initialization stage, an initialization module provides an initialization signal for a first node; the writing module writes the data signal into the second node and stores the data signal in the storage module; the light-emitting control module provides a first power signal to the third node.

S102, in a threshold compensation stage, the initialization module controls the potential of the first node to be kept as an initialization signal, the writing module controls the second node to be kept as a data signal, the light-emitting control module stops providing the first power supply signal to the third node, and the threshold voltage of the driving transistor is compensated into the storage module.

S103, in the data writing stage, the isolation module conducts a passage between the second node and the first node.

S104, in the light emitting stage, the light emitting control module controls the first power supply signal to be transmitted to the third node. The storage module controls the potential of the second node to have the same variation as the potential of the third node; the isolation module controls the second node and the first node to keep a conducting state; the driving transistor supplies a driving current to the light emitting element according to a potential difference between the first node and the third node.

The pixel circuit provided by any embodiment of the present invention has the corresponding technical features and beneficial effects of the pixel circuit, and the details of the driving method of the pixel circuit, which are not described in detail in the embodiments of the driving method of the pixel circuit, can be referred to the description of the pixel circuit, and are not described in detail herein; similarly, the pixel circuit of the embodiment of the present invention also has a functional module and beneficial effects that can execute the driving method of the complex pixel circuit provided in the embodiment of the present invention, and the details that are not described in detail in the embodiment of the pixel circuit can refer to the description of the driving method of the pixel circuit above, which is not repeated here.

Based on the same inventive concept, an embodiment of the present invention further provides a display panel, including the pixel circuit 100 provided in any one of the above embodiments arranged in an array. Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention, as shown in fig. 10, the display panel 100 has corresponding technical features and advantages of the pixel circuit 100, which are not described in detail in the embodiment of the display panel 200, and reference is made to the above description of the pixel circuit, and thus the description is omitted herein.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 11 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and referring to fig. 11, the display device 300 includes the display panel 200 provided in any embodiment of the present invention. The display device 300 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 11, or any electronic product with a display function, including but not limited to the following categories: the embodiment of the invention is not particularly limited to a television, a notebook computer, a display, a tablet computer, a digital camera, a smart bracelet, smart glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (12)

1. A pixel circuit, comprising: the device comprises a driving transistor, a light-emitting element, an initialization module, a writing module, an isolation module, a storage module and a light-emitting control module;

The initialization module and the grid electrode of the driving transistor are electrically connected to a first node; the initialization module is used for writing an initialization signal into the first node in an initialization stage and a threshold compensation stage;

The writing module is electrically connected with the storage module and the second node, and the storage module is also electrically connected with the first electrode of the driving transistor and the third node; the writing module is used for writing a data signal to the second node in the initialization stage and the threshold compensation stage; the storage module is used for storing the data signals written into the second node in the initialization stage and the threshold compensation stage, storing the threshold voltage of the driving transistor in the threshold compensation stage, and controlling the potential of the second node to have the same variation with the potential of the third node in the light-emitting stage;

The isolation module is electrically connected between the first node and the second node; the isolation module is used for disconnecting the passage between the first node and the second node in the initialization stage and the threshold compensation stage, and conducting the passage between the second node and the first node in the data writing stage and the light-emitting stage;

The light-emitting control module is electrically connected to the third node; the light-emitting control module is used for transmitting a first power supply signal to the third node in the initialization stage and controlling the time for the driving transistor to provide driving current for the light-emitting element in the light-emitting stage;

the anode of the light emitting element is electrically connected with the second electrode of the driving transistor, and the cathode of the light emitting element is electrically connected with the second power supply terminal.

2. The pixel circuit of claim 1, wherein the initialization module comprises a first transistor, a first signal terminal, and a first scan terminal; the grid electrode of the first transistor is electrically connected with the first scanning end, the first pole of the first transistor is electrically connected with the first signal end, and the second pole of the first transistor is electrically connected with the first node.

3. The pixel circuit of claim 2, wherein the write module comprises a write transistor, a data signal terminal, and a second scan terminal; the grid electrode of the writing transistor is electrically connected with the second scanning end, the first electrode of the writing transistor is electrically connected with the data signal end, and the second electrode of the writing transistor is electrically connected with the second node.

4. A pixel circuit according to claim 3, wherein the channel types of the first transistor and the write transistor are the same, and the first scan terminal is multiplexed to the second scan terminal.

5. The pixel circuit of claim 2, wherein the isolation module comprises an isolation transistor and a third scan terminal, the gate of the isolation transistor is electrically connected to the third scan terminal, the first pole of the isolation transistor is electrically connected to the first node, and the second pole of the isolation transistor is electrically connected to the second node.

6. The pixel circuit according to claim 5, wherein channel types of the first transistor and the isolation transistor are different, and the first scan terminal is multiplexed to the third scan terminal.

7. The pixel circuit of claim 1, wherein the light emission control module comprises a light emission control transistor, a first power supply terminal, and a light emission control terminal; the grid electrode of the light-emitting control transistor is electrically connected with the light-emitting control end, the first electrode of the light-emitting control transistor is electrically connected with the first power end, and the second electrode of the light-emitting control transistor is electrically connected with the third node.

8. The pixel circuit of claim 1, further comprising a reset module coupled to the anode of the light emitting element at a fourth node; the reset module is used for writing a reset signal to the fourth node in a reset stage.

9. The pixel circuit of claim 8, wherein the reset module comprises a reset transistor, a reset signal terminal, and a reset control terminal, a gate of the reset transistor is electrically connected to the reset control terminal, a first pole of the reset transistor is electrically connected to the reset signal terminal, and a second pole of the reset transistor is electrically connected to the fourth node.

10. A driving method of a pixel circuit for driving the pixel circuit according to any one of claims 1 to 9, comprising:

An initialization stage, wherein the initialization module provides an initialization signal for the first node; the writing module writes the data signal into the second node and stores the data signal in the storage module; the light-emitting control module provides a first power supply signal to the third node;

A threshold compensation stage, wherein the initialization module controls the potential of the first node to be kept as the initialization signal, the writing module controls the second node to be kept as the data signal, the light-emitting control module stops providing a first power supply signal to the third node, and the threshold voltage of the driving transistor is compensated into the storage module;

a data writing stage, wherein the isolation module conducts a passage between the second node and the first node;

The light-emitting stage, the light-emitting control module controls the first power supply signal to be transmitted to the third node; the storage module controls the potential of the second node to have the same variation as the potential of the third node; the isolation module controls the second node and the first node to keep a conducting state; the driving transistor supplies a driving current to the light emitting element according to a potential difference between the first node and the third node.

11. A display panel comprising a plurality of pixel circuits according to any one of claims 1 to 9 arranged in an array.

12. A display device comprising the display panel according to claim 11.