CN117992386A - Method and equipment for flexibly configuring signal processing module based on PCIE bus - Google Patents

Abstract

The invention discloses a method and equipment for flexibly configuring a signal processing module based on a PCIE bus, which aim at solving the problem that the fixed configuration of the CPU and the signal processing module of the traditional computer equipment cannot meet the CPU requirement.

Description

Method and equipment for flexibly configuring signal processing module based on PCIE bus

Technical Field

The invention belongs to the technical field of computer equipment, and particularly relates to a method and equipment for flexibly configuring a signal processing module based on a PCIE bus.

Background

PCI-Express (peripheral component interconnect express), PCIE for short, is a high-speed serial computer expansion bus standard, and is mainly used for expanding the data throughput of a computer system bus and improving the communication speed of equipment, and is used for connecting various devices in the computer system, including a display card, a network card, a sound card and the like.

PCIE is a full duplex connection bus, and the size of the transmission data is determined by the lane number lane. In general, 1 connection lane is designated as X1, each lane is made up of two pairs of data lines, one pair transmitting and one pair receiving, each pair containing two differential lines. I.e. X1 has only 1 lane,4 data lines, 1bit data transmission per direction per clock. By analogy, X2 has 2 lanes, consisting of 8 data lines, each clock transmitting 2 bits. Similarly, X12, X16, and X32 are also described.

When signal processing tasks are involved, the CPU is generally responsible for the control and management functions of the processing system, while the signal processing card is specifically responsible for processing and computing the signals. By using PCIE connection, the CPU may transmit data to be processed to the signal processing card, then perform related computing operations by the signal processing card, and return the result to the CPU or other device. PCIE connections provide high bandwidth and low latency data transfer capabilities, which are important for signal processing tasks that require processing large amounts of data.

However, the signal processing card equipped with each CPU is often designed in advance, and the corresponding processing card is installed as required, which is inconvenient if the signal processing card equipped with each CPU is to be changed. When the signal processing capability required by the CPU varies greatly with the change of the processing task, it is a technical difficulty to temporarily expand the signal processing capability. Therefore, the solution of flexibly configuring the signal processing module by using PCIE buses by multiple CPUs in the system is a technical problem that needs to be solved.

Disclosure of Invention

The invention aims to provide a method and equipment for flexibly configuring a signal processing module based on a PCIE bus, which can meet the change of the signal processing requirements of a plurality of CPUs when computer equipment works.

In order to solve the problems, the technical scheme of the invention is as follows:

A method for flexibly configuring a signal processing module based on a PCIE bus comprises the following steps:

The PCIE bridge chip is configured, two main processing modules are used as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time;

When the calculated amount of any signal processing module exceeds the load, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, and executing switching of the other signal processing module to the current main processing module so as to meet the calculation requirement of the current main processing module;

Or when any main processing module fails, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, switching the signal processing module under the failed main processing module to another main processing module, sending information to the main processing module which normally works, and waking up a backup program of the other main processing module in the main processing module to enable the switched signal processing module to operate.

According to an embodiment of the present invention, the PCIE bridge is configured to support two host paths, each host path running independently; and each host supports mounting two signal processing modules.

According to an embodiment of the present invention, registers of PCIE bridge slices are configured to support switching of signal processing modules.

A device for flexibly configuring a signal processing module based on a PCIE bus, comprising: two main processing modules, PCIE bridge chips and two signal processing modules;

The PCIE bridge chip is configured to support two main processing modules as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time;

When the calculated amount of any signal processing module exceeds the load, the PCIE bridge chip receives the control instruction transmitted through the I ² C bus and executes switching of the other signal processing module to the current main processing module, so that the calculation requirement of the current main processing module is met;

Or when any main processing module fails, the PCIE bridge chip receives a control instruction transmitted through the I ² C bus, switches the signal processing module under the failed main processing module to another main processing module, sends information to the main processing module which normally works, wakes up the backup program of the other main processing module in the main processing module, and enables the switched signal processing module to operate.

By adopting the technical scheme, the invention has the following advantages and positive effects compared with the prior art:

According to the method for flexibly configuring the signal processing module based on the PCIE bus, aiming at the problem that the fixed configuration of the CPU and the signal processing module of the traditional computer equipment cannot meet the CPU requirement, the flexible configuration of the signal processing module can be realized without changing hardware connection by configuring PCIE bridge chips, the utilization rate of the signal processing module is increased, the method is suitable for various application requirements and emergency situations, and the signal processing capability of a single CPU is improved.

Drawings

Fig. 1 is a flowchart of a method for flexibly configuring a PCIE bus-based signal processing module according to an embodiment of the present invention;

Fig. 2 is a device configuration diagram of flexible configuration of a PCIE bus-based signal processing module according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a PCIE bridge supported mode according to an embodiment of the present invention.

Detailed Description

The method and the device for flexibly configuring the signal processing module based on the PCIE bus are further described in detail below with reference to the accompanying drawings and the specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims.

The embodiment provides a method for flexibly configuring a signal processing module based on a PCIE bus, which comprises the following steps:

The PCIE bridge chip is configured, two main processing modules are used as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time;

When the calculated amount of any signal processing module exceeds the load, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, and executing switching of the other signal processing module to the current main processing module so as to meet the calculation requirement of the current main processing module;

Or when any main processing module fails, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, switching the signal processing module under the failed main processing module to another main processing module, sending information to the main processing module which normally works, and waking up a backup program of the other main processing module in the main processing module to enable the switched signal processing module to operate.

Specifically, referring to fig. 1, the method is applied to a computer device, and mainly involves two main processors (CPUs), a PCIE bridge and two signal processing modules (computing accelerator cards). The two main processors CPU are host ends of PCIE, are connected to PCIE bridge chips, and are connected with two signal processing modules as slave devices.

Referring to fig. 2, in an embodiment, a VPX board is used as a CPU board, two signal processing chips are connected to PCIE bridge pieces through PCIE buses, the bridge pieces connect two buses to a P2 interface, and the P2 interface is connected to boards of two CPUs through a chassis base plate.

In general, two main processors respectively control a signal processing device through PCIE bridge slices.

In special cases, one main processor may mount two signal processing devices, and the other main processor may not mount a signal processing device.

In an embodiment, as shown in fig. 3, the PCIE bridge slices used support two hosts and can be used independently, and each host supports mounting two slave devices. PCIE bridge slices configure different modes, and related registers need to be modified, and configuration is modified through an I2C interface. For example, by writing an I ² C instruction into an EEPROM inside the PCIE bridge, a register with a length of 4 is provided in the EEPROM for configuring PCIE bridge channel allocation, and by changing the value of the register, configuration of different modes of the PCIE bridge is realized.

The general working state means that a signal processing module is mounted under each main processing module, each main processing module is accessed into two independent channels of the PCIE bridge piece as host, and the signal processing modules are directly mounted into the two channels.

In a special case, a main processing chip needs high computational power, one signal processing module cannot meet the requirement, and two signal processing modules are required to be mounted on another main processor. Each main processor monitors the utilization rate of the signal processing equipment in real time, and when the requirement of the signal processing equipment exceeds the processing capacity of a single signal processing module, the I ² C transmits a command to the PCIE bridge chip, and one signal processing module is switched to the other main processor. Here, the switch instruction is sent by the BMC. The specific process is that the main processor analyzes the task and finds that the required processing capacity exceeds the capacity of a single signal processing module, then the main processor sends a signal to the BMC, and the BMC transmits an instruction to the PCIE bridge chip through the I2C to reconfigure the signal processing module.

Wherein, BMC full name Baseboard management controller is an embedded management microcontroller. The BMC is called a baseboard management controller (Baseboard Manager Controller, BMC for short) and ensures that the system is in a normal running state by monitoring the power supply, the temperature and the like of the system. The BMC can detect and manage the power supply and the temperature of the whole system, whether the equipment operates normally or not and the like, can detect the abnormality of the equipment and perform operations such as reset and the like.

In a second special case, one main processor fails, and the necessary functions are temporarily run on the other main processor, and both signal processing modules need to be mounted on the other main processor. In order to cope with the fault situation of one main processor, the necessary working program running on the other main processor is backed up in both main processors, and when the fault happens, the working tasks of the two processors are run on the same processor. When one main processor fails, the BMC of the whole system detects the failed main processor, transmits information to the PCIE bridge chip through the I ² C, switches the signal processing module to the main processor which normally works, and transmits a signal to the main processor which normally works, and the processor wakes up a backup program of the failed processor, temporarily runs on the normal processor and maintains the system function.

Correspondingly, the device for flexibly configuring the signal processing module based on the PCIE bus, which is generated according to the method for flexibly configuring the signal processing module based on the PCIE bus, includes: two main processing modules, PCIE bridge chip and two signal processing modules. The PCIE bridge chip is configured to support two main processing modules as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time.

When the calculated amount of any signal processing module exceeds the load, the PCIE bridge chip receives the control instruction transmitted through the I ² C bus and executes the switching of the other signal processing module to the current main processing module, so that the calculation requirement of the current main processing module is met.

Or when any main processing module fails, the PCIE bridge chip receives a control instruction transmitted through the I ² C bus, switches the signal processing module under the failed main processing module to another main processing module, sends information to the main processing module which normally works, wakes up a backup program of the other main processing module in the main processing module, and enables the switched signal processing module to operate.

In summary, the method for flexibly configuring the signal processing module based on the PCIE bus provided by the embodiment aims at the problem that the existing fixed configuration of the CPU and the signal processing module of the computer device cannot meet the CPU requirement, and by configuring the PCIE bridge, flexible configuration of the signal processing module can be realized without changing hardware connection, the utilization rate of the signal processing module is increased, various application requirements and emergency situations are adapted, and the signal processing capability of a single CPU is improved.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is within the scope of the appended claims and their equivalents to fall within the scope of the invention.

Claims (4)

1. A method for flexibly configuring a signal processing module based on a PCIE bus is characterized by comprising the following steps:

The PCIE bridge chip is configured, two main processing modules are used as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time;

When the calculated amount of any signal processing module exceeds the load, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, and executing switching of the other signal processing module to the current main processing module so as to meet the calculation requirement of the current main processing module;

Or when any main processing module fails, transmitting a control instruction to the PCIE bridge chip through the I ² C bus, switching the signal processing module under the failed main processing module to another main processing module, sending information to the main processing module which normally works, and waking up a backup program of the other main processing module in the main processing module to enable the switched signal processing module to operate.

2. The method of flexible configuration of PCIE bus-based signal processing module of claim 1 wherein said PCIE bridge is configured to support two host paths, each host path running independently; and each host supports mounting two signal processing modules.

3. The method for flexibly configuring a PCIE bus-based signal processing module according to claim 2, wherein registers of a PCIE bridge slice are configured to support switching of the signal processing module.

4. The utility model provides a device of flexible configuration of signal processing module based on PCIE bus which characterized in that includes: two main processing modules, PCIE bridge chips and two signal processing modules;

The PCIE bridge chip is configured to support two main processing modules as host to be respectively connected into a first channel and a second channel of the PCIE bridge chip, and a signal processing module is mounted in each channel, so that the main processing module monitors the running condition of the signal processing module in real time;

When the calculated amount of any signal processing module exceeds the load, the PCIE bridge chip receives the control instruction transmitted through the I ² C bus and executes switching of the other signal processing module to the current main processing module, so that the calculation requirement of the current main processing module is met;

Or when any main processing module fails, the PCIE bridge chip receives a control instruction transmitted through the I ² C bus, switches the signal processing module under the failed main processing module to another main processing module, sends information to the main processing module which normally works, wakes up the backup program of the other main processing module in the main processing module, and enables the switched signal processing module to operate.