CN117977382A

CN117977382A - VCSEL unit, VCSEL chip manufacturing method and flexible panel

Info

Publication number: CN117977382A
Application number: CN202410121541.3A
Authority: CN
Inventors: 范纲维; 曾评伟; 沈宏勋
Original assignee: Quanzhou San'an Optical Communication Technology Co ltd
Current assignee: Quanzhou San'an Optical Communication Technology Co ltd
Priority date: 2024-01-29
Filing date: 2024-01-29
Publication date: 2024-05-03

Abstract

The application provides a VCSEL (vertical cavity surface emitting diode) unit, a VCSEL chip, a manufacturing method of the VCSEL chip and a flexible panel. The substrate of two adjacent VCSEL units is provided with a connecting area and a hollowed-out area, the connecting area is provided with a connecting part for connecting the substrates of the two adjacent VCSEL units, and the substrates of the two adjacent VCSEL units are integrally formed. In the VCSEL chip, a connecting part and a hollowed-out area are arranged between two adjacent VCSEL units, and the VCSEL units can be conveniently transferred in a huge amount on the basis of guaranteeing stable and non-offset positions of the VCSEL units through the weakened connecting structure.

Description

VCSEL unit, VCSEL chip manufacturing method and flexible panel

Technical Field

The invention relates to the technical field of semiconductors, in particular to a VCSEL unit, a VCSEL chip, a manufacturing method of the VCSEL chip and a flexible panel.

Background

Currently, a conventional VCSEL (Vertical-Cavity Surface-emitting laser) mainly includes a Vertical structure and a flip-chip structure, where a P electrode and a light emitting hole are both located on a front Surface of a chip, and an N electrode is located on a back Surface of the chip. In the flip-chip VCSEL, the P electrode and the N electrode are both positioned on the front surface of the chip, and the light emitting hole is positioned on the back surface of the chip. In the vertical VCSEL, the P electrode is located on the front side of the chip, the N electrode is located on the back side of the chip, and current flows in the P electrode from an electrode ring above the chip, which is prone to current non-uniformity. Therefore, currently, flip-chip VCSELs are more commonly used.

In the existing flip-chip VCSEL, a larger P electrode is generally arranged on the front surface of a chip, and a back-end module substrate is required to be customized according to packaging requirements under the conditions of high power requirements and specific requirements, so that a product meeting the requirements is formed, and the defects of poor flexibility and the like exist.

Disclosure of Invention

Objects of the present invention include, for example, providing a VCSEL unit, a VCSEL chip fabrication method, and a flexible panel that can meet the flexibility requirements of the product for the VCSEL unit.

Embodiments of the invention may be implemented as follows:

In a first aspect, the present invention provides a VCSEL chip comprising at least two VCSEL units, each of the VCSEL units comprising a substrate and an epitaxial structure disposed on the substrate;

The substrates of two adjacent VCSEL units are connected, and the epitaxial structures are arranged at intervals;

The substrate of two adjacent VCSEL units is provided with a connecting area and a hollowed-out area, the connecting area is provided with a connecting part for connecting the substrates of the two adjacent VCSEL units, and the substrates of the two adjacent VCSEL units are integrally formed.

In an alternative embodiment, the number of connections between the two adjacent VCSEL units is one or more;

In the case where there are a plurality of connection portions between the adjacent two VCSEL units, the plurality of connection portions are provided at intervals.

In an alternative embodiment, the cross section of the connecting portion is rectangular, or has a shape with notches on two opposite sides adjacent to the substrate.

In an alternative embodiment, the distance between the epitaxial structures of the two adjacent VCSEL units is 30 μm to 100 μm in the first direction in which the two adjacent VCSEL units are located.

In an alternative embodiment, the width of the connection portion is 20 μm to 30 μm in a second direction perpendicular to the first direction.

In an alternative embodiment, for each of the VCSEL units, a projection region of an epitaxial structure of the VCSEL unit onto a substrate is located inside an edge of the substrate, which extends beyond the projection region.

In an alternative embodiment, the portion of the substrate extending beyond the projection area has a width of 10 μm to 15 μm.

In an alternative embodiment, the epitaxial structure of each VCSEL unit includes a first bragg mirror on the substrate, a resonant cavity on a side of the first bragg mirror away from the substrate, and a second bragg mirror on a side of the resonant cavity away from the first bragg mirror;

The second Bragg reflector is provided with an oxidation limiting hole formed by surrounding an oxidation limiting layer, and a first electrode is arranged at a position corresponding to the oxidation limiting hole on the surface of the second Bragg reflector;

the epitaxial structure is provided with a groove, and a second electrode is arranged on the basis of the groove and the periphery of the second Bragg reflector, which is positioned on the first electrode.

In an alternative embodiment, the recess includes a plurality of through holes extending through the second Bragg reflector and the resonant cavity, and a plurality of sub-recesses in the first Bragg reflector;

The second Bragg reflector has a reflectivity that is greater than the reflectivity of the first Bragg reflector.

In a second aspect, the present invention provides a VCSEL unit comprising a substrate and an epitaxial structure on the substrate, the epitaxial structure comprising:

a first Bragg reflector on the substrate;

a resonant cavity positioned on one side of the first Bragg reflector away from the substrate;

a second Bragg reflector positioned on a side of the resonant cavity away from the first Bragg reflector;

In an alternative embodiment, the recess includes a plurality of through holes extending through the second Bragg reflector and the resonant cavity, and a plurality of sub-recesses in the first Bragg reflector.

In an alternative embodiment, the VCSEL unit further comprises an ion implantation isolation region located at an edge of the second bragg mirror;

The ion implantation concentration in the ion implantation isolation region is 1.95×10 ¹⁴/cm³-4.0×10¹⁴/cm³.

In an alternative embodiment, the VCSEL unit further comprises a first front side passivation layer, a second front side passivation layer and a back side passivation layer;

the first front passivation layer is positioned on the hole wall and the bottom of each through hole and the surface of the second Bragg reflector except the area where the second electrode is positioned;

the second front passivation layer is positioned above the first front passivation layer and is arranged around the periphery of the first electrode;

the back passivation layer is located on a side of the substrate away from the epitaxial structure.

In an alternative embodiment, the first front passivation layer has a thickness of 0.1 μm to 0.3 μm and the back passivation layer has a thickness of 0.1 μm to 0.3 μm.

In an alternative embodiment, the VCSEL unit further comprises a first contact metal layer and a second contact metal layer;

The first contact metal layer is positioned on the surface of the second Bragg reflector and corresponds to the oxidation limiting hole, and the first electrode is positioned on the first contact metal layer;

The second contact metal layer is located on the surface of the groove and the periphery of the first electrode of the second Bragg reflector, and the second electrode is located on the portion of the second contact metal layer located on the current conducting layer of the second Bragg reflector.

In a third aspect, the present invention provides a method for fabricating a VCSEL chip for forming a VCSEL chip in any of the above implementations, the method comprising:

providing at least two VCSEL units, wherein the substrates of two adjacent VCSEL units in the at least two VCSEL units are connected, and the epitaxial structures are connected;

Defining a cutting channel region on the epitaxial structure between the two adjacent VCSEL units, etching the epitaxial structure at the cutting channel region, and exposing the substrate below;

Defining a first area and a second area on the exposed substrate, cutting the substrate at the first area to remove the substrate at the first area to form a hollowed-out area, and reserving the substrate at the second area to form a connection area, wherein the connection area is provided with a connection part for connecting the substrates of the two adjacent VCSEL units.

In an alternative embodiment, the step of defining a scribe line region on the epitaxial structure between the two adjacent VCSEL units, etching the epitaxial structure at the scribe line region, and exposing the underlying substrate includes:

defining a cutting channel region on an epitaxial structure between the two adjacent VCSEL units by adopting a yellow light process;

And etching the epitaxial structure at the scribe line region by using a dry etching process to expose the underlying substrate.

In an alternative embodiment, the step of cutting the substrate at the first area to remove the substrate at the first area to form a hollowed-out area includes:

And cutting the substrate at the first area by adopting a laser cutting process to remove the substrate at the first area so as to form a hollowed-out area.

In a fourth aspect, the present invention provides a flexible panel, including a flexible substrate and a VCSEL chip in any of the above implementations, where the VCSEL chip is disposed on the flexible substrate.

The beneficial effects of the embodiment of the invention include, for example:

The application provides a VCSEL (vertical cavity surface emitting diode) unit, a VCSEL chip, a manufacturing method of the VCSEL chip and a flexible panel. The substrate of two adjacent VCSEL units is provided with a connecting area and a hollowed-out area, the connecting area is provided with a connecting part for connecting the substrates of the two adjacent VCSEL units, and the substrates of the two adjacent VCSEL units are integrally formed. In the VCSEL chip, a connecting part and a hollowed-out area are arranged between two adjacent VCSEL units, and the VCSEL units can be conveniently transferred in a huge amount on the basis of guaranteeing stable and non-offset positions of the VCSEL units by the weakened connecting mode.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a hierarchical structure of a VCSEL unit according to an embodiment of the present application;

fig. 2 is a schematic perspective view of a VCSEL unit according to an embodiment of the present application;

FIGS. 3-8 are schematic views of a device hierarchy formed by various steps in the fabrication of an implementation to form the VCSEL unit cell shown in FIG. 1;

Fig. 9 is a schematic diagram of a VCSEL chip according to an embodiment of the present application;

FIG. 10 is an enlarged schematic view of a portion A of FIG. 9;

FIG. 11 is a schematic view of the BB' cross-sectional hierarchical structure in FIG. 10;

FIG. 12 is a schematic view of the AA' cross-sectional hierarchical structure of FIG. 10.

Icon: 0-VCSEL chip; 01-linking region; 02-a hollowed-out area; 03-a connection; 00-VCSEL units; 10-a substrate; a 20-epi structure; 21-a first bragg mirror; 22-resonant cavity; 23-a second bragg mirror; 231-an oxidation limiting layer; 232-ion implantation of the isolation region; 24-groove; 241-through holes; 242-sub-grooves; 251-a first contact metal layer; 252-a second contact metal layer; 261-a first front side passivation layer; 262-a second front passivation layer; 263-a backside passivation layer; 27-a first electrode; 28-a second electrode.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.

It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.

Referring to fig. 1, a schematic level diagram of a VCSEL unit 00 according to an embodiment of the present application is shown, where the VCSEL unit 00 includes a substrate 10 and an epitaxial structure 20 formed on the substrate 10.

Wherein the epitaxial structure 20 comprises a first bragg mirror 21 on the substrate 10, a resonant cavity 22 on a side of the first bragg mirror 21 remote from the substrate 10, and a second bragg mirror 23 on a side of the resonant cavity 22 remote from the first bragg mirror 21. Wherein the reflectivity of the second bragg mirror 23 is greater than the reflectivity of the first bragg mirror 21. In the embodiment of the present invention, the first bragg mirror 21 is an N-type bragg mirror, and the second bragg mirror 23 is a P-type bragg mirror. The second bragg reflector 23 has an oxidation limiting hole surrounded by the oxidation limiting layer 231, and the oxidation limiting hole defines a light emitting region.

In this example, the aperture of the oxidation limiting aperture is 8 μm to 20 μm, i.e., the width of the light-exiting region is 8 μm to 20 μm. In this embodiment, the light emitting direction of the VCSEL unit 00 is the back light emitting direction. After the VCSEL unit 00 is turned on, light will be emitted from the light exit region and out of the back side of the VCSEL unit 00.

A first electrode 27 is provided at a position corresponding to the oxidation limiting hole on the surface of the second bragg mirror 23. Furthermore, a recess 24 is provided in the epitaxial structure 20, and a second electrode 28 is provided on the periphery of the recess 24 and the second bragg mirror 23 at the first electrode 27.

In this embodiment, the first electrode 27 is a P electrode, and the second electrode 28 is an N electrode. The first electrode 27 and the second electrode 28 may be TiAu or AgAu or CuNi, respectively. The first electrode 27 may have a disk shape, and the second electrode 28 may have a ring shape, such as a circular ring shape, an elliptical ring shape, a rectangular ring shape, or the like. In this embodiment, the substrate 10 may be GaAs, alxGa (1-x) As (subscript x represents a percentage of Ga atoms substituted with Al atoms in GaAs), etc., and the thickness of the substrate 10 may be 100 μm to 150 μm. The epitaxial structure 20 may be formed by epitaxial growth on the substrate 10, and the thickness of the epitaxial structure 20 as a whole may be 10 μm. The overall size of the individual VCSEL units 00 ranges from 50 μm to 70 μm.

The first bragg reflector 21 in the epitaxial structure 20 is a multilayer stacked structure, for example, may comprise a plurality of aluminum doped gallium arsenide AlGaAs layers with different Al compositions alternately arranged.

The resonant cavity 22 formed on the first bragg mirror 21 serves as an active layer, and the resonant cavity 22 is constituted by a single or a plurality of quantum well structures. The quantum well structure and the application material in the resonant cavity 22 are InGaAs, alGaAs, alGaInP.

In addition, the second bragg mirror 23 is a multilayer laminated structure, and may include, for example, aluminum-doped gallium arsenide AlGaAs layers alternately arranged with different Al compositions.

In this embodiment, the recess 24 formed in the epitaxial structure 20 includes a plurality of through holes 241 (as shown in fig. 2) penetrating the second bragg reflector 23 and the resonant cavity 22, and a plurality of sub-recesses 242 located on the first bragg reflector 21. Wherein, the number of the through holes 241 and the sub grooves 242 is the same, and the through holes 241 and the sub grooves 242 are in one-to-one correspondence in the vertical direction. The center points of the corresponding through holes 241 and the sub grooves 242 are located on the same vertical line. In cross section, the size of the through hole 241 is larger than the size of the sub-groove 242.

In this embodiment, a plurality of through holes 241 penetrating the second bragg mirror 23 and the resonant cavity 22 may be formed based on a plurality of positions of the surface of the second bragg mirror 23 and by using an oxidation process. On the basis, a plurality of sub-grooves 242 are formed from the exposed surface of the first bragg reflector 21 by an oxidation process.

In this embodiment, the cross sections of the through holes 241 and the sub grooves 242 may be circular or elliptical, or may be other irregular shapes. The plurality of through holes 241 are arranged at intervals, and a line connecting center points of the plurality of through holes 241 may form a polygon, for example, may be a regular polygon. The number of the through holes 241 may be set to 4-8, and it is ensured that the connection lines of the center points of the plurality of through holes 241 constitute a regular polygon. For example, when the number of the through holes 241 is six, the center points of the six through holes 241 are connected, and may form a hexagon.

Similarly, the plurality of sub-grooves 242 are disposed at intervals, and the connection lines of the center points of the plurality of sub-grooves 242 form a polygon, such as a regular polygon.

In this embodiment, if the center points of the plurality of through holes 241 or the plurality of sub-grooves 242 are connected in a curve, the curve connection of the center points of the plurality of through holes 241 or the plurality of sub-grooves 242 may form a circle or an ellipse.

In the VCSEL unit 00 provided in this embodiment, a plurality of central point connecting lines are formed in the second bragg reflector 23 and the resonant cavity 22 to form a regular polygon through hole 241, and a plurality of central point connecting lines are formed in the first bragg reflector 21 to form a regular polygon sub-groove 242, so that the overall structure of the VCSEL unit 00 is stronger.

In this embodiment, the VCSEL unit 00 includes an ion implantation isolation region 232, and the ion implantation isolation region 232 is located at an edge of the second bragg mirror 23, specifically, at a periphery of the second bragg mirror 23. The ion implantation isolation region 232 has a ring-shaped structure in a top view.

The ion implantation isolation region 232 may be formed by ion implantation of H ⁺ into the second bragg mirror 23, the ion implantation isolation region 232 being formed to have a characteristic of limiting a current.

In this embodiment, the ion implantation concentration in the ion implantation isolation region 232 is 1.95X10 ¹⁴/cm³-4.0×10¹⁴/cm³, and the ion implantation energy is 100KeV-330KeV.

On this basis, the VCSEL unit 00 further comprises a first contact metal layer 251 and a second contact metal layer 252. The first contact metal layer 251 is located on the surface of the second bragg reflector 23 and corresponds to the oxidation limiting hole location, and the first electrode 27 is located on the first contact metal layer 251.

The second contact metal layer 252 is located on the surface of the recess 24 (including the via 241 and the sub-recess 242) and the periphery of the first electrode 27 of the second bragg mirror 23, and the second electrode 28 is located on the portion of the second contact metal layer 252 located on the current conducting layer of the second bragg mirror 23.

In order to achieve a conductive isolation between the metal layer and the second bragg mirror 23 and the resonant cavity 22, the VCSEL unit 00 further comprises a first front passivation layer 261 in this embodiment. Wherein the first front passivation layer 261 is located on the hole wall and bottom of each through hole 241, and the surface of the second bragg reflector 23 except the area where the second contact metal layer 252 is located.

That is, within each via 241, there is a first front passivation layer 261 between the first contact metal layer 251 and the walls and between the bottoms of the vias 241. A first front passivation layer 261 is present between the surface of the second bragg mirror 23 and the first contact metal layer 251. Further, a first front passivation layer 261 is provided on the periphery of the second contact metal layer 252 on the surface of the second bragg mirror 23.

In this embodiment, the VCSEL unit 00 further includes a second front passivation layer 262, where the second front passivation layer 262 is located above the first front passivation layer 261 and surrounds the periphery of the first electrode 27.

The second front passivation layer 262 has a ring-shaped structure in a top view, and is located between the disk-shaped first electrode 27 and the ring-shaped second electrode 28. The second front passivation layer 262 and the first front passivation layer 261 may function to protect the chip.

In addition, the VCSEL unit 00 further comprises a back passivation layer 263, the back passivation layer 263 being located on the side of the substrate 10 remote from the epitaxial structure 20.

In this embodiment, the thickness of the first front passivation layer 261 may be 0.1 μm to 0.3 μm, and the thickness of the back passivation layer 263 may be 0.1 μm to 0.3 μm.

The first front passivation layer 261, the second front passivation layer 262, and the back passivation layer 263 may be silicon nitride layers.

Referring to fig. 3 through 8, a schematic diagram of a chip hierarchy formed in each step in the implementation of the VCSEL unit 00 shown in fig. 1 is shown.

As shown in fig. 3, a first bragg mirror 21, a resonant cavity 22, and a second bragg mirror 23 may be sequentially formed on the provided substrate 10. For example, each of the above layers may be deposited on the substrate 10 by any one of low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition (PECVD), and inductively coupled enhanced plasma Deposition (ICP-PECVD).

In addition, H ⁺ ion implantation is employed in the second Bragg reflector 23 to form the ion implantation isolation region 232, wherein the ion implantation energy is 100KeV-330KeV and the ion implantation concentration is 1.95X10 ¹⁴/cm³-4.0×10¹⁴/cm³. The ion implantation isolation region 232 is formed in a ring-like structure.

Referring to fig. 4, a first contact metal layer 251 is deposited on the surface of the second bragg reflector 23, the first contact metal layer 251 may have a disk shape, and the first contact metal layer 251 is located at other positions of the second bragg reflector 23 except for the corresponding ion implantation isolation region 232.

Referring to fig. 5, a first front passivation layer 261 is deposited on the surface of the second bragg reflector 23, and the first front passivation layer 261 is located at other portions of the second bragg reflector 23 except for the region where the first contact metal layer 251 is located.

Referring to fig. 6, an oxide region is defined on the surface of the second bragg reflector 23, and an oxide etching process is performed on the second bragg reflector 23 based on the oxide region, so as to etch through the second bragg reflector 23 and the resonant cavity 22, so as to form a plurality of through holes 241.

Referring to fig. 7, an oxidation limiting layer 231 is formed on the second bragg reflector 23 by a wet oxidation method, a first front passivation layer 261 is deposited on the hole wall and the bottom of each through hole 241, and oxidation etching is continuously performed on the first bragg reflector 21 exposed below on the basis of the first front passivation layer 261, so that a plurality of etching regions can be defined on the first bragg reflector 21, and the etching regions are arranged at intervals. The first bragg reflector 21 is etched in each etching region, and the etching ends at a level intermediate position of the first bragg reflector 21, that is, the etching forms a plurality of sub-grooves 242. The cross-sectional shape of each sub-groove 242 may be circular or elliptical, or may be other shapes.

The connection lines of the center points of the plurality of through holes 241 and the plurality of sub grooves 242 may constitute a polygon.

In addition, an oxidation limiting layer 231 is formed on the second bragg reflector 23 at other positions except for the ion implantation isolation region 232, the oxidation limiting layer 231 has a ring-shaped structure, and an oxidation limiting hole is formed around the inner edge of the ring-shaped structure, and the oxidation limiting hole defines the light emitting region of the VCSEL unit 00. The light-emitting direction of the light-emitting region of the VCSEL unit 00 is back-side light emission. The pore diameter of the oxidation limiting pore is 8 μm to 20 μm.

On the basis of this, referring to fig. 8, a second contact metal layer 252 may be deposited on each sub-groove 242, each via 241, and other portions of the second bragg reflector 23 except for the region where the first contact metal layer 251 is located.

In addition, the back passivation layer 263 may be deposited on the back surface of the substrate 10 after the substrate 10 is thinned. The thickness of the thinned substrate 10 may be 100 μm to 150 μm and the thickness of the back passivation layer 263 may be 0.1 μm to 0.3 μm.

A first electrode 27 is deposited on the surface of the first contact metal layer 251 and a second electrode 28 is deposited on the surface of the second contact metal layer 252 on the current conducting layer of the second bragg mirror 23. The first electrode 27 is formed in a disc shape, the second electrode 28 is in a ring shape, the first electrode 27 and the second electrode 28 can be TiAu, agAu or CuNi, and the first electrode 27 and the second electrode 28 can further comprise solder metal layers, such as SnAg, respectively formed on the surface layers of the first electrode 27 and the second electrode 28, so as to facilitate the flip-chip packaging of the subsequent VCSEL chip. Finally, a second front passivation layer 262 is formed on the first front passivation layer 261 at a position surrounding the first electrode 27, and the second front passivation layer 262 has a ring-like structure in a plan view. Finally, a device structure as shown in fig. 1 is formed.

The VCSEL unit 00 provided in this embodiment is of a single light emitting hole structure, and has a smaller size based on the first electrode 27 formed on the light emitting region, so that a chip can be arbitrarily set based on the module requirement, thereby meeting the product flexibility. The VCSEL unit 00 can be transferred to a flexible substrate or other substrates by means of mass transfer technology of Min LEDs or Micro LEDs, which can meet the requirements of windable applications.

The embodiment of the present application further provides a VCSEL chip 0, referring to fig. 9, where the VCSEL chip 0 includes at least two VCSEL units 00. Among the at least two VCSEL units 00, the substrates 10 of two adjacent VCSEL units 00 are connected, and the epitaxial structures 20 are spaced apart. The two adjacent parts can be two adjacent parts in the horizontal direction or two adjacent parts in the vertical direction when in the horizontal state.

A connection region 01 and a hollow region 02 are arranged between the substrates 10 of two adjacent VCSEL units 00, a connection portion 03 for connecting the substrates 10 of two adjacent VCSEL units 00 is arranged on the connection region 01, and the substrates 10 of two adjacent VCSEL units 00 are integrally formed.

In this embodiment, the hollowed-out region 02 is a region where the epitaxial structure 20 and the substrate 10 are removed, and the connection region 01 is a region where only the epitaxial structure 20 is removed and the substrate 10 is left, so that the connection portion 03 is a portion of the substrate 10 that is left.

When the VCSEL unit 00 needs to be transferred in a huge amount, the VCSEL unit 00 can be transferred on the basis of the VCSEL chip 0 by pinching off the connection 03 by using a clamping tool.

In the VCSEL chip 0 provided in this embodiment, the connection portion 03 and the hollow area 02 are provided between two adjacent VCSEL units 00, and by this weakened connection manner, the VCSEL units 00 can be conveniently transferred in a huge amount on the basis of ensuring that the positions of the VCSEL units 00 are stable and do not deviate.

In this embodiment, the number of the connection portions 03 between two adjacent VCSEL units 00 may be one or more. In the case where the number of the connection portions 03 is one, as shown in fig. 9, the connection portions 03 may be located at an edge position between two adjacent VCSEL units 00, for example, at one corner position between two adjacent VCSEL units 00. The connecting part 03 is arranged as one, so that the connecting part 03 can be conveniently clamped off for transferring in the process of transferring huge quantities.

In the case where the number of the connection portions 03 is plural, the plural connection portions 03 may be disposed at intervals, for example, if the number of the connection portions 03 is two, the two connection portions 03 may be located at two corner positions between the adjacent two VCSEL units 00, respectively, or if the number of the connection portions 03 is three, the three connection portions 03 may be located at two corner positions between the adjacent two VCSEL units 00, respectively, and at an intermediate position. The plurality of connecting parts 03 can further ensure that the positions of the VCSEL units 00 are stable and not offset.

In this embodiment, the connection portion 03 may have a rectangular cross section, and the rectangular connection portion 03 is convenient to manufacture and form. It should be noted that the cross section may be of other irregular shapes. The connection portion 03 may have a notch on two opposite sides adjacent to the substrate 10. The notch may be a right angle notch or a rounded corner notch, that is, the connecting portion 03 may have a structure with a larger width at both ends and a smaller width in the middle. By providing the connection portion 03 in a shape having a notch, the connection portion 03 can be pinched off at the notch position at the time of subsequent mass transfer, so that the VCSEL unit 00 can be transferred.

Referring to fig. 10 to 12 in combination, in this embodiment, for each two adjacent VCSEL units 00, the direction in which the two adjacent VCSEL units 00 are located may be defined as a first direction, in which a distance d3 between the epitaxial structures 20 of the two adjacent VCSEL units 00 is 30 μm to 100 μm. The problem of interference between two adjacent VCSEL units 00 can be avoided by providing a certain separation distance between the epitaxial structures 20 of two adjacent VCSEL units 00.

In the present embodiment, a direction perpendicular to the first direction is defined as a second direction in which the width d2 of the connection portion 03 is less than or equal to 40% of the size of the VCSEL unit 00. Alternatively, the width of the connection 03 is 20 μm-30 μm. If the width of the connection portion 03 is smaller than 20 μm, a problem may be caused that affects the positional stability of the VCSEL unit 00. If the width of the connection portion 03 is set large, for example, greater than 30 μm, it may be inconvenient to disconnect the connection portion 03 after the transfer when the VCSEL unit 00 is transferred later.

In this embodiment, the hollowed-out region 02 between the substrates 10 of two adjacent VCSEL units 00 is formed by etching and cutting the epitaxial structure 20 and the substrates 10. In order to avoid damage to the epitaxial structure 20 when dicing the substrate 10, a portion of the substrate 10 will remain beyond the epitaxial structure 20 when dicing the substrate 10.

That is, in the formed VCSEL chip 0, the projection region of the epitaxial structure 20 of each VCSEL unit 00 onto the substrate 10 is located inside the edge of the substrate 10, the edge of the substrate 10 extending beyond the projection region. For example, when the epitaxial structure 20 is rectangular in the entire plan view and the substrate 10 is rectangular, the projection area of the epitaxial structure 20 on the substrate 10 is also rectangular, and the edge of the rectangular substrate 10 exceeds the projection area. The edge of substrate 10 is beyond the edge of epitaxial structure 20 in a top view.

In this embodiment, the width d1 of the portion of the substrate 10 extending beyond the projection region is 10 μm to 15 μm, so as to ensure that the epitaxial structure 20 of each VCSEL unit 00 in the VCSEL chip 0 is not damaged.

The VCSEL chip 0 provided in this embodiment includes at least two VCSEL units 00, and the epitaxial structures 20 between every two adjacent VCSEL units 00 are arranged at intervals, and the substrates 10 are connected, and a connection area 01 and a hollowed-out area 02 are provided between the substrates 10 of two adjacent VCSEL units 00, wherein the connection area 01 has a connection portion 03 for connecting the substrates 10, and the hollowed-out area 02 is an area formed by cutting the substrates 10 to remove the substrates 10.

On the basis of comprising a plurality of small-sized VCSEL units 00, the VCSEL chips 0 are connected through the weakening structure with the hollowed-out areas 02, so that the VCSEL chips 0 can be transferred through the existing LED huge transfer technology, the stable and non-offset positions of the VCSEL units 00 are ensured, and the weakening structure is directly pinched off during transfer, so that transfer under various requirements can be realized.

The hierarchical structure of each VCSEL unit 00 in the VCSEL chip 0 provided in this embodiment is shown in fig. 1, each VCSEL unit 00 in the VCSEL chip 0 in this embodiment has the same features as the VCSEL unit 00 in the foregoing embodiment, and the VCSEL chip has the same technical effects as the VCSEL unit 00 in the foregoing embodiment, which is not described in detail in this embodiment, but reference may be made to the related description of the VCSEL unit 00 in the foregoing embodiment, which is not described herein.

The embodiment of the present application further provides a method for manufacturing the VCSEL chip 0, where the method for manufacturing the VCSEL chip 0 in the above embodiment may be used to manufacture the VCSEL chip 0, and the method for manufacturing the VCSEL chip 0 includes the following steps:

S11, at least two VCSEL units 00 are provided, the substrates 10 of adjacent two VCSEL units 00 of the at least two VCSEL units 00 being connected, the epitaxial structure 20 being connected.

And S12, defining a cutting channel region on the epitaxial structure 20 between the two adjacent VCSEL units 00, and etching the epitaxial structure 20 at the cutting channel region to expose the substrate 10 below.

S13, defining a first area and a second area on the exposed substrate 10, cutting the substrate 10 at the first area to remove the substrate 10 at the first area to form a hollowed-out area 02, and reserving the substrate at the second area to form a connection area 01, wherein the connection area 01 is provided with a connection portion 03 for connecting the substrates of two adjacent VCSEL units.

In this embodiment, at least two VCSEL units 00 may be provided as VCSEL units 00 formed by implementation of the above-described embodiments. The above embodiment is described with respect to a single VCSEL unit 00, and when fabricating the VCSEL unit 00, it is understood that fabrication of a plurality of VCSEL units 00 is performed simultaneously on the same substrate.

The substrates 10 of adjacent two VCSEL units 00 of the at least two VCSEL units 00 are provided connected, the epitaxial structure 20 being connected. A scribe line region may be defined on the epitaxial structure 20 between two adjacent VCSEL units 00 and the epitaxial structure 20 at the scribe line region is etched.

Specifically, the present embodiment may implement etching of the epitaxial structure 20 by:

a scribe line region is defined on the epitaxial structure 20 between the two adjacent VCSEL units 00 by a yellow light process, and the epitaxial structure 20 at the scribe line region is etched by a dry etching process to expose the underlying substrate 10.

In this embodiment, the width of the scribe line region is defined to be 30 μm to 100 μm, that is, the distance between the epitaxial structures 20 of two adjacent VCSEL units 00 is 30 μm to 100 μm after etching the epitaxial structures 20, so that the width of the scribe line region cannot be set too small or too large, for example, cannot be smaller than 30 μm or larger than 100 μm, in order to ensure that no damage is caused to the epitaxial structures 20 and that the connection portion 03 is smoothly broken during transfer.

On the basis of this, a first region and a second region are defined on the substrate 10 exposed below, and the first region is cut in the following manner:

and cutting the substrate 10 at the first area by adopting a laser cutting process to remove the substrate 10 at the first area so as to form the hollowed-out area 02.

In this embodiment, the first region is defined with a view to avoiding damage to the epitaxial structure 20, and therefore, the width of the first region is smaller than the width between the epitaxial structures 20 of the adjacent two VCSEL units 00. So that the substrate 10 at the first region is cut, ensuring that the epitaxial structure 20 is not damaged.

According to the manufacturing method of the VCSEL chip, the epitaxial structure 20 is etched, the substrate 10 is cut, so that a weakening structure is formed between two adjacent VCSEL units 00, and the huge transfer of the subsequent VCSEL units 00 is guaranteed in a convenient process mode.

In addition, in the method for fabricating the VCSEL chip 0 provided in the present embodiment, the related description of the VCSEL chip 0 can refer to the VCSEL chip 0 in the above embodiment, and the description of the embodiment is omitted herein.

The embodiment of the application also provides a flexible panel, which comprises a flexible substrate and the VCSEL chip 0 in any implementation mode of the embodiment, wherein the VCSEL chip 0 is arranged on the flexible substrate. The flexible substrate may be a substrate of any shape such as a curved plate or a flat plate.

The VCSEL chip 0 in the flexible panel in the present embodiment has the same features as the VCSEL chip 0 in the above embodiment, and the flexible panel has the same technical effects as the VCSEL chip 0 in the above embodiment, and for the relevant content of the flexible panel, reference is made to the relevant description in the above embodiment.

The embodiment of the application also provides an electronic device, which comprises an optical module, wherein the optical module comprises a VCSEL chip 0, the VCSEL chip comprises a plurality of VCSEL units 00, and the plurality of VCSEL units 00 can be arranged in a matrix mode or can be arranged in a non-matrix mode to form an irregular shape.

In summary, in the VCSEL unit 00, the VCSEL chip 0, the VCSEL chip manufacturing method, and the flexible panel provided in the embodiments of the present application, the VCSEL chip 0 includes at least two VCSEL units 00, each VCSEL unit 00 includes a substrate 10 and an epitaxial structure 20 disposed on the substrate 10, the substrates 10 of two adjacent VCSEL units 00 are connected, and the epitaxial structures 20 are disposed at intervals. The substrate 10 of two adjacent VCSEL units 00 has a connection area 01 and a hollow area 02, the connection area 01 has a connection portion 03 for connecting the substrates 10 of two adjacent VCSEL units 00, and the substrates 10 of two adjacent VCSEL units 00 are integrally formed. In the VCSEL chip 0, a connection portion 03 and a hollowed-out area 02 are provided between two adjacent VCSEL units 00, and by means of the weakened connection mode, the VCSEL units 00 can be conveniently transferred in a huge amount on the basis of guaranteeing stable and non-offset positions of the VCSEL units 00, so that the VCSEL units 00 can be applied to flexible panels, and application requirements of the VCSEL units 00 can be met.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A VCSEL chip comprising at least two VCSEL units, each of said VCSEL units comprising a substrate and an epitaxial structure disposed on said substrate;

2. A VCSEL chip as claimed in claim 1, wherein the number of connections between two adjacent VCSEL units is one or more;

3. A VCSEL chip as claimed in claim 1, characterized in that the cross section of the connection is rectangular or in the shape of two opposite edges adjacent to the substrate with notches.

4. A VCSEL chip as claimed in claim 1, characterized in that the distance between the epitaxial structures of the two adjacent VCSEL units in the first direction in which the two adjacent VCSEL units are located is 30 μm-100 μm.

5. A VCSEL chip as claimed in claim 4, characterized in that the width of the connection section in a second direction perpendicular to the first direction is 20 μm-30 μm.

6. The VCSEL chip of claim 1, wherein for each of the VCSEL cells, a projected region of an epitaxial structure of the VCSEL cell onto a substrate is located inward of an edge of the substrate that extends beyond the projected region.

7. A VCSEL chip as claimed in claim 6, characterized in that the part of the substrate extending beyond the projection region has a width of 10 μm-15 μm.

8. A VCSEL chip as claimed in any of claims 1 to 7, wherein the epitaxial structure of each of the VCSEL units comprises a first bragg mirror on the substrate, a resonant cavity on a side of the first bragg mirror remote from the substrate, and a second bragg mirror on a side of the resonant cavity remote from the first bragg mirror;

9. The VCSEL chip of claim 8, wherein the recess comprises a plurality of through holes through the second bragg mirror and resonant cavity, and a plurality of sub-recesses in the first bragg mirror;

10. A VCSEL unit comprising a substrate and an epitaxial structure on the substrate, the epitaxial structure comprising:

a first Bragg reflector on the substrate;

11. The VCSEL unit as claimed in claim 10, wherein the recess comprises a plurality of through holes through the second bragg mirror and resonant cavity, and a plurality of sub-recesses in the first bragg mirror.

12. The VCSEL unit as claimed in claim 11, further comprising an ion implantation isolation region at an edge of the second bragg mirror;

13. The VCSEL unit as claimed in claim 11, further comprising a first front side passivation layer, a second front side passivation layer and a back side passivation layer;

14. The VCSEL unit as claimed in claim 13, wherein the first front side passivation layer has a thickness of 0.1 μm-0.3 μm and the back side passivation layer has a thickness of 0.1 μm-0.3 μm.

15. The VCSEL unit as claimed in claim 10, further comprising a first contact metal layer and a second contact metal layer;

16. A method of fabricating a VCSEL chip, for use in fabricating a VCSEL chip as claimed in any of claims 1-9, the method comprising:

17. The method of fabricating a VCSEL chip as claimed in claim 16, wherein the step of defining a street region on the epitaxial structure between the two adjacent VCSEL units, etching the epitaxial structure at the street region to expose an underlying substrate, comprises:

18. The method of fabricating a VCSEL chip as claimed in claim 17, wherein said step of dicing the substrate at the first region to remove the substrate at the first region to form a hollowed-out region comprises:

19. A flexible panel comprising a flexible substrate and the VCSEL chip of any one of claims 1-9, the VCSEL chip being disposed on the flexible substrate.