CN117976791B - 940Nm reversed-polarity infrared LED epitaxial wafer and preparation method thereof - Google Patents
940Nm reversed-polarity infrared LED epitaxial wafer and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a 940nm reversed polarity infrared LED epitaxial wafer and a preparation method thereof, wherein the epitaxial wafer comprises a GaAs substrate, a GaAs buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-face space layer, an N-face strain relief layer, a first luminous active layer, an intermediate strain relief layer, a second luminous active layer, a P-face strain relief layer, a P-face space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer from bottom to top in sequence; the strain relief layers are all GaAsP in material and are all undoped. According to the invention, the strain relief layers are introduced at the two sides and the middle of the light-emitting active region, and the problems of insufficient light-emitting efficiency, apparent lattice mismatch of an epitaxial wafer, light effect attenuation and the like can be effectively solved by combining a quantum well/quantum barrier structure with gradually changed PH 3 and a pause purging type growth method, so that the high-light-efficiency 940nm reversed-polarity LED suitable for pulse current operation is obtained.
Description
Technical Field
The invention relates to the technical field of LEDs, in particular to a 940nm reversed polarity infrared LED epitaxial wafer and a preparation method thereof.
Background
An infrared LED (LIGHTING EMITTING Diode) with the luminous wavelength of 940nm is widely applied to infrared detection, infrared remote sensing, high-speed infrared communication, security monitoring and the like. With the continuous development of application fields, the main working conditions of the monitoring camera, the infrared induction detector and the like are pulse currents, and compared with the traditional constant current driving, the constant current driving needs higher luminous power, current bearing capacity and higher reliability.
At present, a schematic structural diagram of a 940nm reverse polarity infrared LED epitaxial wafer conventional in the industry is shown in fig. 1, and epitaxial materials are grown sequentially from bottom to top, wherein the epitaxial materials comprise a GaAs substrate 1, a GaAs buffer layer 2, a corrosion cut-off layer 3, an N-type ohmic contact layer 4, an electrode protection layer 5, an N-type current expansion layer 6, an N-type limiting layer 7, an N-face space layer 8, a multiple quantum well active layer 13, a P-face space layer 9, a P-type limiting layer 10, a P-type current expansion layer 11 and a P-type window layer 12. However, the existing conventional 940nm reversed polarity LED cannot achieve stable luminous efficiency and power under the condition of pulse current. In order to improve the luminous efficiency, the personnel in the industry can increase the logarithm of luminous quantum wells/barriers in the multi-quantum well active layer, however, the adopted wells are generally made of InGaAs materials, after the logarithm is increased, the lattice mismatch of the epitaxial wafer is caused by the fact that the strain superposition of the InGaAs materials is large, the surface of the epitaxial wafer has mismatched lines or cracks, and the problems of brightness reduction, light efficiency attenuation and the like occur in the continuous working process of pulse current.
Therefore, how to develop 940nm reverse polarity infrared LEDs with high luminous efficiency and high reliability under pulsed current operation is a difficult problem for technicians.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a 940nm reversed polarity infrared LED epitaxial wafer and a preparation method thereof, which effectively avoid the problems of lattice mismatch, light effect attenuation and the like caused by the increase of the number of luminescent quantum wells/barriers.
The invention provides a 940nm reverse polarity infrared LED epitaxial wafer, which sequentially grows from bottom to top, and sequentially comprises a GaAs buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-face space layer, an N-face strain relief layer, a first light-emitting active layer, an intermediate strain relief layer, a second light-emitting active layer, a P-face strain relief layer, a P-face space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer from a GaAs substrate;
the N-face strain relief layer, the middle strain relief layer and the P-face strain relief layer are all made of GaAsP and are undoped.
According to the technical scheme, a strain relief layer GaAsP material is inserted between an N-plane space layer and a multi-quantum well active layer, between a P-plane space layer and the multi-quantum well active layer, and lattice mismatch caused by overlarge superposition of compressive strain of a well layer material InGaAs in the process of increasing the logarithm of the quantum well can be avoided through the design of the structure; meanwhile, by utilizing the tensile strain characteristic of the strain relief layer material GaAsP, the lattice mismatch problem caused by the compressive strain of the InGaAs material can be compensated at both sides and in the middle of the active region, and the crystal quality of the epitaxial material and the reliability of the LED are improved.
Furthermore, the thicknesses of the N-surface strain relief layer and the P-surface strain relief layer are 300-500 nm, so that enough thickness of epitaxial layer material can be ensured to help to compensate and release stress; the thickness of the intermediate strain relief layer is 60 nm-70 nm, so that stress relief can be facilitated in the light-emitting area of the core, and meanwhile, voltage rise can be avoided through thickness control. According to the technical scheme, the crystal quality and the reliability of the epitaxial material are improved by adopting the strain relief layers with different thicknesses at different positions.
Further, the first light-emitting active layer and the second light-emitting active layer are combined into a light-emitting active layer, the light-emitting active layer is of a periodic circulation structure in which a quantum well layer and a quantum barrier layer alternately grow, and the number of circulation pairs is 6-8; the quantum barrier layer is sequentially provided with a first strain compensation layer, a second strain compensation layer and a third strain compensation layer from bottom to top.
Further, the material of the quantum well layer is In x4Ga1-x4 As, the thickness of the single well is 6 nm-8 nm, and the value range of x4 is 0.16-0.18; the materials of the first strain compensation layer, the second strain compensation layer and the third strain compensation layer in the quantum barrier layer are (Al y1Ga1-y1)0.5As0.5 P, the thicknesses of the first strain compensation layer and the third strain compensation layer are 4 nm-8 nm, the thickness of the second strain compensation layer is 10 nm-20 nm, wherein the value range of y1 is 0.1-0.2.
Further, the materials of the corrosion stop layer and the electrode protection layer are Ga 0.5In0.5 P, the doping materials are Si, the doping concentration is 1.5X10 18cm-3～3.0×1018cm-3, the thickness of the corrosion stop layer is 200 nm-400 nm, and the thickness of the electrode protection layer is 20 nm-40 nm; the N-type ohmic contact layer is made of GaAs, the doping material is Si, the doping concentration is 2.0X10 18cm-3～5.0×1018cm-3, and the thickness is 40-80 nm.
Further, the materials of the N-type current expansion layer and the P-type current expansion layer are Al x1Ga1-x1 As, wherein the value range of x1 is 0.1-0.2; the doping material of the N-type current expansion layer is Si, the doping concentration is 3.0X10 18cm-3～6.0×1018cm-3, and the thickness is 7000 nm-8000 nm; the doping material of the P-type current expansion layer is C, the doping concentration is 3.0X10 18cm-3～6×1018cm-3, and the thickness is 2000 nm-3000 nm; the materials of the N-type limiting layer and the P-type limiting layer are Al x2Ga1-x2 As, wherein the value range of x2 is 0.2-0.4, the thickness of the N-type limiting layer is 300-500 nm, the doping material is Si, and the doping concentration is 2X 10 18cm-3～4×1018cm-3; the thickness of the P-type limiting layer is 400-600 nm, the doping material is C, and the doping concentration is 2X 10 18cm-3～4×1018cm-3; the materials of the N-surface space layer and the P-surface space layer are Al x3Ga1-x3 As, wherein the value range of x3 is 0.05-0.15, the thicknesses of the N-surface space layer and the P-surface space layer are 500-800 nm, and the N-surface space layer and the P-surface space layer are undoped.
The P-type window layer is made of GaP, the thickness is 150-200 nm, the doping material is Mg, and the doping concentration is 0.5X10 19cm-3～2×1019cm-3.
The second object of the invention is to provide a preparation method of 940nm reversed polarity infrared LED epitaxial wafer, which comprises the steps of growing a GaAs buffer layer, a corrosion cut-off layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-face space layer, an N-face strain relief layer, a first luminous active layer, an intermediate strain relief layer, a second luminous active layer, a P-face strain relief layer, a P-face space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer on a GaAs substrate in sequence by using MOCVD (metal organic chemical vapor deposition) equipment; the first light-emitting active layer and the second light-emitting active layer are periodic circulation structures in which quantum well layers and quantum barrier layers alternately grow; the quantum barrier layer is sequentially provided with a first strain compensation layer, a second strain compensation layer and a third strain compensation layer from bottom to top; and growing the quantum well layer and the quantum barrier layer in a pause purging type growth mode.
In the technical scheme, a pause purging type growth mode is adopted between the quantum well layer and the quantum barrier layer for growth, namely before and after each quantum well layer is grown, the surface flatness of the quantum well layer can be improved by controlling the raw materials and the flow of the gas, so that the light-emitting efficiency under the pulse current operation is facilitated.
Further, the growth step of the N-face strain relief layer is as follows: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the N-surface space layer, and growing GaAsP material with the thickness of 300-500 nm, wherein the flow rate of the TMGa is set to 100-150 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 300-400 sccm;
The intermediate strain relief layer growth steps are: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the first light-emitting active layer, and growing GaAsP material with the thickness of 60-70 nm, wherein the flow rate of the TMGa is set to 60-80 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 600-700 sccm;
The growth steps of the P-plane strain relief layer are as follows: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the second light-emitting active layer, and growing GaAsP material with the thickness of 300-500 nm, wherein the flow rate of the TMGa is set to 100-150 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 300-400 sccm.
Further, the quantum barrier layer growth step is as follows: setting the temperature of the reaction chamber to 670 ℃ +/-20 ℃, introducing TMAl, TMGa, asH 3、PH3, growing the first strain compensation layer, the second strain compensation layer and the third strain compensation layer, wherein the materials are AlGaAsP, the thicknesses are sequentially 4 nm-8 nm, 10 nm-20 nm and 4 nm-8 nm, wherein the flow of TMAL is set to 80-120 sccm, the flow of TMGa is set to 100-150 sccm, the flow of AsH 3 is set to 400-500 sccm, the PH 3 flow when the first strain compensation layer and the third strain compensation layer are grown is set to 100-200 sccm, and the PH 3 flow when the second strain compensation layer is grown is set to 600-800 sccm.
According to the technical scheme, a light-emitting quantum well/barrier is adjusted from an InGaAs/AlGaAsP structure to a multi-quantum well/barrier structure with a PH 3 gradual-change type strain compensation layer, the quantum barrier layer is improved to be a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, materials of the three strain compensation layers are the same, but PH 3 flow rates in the growing process are different, wherein PH 3 growth flow rates of the first strain compensation layer and the third strain compensation layer are 100 sccm-200 sccm, PH 3 flow rate of the second strain compensation layer is 600 sccm-800 sccm, the problem that light-emitting efficiency is restrained due to too large strain can be effectively solved, and the problem that phosphorus element diffuses into the quantum well in the continuous large-current working process of a chip to cause light-emitting efficiency attenuation can be prevented by reducing the content of PH 3 at two sides close to the quantum well.
Further, the step of the growth mode of the pause purging type is as follows: the temperature of the reaction chamber is set to 680+/-20 ℃, materials of other sources are closed to enter the reaction chamber before and after the start and the end of the growth of each quantum well layer, and only AsH 3 is introduced to purge the surface of the epitaxial layer, wherein the flow of AsH 3 is set to 400-500 sccm, and the purging time of each time is 2-5 s. According to the technical scheme, by adopting a pause purging type growth mode, other source materials are stopped from being introduced before and after the InGaAs quantum well layer is grown, and only AsH 3 is introduced as purge gas, so that the surface flatness of the quantum well layer can be improved, and the light-emitting efficiency under the pulse current operation is facilitated.
Compared with the prior art, the invention has the beneficial effects that:
1. Aiming at the characteristics of the working condition of the pulse current, the invention introduces the strain relief layers at the two sides and the middle of the light-emitting active region, and improves the quantum barrier in the light-emitting region into the strain compensation layer material with gradually changed PH 3, thereby not only effectively ensuring the light-emitting efficiency and the brightness of the 940nm reversed polarity LED when the pulse current works, but also avoiding the problems of lattice mismatch, reliability reduction and the like caused by the logarithmic increase of the quantum well.
2. According to the invention, a pause purging type PH 3 diffusion epitaxy inhibition technology is adopted, so that the growth quality of epitaxial crystals can be improved, the influence of PH 3 in a strain compensation layer on a quantum well layer is avoided, and the surface flatness of the quantum well layer is improved, thereby being beneficial to the stability of luminous efficiency under the pulse current operation.
3. The preparation method of the invention not only can solve the problems of brightness reduction, light effect attenuation and the like in the continuous operation of pulse current in the prior art, but also can ensure the stability and reliability of the performance of the epitaxial wafer.
Drawings
FIG. 1 is a schematic diagram of a conventional 940nm reverse polarity infrared LED epitaxial wafer structure in the industry;
FIG. 2 is a schematic diagram of the structure of the 940nm reversed polarity infrared LED epitaxial wafer;
FIG. 3 is a schematic diagram of a quantum well/quantum barrier structure of the present invention;
FIG. 4 is a graph showing the variation of the luminous power with current, a is a 940nm reversed polarity LED epitaxial wafer obtained in example 1, and b is a conventional 940nm reversed polarity LED epitaxial wafer obtained in comparative example 1;
fig. 5 is a surface topography of the epitaxial wafer of the present invention observed under a microscope, (a) a 940nm reversed polarity LED epitaxial wafer obtained in example 1, and (b) a conventional 940nm reversed polarity LED epitaxial wafer obtained in comparative example 1.
The reference numerals in the schematic drawings indicate:
1. a GaAs substrate; 2. a GaAs buffer layer; 3. etching the stop layer; 4. an N-type ohmic contact layer; 5. an electrode protection layer; 6. an N-type current expansion layer; 7. an N-type limiting layer; 8. an N-plane spatial layer; 9. a P-plane space layer; 10. a P-type limiting layer; 11. a P-type current expansion layer; 12. a P-type window layer; 13. a multi-quantum well active layer; 14. a first light emitting active layer; 15. a second light emitting active layer; 16. an N-side strain relief layer; 17. an intermediate strain relief layer; 18. a P-plane strain relief layer; 19. a first strain compensation layer; 20. a second strain compensation layer; 21. and a third strain compensation layer.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for defining the components, and are merely for convenience in distinguishing the corresponding components, and the terms are not meant to have any special meaning unless otherwise indicated, so that the scope of the present application is not to be construed as being limited.
In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present application; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.
Referring to fig. 1-5, it should be noted that the illustrations provided in the present embodiment are only schematic illustrations of the basic concept of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The structural schematic diagram of the 940nm reverse polarity infrared LED epitaxial wafer provided in the embodiment of the invention is shown in fig. 2, and the epitaxial wafer sequentially grows from bottom to top, and the epitaxial wafer sequentially comprises a GaAs buffer layer 2, a corrosion cut-off layer 3, an N-type ohmic contact layer 4, an electrode protection layer 5, an N-type current expansion layer 6, an N-type limiting layer 7, an N-side space layer 8, an N-side strain relief layer 16, a first light-emitting active layer 14, an intermediate strain relief layer 17, a second light-emitting active layer 15, a P-side strain relief layer 18, a P-side space layer 9, a P-type limiting layer 10, a P-type current expansion layer 11 and a P-type window layer 12 from the GaAs substrate 1.
In some embodiments, the N-side strain relief layer, the intermediate strain relief layer, and the P-side strain relief layer are all GaAsP and undoped, and the N-side strain relief layer and the P-side strain relief layer each have a thickness of 300nm to 500nm; the thickness of the intermediate strain relief layers is 60 nm-70 nm. And strain relief layers GaAsP materials with different thicknesses are inserted between the N-plane space layer and the multi-quantum well active layer and between the P-plane space layer and the multi-quantum well active layer, and the lattice mismatch problem caused by the compressive strain of the InGaAs materials can be compensated at both sides and the middle of the active region by utilizing the tensile strain characteristics of the strain relief layer materials GaAsP, so that the crystal quality of the epitaxial materials is improved.
In some embodiments, the first light-emitting active layer and the second light-emitting active layer are formed into a light-emitting active layer, the light-emitting active layer is in a periodic circulation structure of alternately growing quantum well layers and quantum barrier layers, the number of circulation pairs is 6-8, and the schematic structure of a single light-emitting active layer quantum well/quantum barrier is shown in fig. 3; the quantum barrier layer is sequentially provided with a first strain compensation layer 19, a second strain compensation layer 20 and a third strain compensation layer 21 from bottom to top; the quantum well layer is made of In x4Ga1-x4 As, the thickness of a single well is 6 nm-8 nm, and the value range of x4 is 0.16-0.18; the materials of the first strain compensation layer, the second strain compensation layer and the third strain compensation layer in the quantum barrier layer are (Al y1Ga1-y1)0.5As0.5 P, the thicknesses of the first strain compensation layer and the third strain compensation layer are 4 nm-8 nm, the thickness of the second strain compensation layer is 10 nm-20 nm, wherein the value range of y1 is 0.1-0.2. By improving the conventional quantum barrier layer AlGaAsP into the first strain compensation layer AlGaAsP, the second strain compensation layer AlGaAsP and the third strain compensation layer AlGaAsP, and the materials and the thicknesses of the layers are different, the problem of inhibiting luminous efficiency due to too large strain can be effectively solved.
In some embodiments, the materials of the corrosion stopping layer and the electrode protecting layer are Ga 0.5In0.5 P, the doping materials are Si, the doping concentration is 1.5X10 18cm-3～3.0×1018cm-3, the thickness of the corrosion stopping layer is 200 nm-400 nm, and the thickness of the electrode protecting layer is 20 nm-40 nm; the N-type ohmic contact layer is made of GaAs, the doping material is Si, the doping concentration is 2.0X10 18cm-3～5.0×1018cm-3, and the thickness is 40-80 nm.
In some embodiments, the materials of the N-type current expansion layer and the P-type current expansion layer are Al x1Ga1-x1 As, wherein the value range of x1 is 0.1-0.2; the doping material of the N-type current expansion layer is Si, the doping concentration is 3.0X10 18cm-3～6.0×1018cm-3, and the thickness is 7000 nm-8000 nm; the doping material of the P-type current expansion layer is C, the doping concentration is 3.0X10 18cm-3～6×1018cm-3, and the thickness is 2000 nm-3000 nm.
In some embodiments, the materials of the N-type limiting layer and the P-type limiting layer are Al x2Ga1-x2 As, wherein the value range of x2 is 0.2-0.4, the thickness of the N-type limiting layer is 300-500 nm, the doping material is Si, and the doping concentration is 2×10 18cm-3～4×1018cm-3; the thickness of the P-type limiting layer is 400-600 nm, the doping material is C, and the doping concentration is 2X 10 18cm-3～4×1018cm-3.
In some embodiments, the materials of the N-side and P-side spatial layers are Al x3Ga1-x3 As, where x3 ranges from 0.05 to 0.15, and the thicknesses are 500nm to 800nm, and are undoped.
In some embodiments, the material of the P-type window layer is GaP, the thickness is 150 nm-200 nm, the doping material is Mg, and the doping concentration is 0.5x 19cm-3～2×1019cm-3.
In still another embodiment, the invention further provides a preparation method of the 940nm reversed polarity infrared LED epitaxial wafer, which comprises the steps of sequentially growing a GaAs buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-face space layer, an N-face strain relief layer, a first light-emitting active layer, an intermediate strain relief layer, a second light-emitting active layer, a P-face strain relief layer, a P-face space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer on a GaAs substrate by using MOCVD equipment. The method specifically comprises the following steps:
(1) MOCVD is pumped down to 50mbar in pure H 2 atmosphere, the temperature of the reaction chamber is set to 400 ℃, then the GaAs substrate is transferred into the reaction chamber through a transfer bin of a manipulator, then the temperature is quickly raised to 720+/-20 ℃, and the constant temperature is maintained for 10-15 min at 720+/-20 ℃.
(2) Growing a GaAs buffer layer: the reaction chamber is set at 700+/-20 ℃, TMGa and AsH 3 are introduced, gaAs buffer layer material with the thickness of 400-600 nm is grown, siH 4 is adopted as doping agent, and the doping concentration is 3 multiplied by 10 18cm-3～5×1018cm-3.
(3) Growing a corrosion cut-off layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMIn, PH 3, growing GaInP material with the thickness of 200-400 nm, and adopting SiH 4 as a doping agent with the doping concentration of 1.5X10 18cm-3～3×1018cm-3.
(4) And (3) growing an N-type ohmic contact layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3, growing GaAs material with the thickness of 40-80 nm, and adopting SiH 4 as an N-type dopant, wherein the doping concentration is 2 multiplied by 10 18cm-3～5×1018cm-3.
(5) Growing an N-type electrode protection layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMIn, PH 3, growing GaInP material with the thickness of 20-40 nm, and adopting SiH 4 as an N-type dopant, wherein the doping concentration is 1.5X10. 10 18cm-3～3×1018cm-3.
(6) Growing an N-type current expansion layer: the reaction chamber is set at 680+/-20 ℃, TMGa, TMAl, asH 3 is introduced, al x1Ga1-x1 As material with the thickness of 7000-8000 nm is grown, the value range of x1 is 0.1-0.2, siH 4 is adopted As an N-type dopant, and the doping concentration is 3 multiplied by 10 18cm-3～6×1018cm-3.
(7) Growing an N-type limiting layer: the reaction chamber is set at 680+/-20 ℃, TMGa, TMAl, asH 3 is introduced, al x2Ga1-x2 As material with the thickness of 400-500 nm is grown, wherein the value range of x2 is 0.2-0.4, siH 4 is used As an N-type dopant, and the doping concentration is 2X 10 18cm-3～4×1018cm-3.
(8) Growing an N-surface space layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMAl, asH 3, and growing Al x3Ga1-x3 As material with the thickness of 5000-8000 nm, wherein the value range of x3 is 0.05-0.15, and the layer is undoped.
(9) Growing an N-face strain relief layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, asH3 and PH 3, and growing GaAsP material with the thickness of 300-500 nm, wherein the layer is undoped.
(10) Growing a first light emitting active layer: setting the temperature of the reaction chamber to 670+/-20 ℃, introducing TMGa, TMAl, TMIn, asH 3、PH3, growing a quantum well layer and a quantum barrier layer which are respectively In x4Ga1-x4As、(Aly1Ga1-y1)0.5As0.5 P materials, wherein the thickness of the single quantum well layer is 6-8 nm, the value range of x4 is 0.16-0.18, the value range of y1 is 0.1-0.2, the single-layer barrier layer is formed by combining a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, and the thickness of the single-layer barrier layer is 4 nm-8 nm, 10 nm-20 nm and 4 nm-8 nm in sequence. When the quantum barrier layer is grown, TMAL flow rate is set to 80-120 sccm, TMGa flow rate is set to 100-150 sccm, asH 3 flow rate is set to 400-500 sccm, PH 3 flow rates in the first strain compensation layer and the third strain compensation layer are set to 100-200 sccm, The flow rate of PH 3 in the second strain compensation layer is set to 600 sccm-800 sccm; By controlling the flow of PH 3 in the growth process, the PH 3 content is reduced at two sides close to the quantum well layer, so that the problem of luminous efficiency attenuation caused by the diffusion of phosphorus element into the quantum well in the continuous high-current working process of the chip can be prevented, and the luminous efficiency is improved. The number of quantum well/quantum barrier circulation pairs in the first light-emitting active layer is 6-8, and the light-emitting area is undoped. In the process of growing the luminous active layer, adopting a pause purging mode for growth, and specifically comprising the following steps: before and after the starting and ending of growing the InGaAs material of each quantum well layer, only AsH 3 is introduced, the introduction of the material of other sources into the reaction chamber is stopped, the surface of the epitaxial layer is purged, the flow rate of AsH 3 is set to 400-500 sccm, The purging time is 2 s-5 s each time. By adopting the pause purging type PH 3 diffusion epitaxy inhibiting technology, the growth quality of epitaxial crystals can be improved, the influence of PH 3 in the strain compensation layer on the quantum well layer is avoided, the surface flatness of the quantum well layer is improved, and therefore the stability of luminous efficiency under the pulse current operation is facilitated.
(11) Growing an intermediate strain relief layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3, and growing GaAsP material with the thickness of 60-70 nm, wherein the layer is undoped.
(12) Growing a second light emitting active layer: the reaction chamber is set at 670 ℃ +/-20 ℃, TMGa, TMAl, TMIn, asH 3、PH3 is introduced, the materials of the grown quantum well layer and the quantum barrier layer are respectively In x4Ga1-x4As、(Aly1Ga1-y1)0.5As0.5 P, the thickness of the single-layer quantum well layer is 6-8 nm, the value range of x4 is 0.16-0.18, the value range of y1 is 0.1-0.2, and the single-layer barrier layer is formed by combining a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, wherein the thicknesses of the single-layer quantum well layer and the quantum barrier layer are respectively 4-8 nm, 10-20 nm and 4-8 nm. When the quantum barrier layer is grown, TMAL flow rate is set to 80-120 sccm, TMGa flow rate is set to 100-150 sccm, asH 3 flow rate is set to 400-500 sccm, PH 3 flow rates in the first strain compensation layer and the third strain compensation layer are set to 100-200 sccm, and PH 3 flow rate in the second strain compensation layer is set to 600-800 sccm. The number of quantum well/quantum barrier circulation pairs in the second luminous active layer is 6-8, and the luminous area is undoped. In the process of growing the luminous active layer, adopting a pause purging mode for growth, and specifically comprising the following steps: before and after the growth of the InGaAs material of each quantum well layer, only AsH 3 is introduced, the introduction of the material of other sources into the reaction chamber is stopped, the surface of the epitaxial layer is purged, the flow of AsH 3 is set to 400-500 sccm, and the purging time of each time is 2-5 s.
(13) And (3) growing a P-plane space layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMAl, asH 3, and growing Al x3Ga1-x3 As material with the thickness of 5000-8000 nm, wherein the value range of x3 is 0.05-0.15, and the layer is undoped.
(14) Growing a P-type limiting layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMAl, asH 3, and growing Al x2Ga1-x2 As material with the thickness of 400-600 nm, wherein the value range of x2 is 0.2-0.4, CCl 4 is used As an N-type dopant, and the doping concentration is 2X 10 18cm-3～4×1018cm-3.
(15) And (3) growing a P-type current expansion layer: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa, TMAl, asH 3, growing Al x1Ga1-x1 As material with the thickness of 2000-3000 nm, wherein the value range of x1 is 0.1-0.2, adopting SiH 4 As an N-type dopant, and the doping concentration is 3X 10 18cm-3～6×1018cm-3.
(16) And (3) growing a P-type window layer: setting the temperature of the reaction chamber at 630+/-20 ℃, introducing TMGa and PH 3, growing GaP material with the thickness of 150-200 nm, adopting CP 2 Mg as a P-type doping agent, and doping the GaP material with the doping concentration of 0.5 multiplied by 10 19cm-3～5×1019cm-3.
(17) Taking a piece: and after the growth is finished, the temperature of the MOCVD reaction chamber is reduced to 110 ℃, then the pressure is regulated to 1000mbar, the reaction chamber is opened, and the epitaxial wafer is taken out.
Example 1
A preparation method of 940nm reversed polarity infrared LED epitaxial wafer specifically comprises the following steps:
(1) Pumping MOCVD to 50mbar in pure H 2 atmosphere, setting the temperature of a reaction chamber to 400 ℃, transferring a GaAs substrate into the reaction chamber through a transfer bin of a manipulator, quickly heating to 720 ℃, and maintaining the constant temperature at 720 ℃ for 10min;
(2) Growing a GaAs buffer layer: setting the temperature of the reaction chamber to 700 ℃, introducing TMGa and AsH 3, growing a GaAs buffer layer material with the thickness of 400nm, and adopting SiH 4 as a doping agent, wherein the doping concentration is 3 multiplied by 10 18cm-3;
(3) Growing a corrosion cut-off layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMIn, PH 3, growing GaInP material with the thickness of 200nm, and adopting SiH 4 as a doping agent, wherein the doping concentration is 1.5X10. 10 18cm-3;
(4) And (3) growing an N-type ohmic contact layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa and AsH 3, growing a GaAs material with the thickness of 40nm, and adopting SiH 4 as an N-type doping agent, wherein the doping concentration is 2 multiplied by 10 18cm-3;
(5) Growing an N-type electrode protection layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMIn, PH 3, growing GaInP material with the thickness of 20nm, and adopting SiH 4 as an N-type doping agent, wherein the doping concentration is 1.5X10 18cm-3;
(6) Growing an N-type current expansion layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, growing an Al 0.1Ga0.9 As material with the thickness of 7000nm (the value of x1 is 0.1), and adopting SiH 4 As an N-type dopant, wherein the doping concentration is 3 multiplied by 10 18cm-3;
(7) Growing an N-type limiting layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, growing Al 0.2Ga0.8 As material with the thickness of 400nm (the value of x2 is 0.2), and taking SiH 4 As an N-type dopant, wherein the doping concentration is 2 multiplied by 10 18cm-3;
(8) Growing an N-surface space layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, and growing an Al 0.05Ga0.95 As material (the value of x3 is 0.05) with the thickness of 5000nm, wherein the layer is undoped;
(9) Growing an N-face strain relief layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa and AsH 3、PH3, and growing GaAsP material with the thickness of 300nm, wherein the layer is undoped;
(10) Growing a first light emitting active layer: setting the temperature of the reaction chamber to 670 ℃, introducing TMGa, TMAl, TMIn, asH 3、PH3, growing materials of which the quantum well layer and the quantum barrier layer are In 0.16Ga0.84As、(Al0.1Ga0.9)0.5As0.5 P respectively (the value of x4 is 0.16, the value of y1 is 0.1), wherein the thickness of the single-layer quantum well layer is 6nm, and the single-layer barrier layer is formed by combining a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, wherein the thicknesses of the single-layer quantum well layer and the quantum barrier layer are 4nm, 10nm and 4nm In sequence. When the quantum barrier layer was grown, the flow rate of TMAl was set to 80sccm, the flow rate of tmga was set to 100sccm, the flow rate of ash 3 was set to 400sccm, the flow rates of PH 3 in the first and third strain compensation layers were set to 100sccm, and the flow rate of PH 3 in the second strain compensation layer was set to 600sccm. The number of quantum well/quantum barrier cycle pairs in the first light emitting active layer is 6, and the light emitting region is undoped. In the process of growing the luminous active layer, adopting a pause purging mode for growth, and specifically comprising the following steps: before and after the starting and finishing of growing the InGaAs material of each quantum well layer, only introducing AsH 3, stopping introducing the material of other sources into the reaction chamber, and purging the surface of the epitaxial layer, wherein the flow of AsH 3 is set to 400sccm, and the purging time of each time is 2s;
(11) Growing an intermediate strain relief layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa and AsH 3、PH3, and growing GaAsP material with the thickness of 60nm, wherein the layer is undoped;
(12) Growing a second light emitting active layer: setting the temperature of the reaction chamber to 670 ℃, introducing TMGa, TMAl, TMIn, asH 3、PH3, and growing the materials of the quantum well layer and the quantum barrier layer (the value of x4 is 0.16, the value of y1 is 0) of In 0.16Ga0.84As、(Aly1Ga1-y1)0.5As0.5 P respectively, wherein the thickness of the single-layer quantum well layer is 6nm, and the single-layer barrier layer is formed by combining a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, and the thicknesses are 4nm, 10nm and 4nm In sequence. When the quantum barrier layer was grown, the flow rate of TMAl was set to 80sccm, the flow rate of tmga was set to 100sccm, the flow rate of ash 3 was set to 400sccm, the flow rates of PH 3 in the first and third strain compensation layers were set to 100sccm, and the flow rate of PH 3 in the second strain compensation layer was set to 600sccm. The number of quantum well/quantum barrier cycle pairs in the second light emitting active layer is 6, and the light emitting region is undoped. In the process of growing the luminous active layer, adopting a pause purging mode for growth, and specifically comprising the following steps: before and after the starting and finishing of growing the InGaAs material of each quantum well layer, only introducing AsH 3, stopping introducing the material of other sources into the reaction chamber, and purging the surface of the epitaxial layer, wherein the flow of AsH 3 is set to 400sccm, and the purging time of each time is 2s;
(13) And (3) growing a P-plane space layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, and growing an Al 0.05Ga0.95 As material (the value of x3 is 0.05) with the thickness of 5000nm, wherein the layer is undoped;
(14) Growing a P-type limiting layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, growing Al x2Ga1-x2 As material with the thickness of 400nm (the value of x2 is 0.2), and taking CCl 4 As an N-type dopant, wherein the doping concentration is 2 multiplied by 10 18cm-3;
(15) And (3) growing a P-type current expansion layer: setting the temperature of the reaction chamber to 680 ℃, introducing TMGa, TMAl, asH 3, growing Al 0.1Ga0.9 As material with the thickness of 2000nm (the value range of x1 is 0.1), and adopting SiH 4 As an N-type dopant, wherein the doping concentration is 3 multiplied by 10 18cm-3;
(16) And (3) growing a P-type window layer: setting the temperature of the reaction chamber to 630 ℃, introducing TMGa and PH 3, growing GaP material with the thickness of 150nm, adopting CP 2 Mg as a P-type doping agent, and doping the GaP material with the doping concentration of 1 multiplied by 10 19cm-3;
(17) Taking a piece: and after the growth is finished, the temperature of the MOCVD reaction chamber is reduced to 110 ℃, then the pressure is regulated to 1000mbar, the reaction chamber is opened, and the epitaxial wafer is taken out.
Comparative example 1
A conventional 940nm reversed polarity LED epitaxial wafer is obtained by a conventional method, and the structural schematic diagram of the conventional 940nm reversed polarity LED epitaxial wafer is shown in figure 1.
Test examples
1. The 940nm reversed-polarity LED epitaxial wafer obtained in example 1 and the conventional 940nm reversed-polarity LED epitaxial wafer obtained in comparative example 1 were tested under continuous pulse current operation, and the change curve of the light-emitting power with the current is shown in fig. 4, wherein a is the 940nm reversed-polarity LED epitaxial wafer obtained in example 1 of the present invention, and b is the conventional 940nm reversed-polarity LED epitaxial wafer obtained in comparative example 1. As can be seen from the results of fig. 4, as the operating current continues to increase, the conventional LED chip begins to decay significantly under high current conditions, and the LED chip power of the present invention remains stable.
2. The surface morphology of the 940nm reversed-polarity LED epitaxial wafer obtained in example 1 and the conventional 940nm reversed-polarity LED epitaxial wafer obtained in comparative example 1 were observed under a microscope, and the results are shown in fig. 5, wherein (a) is the 940nm reversed-polarity LED epitaxial wafer obtained in example 1 of the present invention, and (b) is the conventional 940nm reversed-polarity LED epitaxial wafer obtained in comparative example 1. As can be seen from the result of fig. 5, the surface lattice of the 940nm reverse polarity LED epitaxial wafer obtained in the embodiment 1 of the present invention is flat, and no mismatch lines are generated; and the apparent morphology of the conventional 940nm reversed polarity LED epitaxial wafer obtained in the comparative example 1 has obvious lattice mismatch lines.
In summary, the strain relief layers GaAsP material are introduced at the two sides and the middle of the light-emitting active region, and the quantum well/quantum barrier structure with gradually changed PH 3 and the pause purging type epitaxial growth method are combined, so that the problems of insufficient light-emitting efficiency, apparent lattice mismatch of an epitaxial wafer, light effect attenuation in the using process and the like in the existing structure can be effectively solved, and the 940nm reversed polarity infrared LED has the advantages of high light-emitting efficiency, high brightness, good reliability and stability and the like, and is suitable for pulse current working conditions.
Finally, it should be emphasized that the foregoing description is merely illustrative of the preferred embodiments of the invention, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and principles of the invention, and any such modifications, equivalents, improvements, etc. are intended to be included within the scope of the invention.
Claims (6)
1. The 940nm reverse polarity infrared LED epitaxial wafer is characterized in that the LED epitaxial wafer sequentially grows from bottom to top, and a GaAs buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-face space layer, an N-face strain relief layer, a first light-emitting active layer, an intermediate strain relief layer, a second light-emitting active layer, a P-face strain relief layer, a P-face space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer are sequentially arranged from a GaAs substrate;
The N-face strain relief layer, the middle strain relief layer and the P-face strain relief layer are all made of GaAsP and are undoped;
the thicknesses of the N-face strain relief layer and the P-face strain relief layer are 300-500 nm; the thickness of the intermediate strain relief layer is 60 nm-70 nm;
The preparation method of the LED epitaxial wafer comprises the following steps: sequentially growing a GaAs buffer layer, a corrosion stop layer, an N-type ohmic contact layer, an electrode protection layer, an N-type current expansion layer, an N-type limiting layer, an N-side space layer, an N-side strain relief layer, a first light-emitting active layer, an intermediate strain relief layer, a second light-emitting active layer, a P-side strain relief layer, a P-side space layer, a P-type limiting layer, a P-type current expansion layer and a P-type window layer on a GaAs substrate by using MOCVD equipment; the first light-emitting active layer and the second light-emitting active layer are periodic circulation structures in which quantum well layers and quantum barrier layers alternately grow; the quantum barrier layer is sequentially provided with a first strain compensation layer, a second strain compensation layer and a third strain compensation layer from bottom to top; the quantum well layer and the quantum barrier layer are grown in a pause purging type growth mode;
The materials of the first strain compensation layer, the second strain compensation layer and the third strain compensation layer in the quantum barrier layer are (Al y1Ga1-y1)0.5As0.5 P, the thicknesses of the first strain compensation layer and the third strain compensation layer are 4 nm-8 nm, the thickness of the second strain compensation layer is 10 nm-20 nm, and the value range of y1 is 0.1-0.2;
The quantum barrier layer growth steps are as follows: setting the temperature of a reaction chamber to 670+/-20 ℃, introducing TMAl, TMGa, asH 3、PH3, growing a first strain compensation layer, a second strain compensation layer and a third strain compensation layer, wherein the materials are AlGaAsP, the thicknesses of the AlGaAsP are sequentially 4 nm-8 nm, 10 nm-20 nm and 4 nm-8 nm, wherein the flow of TMAL is set to 80-120 sccm, the flow of TMGa is set to 100-150 sccm, the flow of AsH 3 is set to 400-500 sccm, the PH 3 flow when the first strain compensation layer and the third strain compensation layer are grown is set to 100-200 sccm, and the PH 3 flow when the second strain compensation layer is grown is set to 600-800 sccm;
the step of the pause purging type growth mode comprises the following steps: the temperature of the reaction chamber is set to 680+/-20 ℃, materials of other sources are closed to enter the reaction chamber before and after the start and the end of the growth of each quantum well layer, and only AsH 3 is introduced to purge the surface of the epitaxial layer, wherein the flow of AsH 3 is set to 400-500 sccm, and the purging time of each time is 2-5 s.
2. The 940nm reverse polarity infrared LED epitaxial wafer of claim 1, wherein the first light emitting active layer and the second light emitting active layer are formed into light emitting active layers, the light emitting active layers are periodic circulation structures with alternately grown quantum well layers and quantum barrier layers, and the number of circulation pairs is 6-8.
3. The 940nm reverse polarity infrared LED epitaxial wafer of claim 1, wherein the quantum well layer is made of In x4Ga1-x4 As, the thickness of a single well is 6 nm-8 nm, and the value range of x4 is 0.16-0.18.
4. The 940nm reverse polarity infrared LED epitaxial wafer of claim 1, wherein the materials of the corrosion cut-off layer and the electrode protection layer are Ga 0.5In0.5 P, the doping materials are Si, the doping concentrations are 1.5 x 10 18cm-3～3.0×1018cm-3, the thickness of the corrosion cut-off layer is 200 nm-400 nm, and the thickness of the electrode protection layer is 20 nm-40 nm; the N-type ohmic contact layer is made of GaAs, the doping material is Si, the doping concentration is 2.0X10 18cm-3～5.0×1018cm-3, and the thickness is 40-80 nm.
5. The 940nm reverse polarity infrared LED epitaxial wafer according to claim 1, wherein the materials of the N-type current expansion layer and the P-type current expansion layer are Al x1Ga1-x1 As, and the value range of x1 is 0.1-0.2; the doping material of the N-type current expansion layer is Si, the doping concentration is 3.0X10 18cm-3～6.0×1018cm-3, and the thickness is 7000 nm-8000 nm; the doping material of the P-type current expansion layer is C, the doping concentration is 3.0X10 18cm-3～6×1018cm-3, and the thickness is 2000 nm-3000 nm; the materials of the N-type limiting layer and the P-type limiting layer are Al x2Ga1-x2 As, wherein the value range of x2 is 0.2-0.4, the thickness of the N-type limiting layer is 300-500 nm, the doping material is Si, and the doping concentration is 2X 10 18cm-3～4×1018cm-3; the thickness of the P-type limiting layer is 400-600 nm, the doping material is C, and the doping concentration is 2X 10 18cm-3～4×1018cm-3; the materials of the N-surface space layer and the P-surface space layer are Al x3Ga1-x3 As, wherein the value range of x3 is 0.05-0.15, the thicknesses of the N-surface space layer and the P-surface space layer are 500-800 nm, and the N-surface space layer and the P-surface space layer are undoped.
6. The 940nm reverse polarity infrared LED epitaxial wafer of claim 1, wherein the N-sided strain relief layer growth step comprises: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the N-surface space layer, and growing GaAsP material with the thickness of 300-500 nm, wherein the flow rate of the TMGa is set to 100-150 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 300-400 sccm;
The intermediate strain relief layer growth steps are: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the first light-emitting active layer, and growing GaAsP material with the thickness of 60-70 nm, wherein the flow rate of the TMGa is set to 60-80 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 600-700 sccm;
The growth steps of the P-plane strain relief layer are as follows: setting the temperature of the reaction chamber to 680+/-20 ℃, introducing TMGa and AsH 3、PH3 into the second light-emitting active layer, and growing GaAsP material with the thickness of 300-500 nm, wherein the flow rate of the TMGa is set to 100-150 sccm, the flow rate of the AsH 3 is set to 400-500 sccm, and the flow rate of the PH 3 is set to 300-400 sccm.
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| CN117976791A (en) | 2024-05-03 |
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