CN117971770A - SoC pre-silicon performance and power consumption estimation method - Google Patents
SoC pre-silicon performance and power consumption estimation method Download PDFInfo
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Abstract
The invention discloses a method for estimating performance and power consumption before SoC silicon, which comprises the steps of building a directed acyclic graph with functions as node tasks and data transmission quantity between two functions as edges by decomposing an on-chip application program of the SoC, distributing all node tasks to each computation IP core to obtain a node IP set of each node task, determining an optimal distribution mode between the node tasks and the computation IP cores according to set SoC estimation targets by iterative computation, and simultaneously obtaining a node IP performance and node IP power consumption information graph of each computation IP core, thereby determining the design bottleneck of the SoC, expanding the use of SoC silicon pre-test, and effectively improving the accuracy of performance and power consumption estimation in a SoC silicon pre-test stage.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a method for estimating the pre-silicon performance and power consumption of a SoC.
Background
In the development process of a System on Chip (SoC), performance evaluation before silicon is required to ensure that performance and power consumption of SoC System scenes after verification and streaming are completed meet design requirements. The performance evaluation before silicon usually adopts a benchmark test mode, an industry-accepted benchmark test program is executed, the score is obtained after the operation is finished, and the score is compared with the score of a standard chip to obtain the performance quality. However, the existing pre-silicon performance evaluation method cannot obtain the optimal allocation method of each function and IP in the SoC system.
Disclosure of Invention
In view of this, the present invention provides a method for estimating performance and power consumption before SoC silicon, which realizes the optimal allocation between functions and IP and the evaluation of performance and power consumption in SoC in the stage of testing before silicon.
The invention provides a method for estimating the pre-silicon performance and power consumption of a SoC, which comprises the following steps:
Step 1, determining the topology structure and the calculation performance of a calculation IP core in a SoC chip, wherein the calculation performance comprises unit data transmission energy consumption and unit data access energy consumption; decomposing an on-chip application program of the SoC into a directed acyclic graph, marking the directed acyclic graph as an SoC graph, marking a node in the SoC graph as a function in the on-chip application program as a node task, and marking the side as the data transmission quantity between the two functions;
Step 2, deploying node tasks on each computing IP core to be respectively executed, and respectively recording computing time and energy consumption as node computing performance and node computing power consumption; measuring data transmission quantity, marking the product of the data transmission quantity and unit data transmission energy consumption as node transmission power consumption, and marking the quotient of the data transmission quantity and bus bandwidth as node transmission performance; measuring the data access amount of the access memory, marking the product of the data access amount and the unit data access energy consumption as node memory access power consumption, and marking the quotient of the data access amount and the storage bandwidth as node memory access performance; taking the sum of node calculation performance, node transmission performance and node memory access performance as node IP performance, taking the sum of node calculation power consumption, node transmission power consumption and node memory access power consumption as node IP power consumption, and constructing an IP set with the node IP performance and the node IP power consumption for each node task to be recorded as a node IP set;
Step 3, configuring a first node task T1 of the SoC diagram to a computation IP core closest to an estimation target in a node IP set according to the estimation target, taking the T1 as a current round of node tasks Ti and i as round serial numbers;
step 4, determining a subsequent task list of Ti by the SoC diagram, and executing step 7 if the subsequent task list is empty; otherwise, the subsequent task list contains K node tasks, which are recorded as { Ti1, ti2, ti3, & gt, tiK }, and the step 5 is executed;
Step 5, distributing all node tasks Tik in the subsequent task list to the calculation IP core closest to the estimation target according to the node IP set, wherein k is the sequence number of the node task in the subsequent task list; if the computing IP cores have overlapping conflict, determining a global optimal distribution mode of the computing IP cores closest to an estimation target of all distributed node tasks by adopting a parallel node task distribution mode, and executing the step 6; otherwise, directly executing the step 6;
Step 6, calculating the sum of node IP performances and the sum of node IP power consumption of the node tasks executed by the IP core which is allocated with the node tasks according to the topological structure; and then taking all node tasks in the current subsequent task list as the current round of node tasks Ti, and executing the step 4;
And 7, outputting a global optimal allocation mode from the node tasks in the SoC to the computation IP cores, and node IP performance and node IP power consumption information graphs of each computation IP core, and determining the design bottleneck of the SoC according to the information graphs.
Further, the computing IP core is a CPU.
Further, the estimation targets are highest performance or lowest power consumption.
Further, in the step 5, the global optimal allocation method for determining the closest estimated target of the computing IP cores of all allocated node tasks by adopting the parallel node task allocation method specifically includes:
S1, setting the maximum iteration number N, and calculating the number of IP cores, wherein the population scale G=the number of node tasks; recording the current execution times as n, wherein n=0;
S2, randomly distributing each node task to a selected calculation IP core to form an allocation scheme until G allocation schemes are formed, wherein each allocation scheme is a chromosome;
s3, calculating the node IP performance or the node IP power consumption of each chromosome according to the estimation targets;
S4, selecting chromosomes for crossing and mutation by using a roulette selection method;
s5, enabling N to be added with 1, if N is not greater than N, executing S2, otherwise ending the flow.
Further, the way of crossing and mutation is:
Randomly selecting two chromosomes, exchanging part of the chromosomes, and finishing crossing; and randomly selecting any node task, and reassigning the node task to another computing IP core to complete mutation.
Further, in the step 3, all the node tasks are first distributed to the CPU for execution.
Advantageous effects
The invention establishes a directed acyclic graph taking functions as node tasks and taking data transmission quantity between two functions as edges by decomposing an on-chip application program of the SoC, distributes all the node tasks to each computing IP core to obtain a node IP set of each node task, and then determines an optimal distribution mode between the node tasks and the computing IP cores according to set SoC estimation targets by iterative computation, and simultaneously obtains a node IP performance and a node IP power consumption information graph of each computing IP core, thereby determining the design bottleneck of the SoC, expanding the use of SoC pre-silicon test and effectively improving the performance and the accuracy of power consumption estimation in the pre-SoC pre-silicon test stage.
Drawings
Fig. 1 is a schematic diagram illustrating a decomposition of a directed acyclic graph formed by an on-chip SoC application in a method for estimating pre-silicon performance and power consumption of an SoC according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the following examples.
The invention provides a method for estimating the pre-silicon performance and power consumption of a SoC, which specifically comprises the following steps:
Step 1, determining the topology structure of each computation unit module (computation IP core) in the SoC chip and the computation performance, bandwidth, frequency and other attributes of each computation IP core, wherein the computation performance comprises unit data transmission energy consumption and unit data access energy consumption.
IP in a SoC may refer to any module of individual components, typically including a CPU, digital signal processor, memory, peripheral controller, etc., with the compute IP core typically being the CPU. The SoC design architecture needs to connect each compute IP core according to a set topology.
Step2, decomposing an on-chip application program of the SoC, describing in a mode of a directed acyclic graph (DIRECTED ACYCLIC GRAPH, DAG), and recording as an SoC graph; the nodes in the DAG are functions in the on-chip application program and are recorded as node tasks, and the edges are data transmission quantities between the two functions, as shown in an example of fig. 1.
Step 3, deploying node tasks on each computing IP core to be actually executed, measuring computing time and energy consumption, and recording the computing time and the energy consumption as node computing performance and node computing power consumption; measuring data transmission quantity, marking the product of the data transmission quantity and unit data transmission energy consumption as node transmission power consumption, and marking the quotient of the data transmission quantity and bus bandwidth as node transmission performance; measuring the data access amount of the access memory, marking the product of the data access amount and the unit data access energy consumption as node memory access power consumption, and marking the quotient of the data access amount and the storage bandwidth as node memory access performance;
Taking the sum of node computing performance, node transmission performance and node memory access performance as node IP performance, taking the sum of node computing power consumption, node transmission power consumption and node memory access power consumption as node IP power consumption, and constructing an IP set with the node IP performance and the node IP power consumption for each node task to be recorded as a node IP set.
Step 4, distributing all node tasks to a CPU, setting an estimation target according to the SoC processing requirement, when the estimation target is the highest performance, configuring a first node task T1 of the SoC graph to a calculation IP core with the highest node IP performance in the node IP set according to the node IP set obtained in the step 3, and executing the step 5 by taking the first node task as the current node task; and when the estimated target is that the power consumption is the lowest, configuring the first node task T1 of the SoC diagram to a calculation IP core with the lowest power consumption of the node IP in the node IP set according to the node IP set obtained in the step 3, and executing the step 9 by taking the first node task as the current round of node task.
Step 5, analyzing and obtaining a subsequent task list of the current round of node tasks Ti according to the SoC diagram, wherein i is a round number, and the subsequent task refers to a node task with an edge with the current round of node tasks Ti; if the subsequent task list is empty, executing the step 13; otherwise, the subsequent task list includes K node tasks, denoted as { Ti1, ti2, ti3,.. TiK }, and step 6 is performed.
Step 6, according to the node IP set obtained in the step 3, distributing all the node tasks Tik in the subsequent task list to the calculation IP core with the highest node IP performance, wherein k is the sequence number of the node task in the subsequent task list; if the computing IP core and the computing IP cores of other distributed node tasks have overlapping conflict, determining a global optimal distribution mode with highest node IP performance of the computing IP cores of all distributed node tasks by adopting a parallel node task distribution mode, and executing the step 7; otherwise, if there is no overlap conflict, step 7 is executed.
The overlapping conflict refers to that two node tasks are allocated to the same computing IP core to be executed.
And 7, calculating the sum of node IP performances and the sum of node IP power consumption of the node tasks executed by the calculation IP cores of the distributed node tasks according to the topological structure.
And step 8, taking all the node tasks in the current and subsequent task lists as the current round of node tasks, and executing the step 5.
Step 9, analyzing and obtaining a subsequent task list of the current round of node tasks Ti according to the SoC graph, wherein the subsequent task is a node task with edges between the subsequent task and the current round of node tasks Ti; if the subsequent task list is empty, executing the step 13; otherwise, the subsequent task list contains K node tasks, denoted as { Ti1, ti2, ti3,.. TiK }, and step 10 is performed.
Step 10, distributing all node tasks Tik in a subsequent task list to a calculation IP core with lowest node IP power consumption according to the node IP set obtained in the step 3; if the IP and the calculation IP cores of other allocated node tasks have overlapping conflict, determining a global optimal allocation mode with lowest node IP power consumption of the calculation IP cores of all the allocated node tasks by adopting a parallel node task allocation mode, and executing the step 11; otherwise, if there is no overlap conflict, step 11 is performed.
And 11, calculating the sum of node IP performances and the sum of node IP power consumption of the node tasks executed by the calculation IP cores of the distributed node tasks according to the topological structure.
And step 12, taking all the node tasks in the current and subsequent task lists as the current round of node tasks, and executing the step 9.
And 13, outputting a global optimal allocation mode from the node tasks in the SoC to the computation IP cores, and node IP performance and node IP power consumption information graphs of each computation IP core, and determining the design bottleneck of the SoC according to the information graphs.
Further, the parallel node task allocation mode adopted in the invention is a parallel task allocation mode based on a genetic algorithm, and specifically comprises the following steps:
S1, setting the maximum iteration number N as 1000, wherein the population scale is as follows: g=number of node tasks/number of computation IP cores; recording the current execution times as n, wherein n=0;
s2, chromosome coding: randomly assigning each node task to a computing IP core to form an assignment scheme until G assignment schemes are formed, wherein each assignment scheme is called a chromosome;
s3, calculating the fitness: calculating the node IP performance or node IP power consumption of each chromosome;
S4, selecting: the chromosomes were selected for crossover and mutation using roulette selection in the following manner:
Crossing: randomly selecting two allocation schemes, namely chromosomes, and exchanging a part of the chromosomes;
Variation: randomly selecting a node task and reassigning the node task to another computing IP core;
s5, enabling N to be added with 1, if N is not greater than N, executing S2, otherwise ending the flow.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The method for estimating the pre-silicon performance and the power consumption of the SoC is characterized by comprising the following steps of:
Step 1, determining the topology structure and the calculation performance of a calculation IP core in a SoC chip, wherein the calculation performance comprises unit data transmission energy consumption and unit data access energy consumption; decomposing an on-chip application program of the SoC into a directed acyclic graph, marking the directed acyclic graph as an SoC graph, marking a node in the SoC graph as a function in the on-chip application program as a node task, and marking the side as the data transmission quantity between the two functions;
Step 2, deploying node tasks on each computing IP core to be respectively executed, and respectively recording computing time and energy consumption as node computing performance and node computing power consumption; measuring data transmission quantity, marking the product of the data transmission quantity and unit data transmission energy consumption as node transmission power consumption, and marking the quotient of the data transmission quantity and bus bandwidth as node transmission performance; measuring the data access amount of the access memory, marking the product of the data access amount and the unit data access energy consumption as node memory access power consumption, and marking the quotient of the data access amount and the storage bandwidth as node memory access performance; taking the sum of node calculation performance, node transmission performance and node memory access performance as node IP performance, taking the sum of node calculation power consumption, node transmission power consumption and node memory access power consumption as node IP power consumption, and constructing an IP set with the node IP performance and the node IP power consumption for each node task to be recorded as a node IP set;
Step 3, configuring a first node task T1 of the SoC diagram to a computation IP core closest to an estimation target in a node IP set according to the estimation target, taking the T1 as a current round of node tasks Ti and i as round serial numbers;
step 4, determining a subsequent task list of Ti by the SoC diagram, and executing step 7 if the subsequent task list is empty; otherwise, the subsequent task list contains K node tasks, which are recorded as { Ti1, ti2, ti3, & gt, tiK }, and the step 5 is executed;
Step 5, distributing all node tasks Tik in the subsequent task list to the calculation IP core closest to the estimation target according to the node IP set, wherein k is the sequence number of the node task in the subsequent task list; if the computing IP cores have overlapping conflict, determining a global optimal distribution mode of the computing IP cores closest to an estimation target of all distributed node tasks by adopting a parallel node task distribution mode, and executing the step 6; otherwise, directly executing the step 6;
Step 6, calculating the sum of node IP performances and the sum of node IP power consumption of the node tasks executed by the IP core which is allocated with the node tasks according to the topological structure; and then taking all node tasks in the current subsequent task list as the current round of node tasks Ti, and executing the step 4;
And 7, outputting a global optimal allocation mode from the node tasks in the SoC to the computation IP cores, and node IP performance and node IP power consumption information graphs of each computation IP core, and determining the design bottleneck of the SoC according to the information graphs.
2. The method for estimating pre-silicon performance and power consumption of a SoC of claim 1, wherein the compute IP core is a CPU.
3. The method of claim 1, wherein the estimation target is the highest performance or the lowest power consumption.
4. The method for estimating pre-SoC performance and power consumption according to claim 1, wherein in the step 5, the global optimal allocation method for determining the computing IP cores closest to the estimation target of all allocated node tasks by using a parallel node task allocation method specifically includes:
S1, setting the maximum iteration number N, and calculating the number of IP cores, wherein the population scale G=the number of node tasks; recording the current execution times as n, wherein n=0;
S2, randomly distributing each node task to a selected calculation IP core to form an allocation scheme until G allocation schemes are formed, wherein each allocation scheme is a chromosome;
s3, calculating the node IP performance or the node IP power consumption of each chromosome according to the estimation targets;
S4, selecting chromosomes for crossing and mutation by using a roulette selection method;
s5, enabling N to be added with 1, if N is not greater than N, executing S2, otherwise ending the flow.
5. The method for estimating pre-silicon performance and power consumption of a SoC of claim 4, wherein the cross-over and variation are as follows:
Randomly selecting two chromosomes, exchanging part of the chromosomes, and finishing crossing; and randomly selecting any node task, and reassigning the node task to another computing IP core to complete mutation.
6. The method for estimating pre-SoC performance and power consumption according to claim 1, wherein in step3, all node tasks are first allocated to the CPU for execution.
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| EP4300304A1 (en) * | 2022-06-29 | 2024-01-03 | Orange | Methods and systems for scheduling energy-efficient execution of periodic, real-time, directed-acyclic-graph tasks |
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| CN109962867A (en) * | 2019-03-19 | 2019-07-02 | 天津中德应用技术大学 | A kind of network-on-chip branch defines duty mapping method |
| CN111858051A (en) * | 2020-07-20 | 2020-10-30 | 国网四川省电力公司电力科学研究院 | Real-time dynamic scheduling method, system and medium suitable for edge computing environment |
| CN113946933A (en) * | 2020-11-08 | 2022-01-18 | 西北工业大学 | Combined optimization power consumption budget estimation and distribution method for dark silicon system |
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