CN117971711A - Multi-level page table traversing method and device, electronic equipment and storage medium - Google Patents

Multi-level page table traversing method and device, electronic equipment and storage medium Download PDF

Info

Publication number
CN117971711A
CN117971711A CN202410383635.8A CN202410383635A CN117971711A CN 117971711 A CN117971711 A CN 117971711A CN 202410383635 A CN202410383635 A CN 202410383635A CN 117971711 A CN117971711 A CN 117971711A
Authority
CN
China
Prior art keywords
page table
level
hit
data
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202410383635.8A
Other languages
Chinese (zh)
Other versions
CN117971711B (en
Inventor
苏叶华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Denglin Juzhen Technology Co ltd
Shanghai Denglin Technology Co ltd
Original Assignee
Shanghai Denglin Juzhen Technology Co ltd
Shanghai Denglin Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Denglin Juzhen Technology Co ltd, Shanghai Denglin Technology Co ltd filed Critical Shanghai Denglin Juzhen Technology Co ltd
Priority to CN202410383635.8A priority Critical patent/CN117971711B/en
Publication of CN117971711A publication Critical patent/CN117971711A/en
Application granted granted Critical
Publication of CN117971711B publication Critical patent/CN117971711B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The application relates to a multi-level page table traversing method, a device, electronic equipment and a storage medium, and belongs to the field of computers. The multi-level page table walk method comprises the following steps: acquiring a page table traversal request; searching whether page table data hit in the page table cache exist or not, wherein the page table cache stores traversed page table data; if the hit page table data exists, traversing a next-level page table based on the hit page table data and the page table traversing request until the last-level page table is traversed, wherein the next-level page table is a next-level page table of a page table level corresponding to the hit page table data. The application can improve the traversing efficiency of the page table and the address conversion efficiency.

Description

Multi-level page table traversing method and device, electronic equipment and storage medium
Technical Field
The application belongs to the field of computers, and particularly relates to a multi-level page table traversing method, a device, electronic equipment and a storage medium.
Background
With the increasing computing performance of computing systems and the increasing demand for big data applications, big memory management is a necessary requirement for modern high-performance computing systems, and 64-bit memory addressing space has become a normal state. One problem with large memories is: the page table itself requires a significant amount of memory space. To solve this problem, multi-level page tables are introduced, which consist of two or more levels of paging tables, also known as hierarchical paging. The entry for the level 1 (level 1) page table is a pointer to the level 2 (level 2) page table, the entry for the level 2 page table is a pointer to the level 3 (level 3) page table, and so on. The last stage page table stores the actual page table information. The reason for introducing multi-level page tables is to avoid storing all page tables in memory, and unnecessary page tables are not reserved. The page table of the virtual memory may be up to 4-6 levels. The page table for a 48bit virtual address, such as is popular today, is a 4-level page table, which is allocated roughly as follows: address [47:38] is the address offset of the first stage page table, address [37:29] is the address offset of the second stage page table, address [28:21] is the address offset of the third stage page table, and address [20:12] is the address offset of the fourth stage page table (the last stage page table). A 48-bit address page table walk requires 4 address add operations and 4 read memory operations. The read memory operations are very time consuming, each of which may require hundreds of clock cycles (cycles), resulting in very slow traversal of the entire page table.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide a multi-level page table walk method, apparatus, electronic device, and storage medium, so as to improve the efficiency of page table walk.
Embodiments of the present application are implemented as follows:
In a first aspect, an embodiment of the present application provides a multi-level page table walk method, including: acquiring a page table traversal request; searching whether page table data hit in the page table cache exist or not, wherein the page table cache stores traversed page table data; if the hit page table data exists, traversing a next-level page table based on the hit page table data and the page table traversing request until the last-level page table is traversed, wherein the next-level page table is a next-level page table of a page table level corresponding to the hit page table data.
In the above embodiment, after the page table walk request is obtained, in order to improve the walk efficiency of the page table, instead of directly performing multi-level page table walk based on the page table walk request, whether there is page table data hitting the page table walk request is first searched in the page table cache, and if there is hit page table data, the walk of the page table of the next level is performed based on the hit page table data and the page table walk request. The intermediate result of the traversed page table is stored for the subsequent page table to traverse and find, so that the purpose of acceleration is achieved, and the same part in the traversing process of different page tables does not need to be subjected to repeated and time-consuming operation, thereby improving the traversing efficiency of the page table and improving the address conversion efficiency.
With reference to a possible implementation manner of the first aspect embodiment, searching in a page table cache whether there is page table data hitting the page table walk request includes: respectively acquiring the address offset of each stage of page table in the page table traversal request; obtaining a TAG address corresponding to each stage of page table according to the obtained address offset, wherein the TAG address corresponding to the i-th stage page table comprises address offsets from the 1-th stage page table to the i-th stage page table, i is 1 to n in sequence, and n is the maximum page table level; and searching whether page table data corresponding to the TAG address is hit or not in a page table cache according to the TAG address corresponding to each stage of page table.
In the above embodiment, the address offset of each stage of page table in the page table traversal request is obtained, so as to obtain the TAG address corresponding to each stage of page table, and then based on the TAG address corresponding to each stage of page table, whether the page table data corresponding to the TAG address is hit is searched in the page table cache, so that whether the page table data hit the page table traversal request can be rapidly and accurately judged.
With reference to a possible implementation manner of the first aspect embodiment, according to a TAG address corresponding to each level of page table, searching whether page table data corresponding to the TAG address is hit in a page table cache includes: and (3) adopting a parallel searching method to search whether page table data hitting the TAG address corresponding to each level of page table exist in the page table cache or not.
In the above embodiment, a parallel search method is adopted, so that whether page table data hit in the TAG address corresponding to each stage of page table exists or not can be quickly searched, and the search time can be shortened.
With reference to a possible implementation manner of the first aspect embodiment, the page table data includes: page table level, TAG address and corresponding data; traversing a next-level page table based on the hit page table data and the page table traversing request, including: if the plurality of page table data is hit, acquiring page table data with the largest page table level in the hit plurality of page table data, and traversing the page table with the next level based on the page table data with the largest page table level and the page table traversing request.
In the above embodiment, if multiple page table data are hit, the highest Level (Level) page table data in all the hit page table data is selected to accelerate the page table walk, because the higher the Level (Level) hit, the fewer walk steps remain.
With reference to a possible implementation manner of the first aspect embodiment, according to a TAG address corresponding to each level of page table, searching whether page table data corresponding to the TAG address is hit in a page table cache includes: and (3) searching whether page table data hitting the TAG address corresponding to each level of page table exist in a page table cache by adopting a serial searching method.
In the above embodiment, a serial lookup method is used to find out whether the page table data hit in the TAG address corresponding to each level of page table is in the page table cache, so that the design requirement on the page table cache can be reduced, and the applicability of the scheme is increased.
With reference to a possible implementation manner of the first aspect embodiment, a serial lookup method is adopted to find whether there is page table data hitting a TAG address corresponding to each level of page table in a page table cache, including: and (3) searching whether page table data hitting the TAG address corresponding to each level of page table exist in a page table cache by adopting an inverted serial searching method.
In the above embodiment, the reverse serial lookup method is adopted to find whether the page table data hit the TAG address corresponding to each level of page table exists in the page table cache, so that the lookup time can be further shortened compared with the serial lookup method, and the page table lookup efficiency is accelerated.
With reference to a possible implementation manner of the first aspect embodiment, the method further includes: and if the page table data is not hit, performing multi-stage page table traversal based on the page table traversal request, and storing the page table data of each stage of page table traversal into the page table cache.
In the above embodiment, if there is no hit page table data, multi-level page table walk is directly performed based on the page table walk request, and the page table data of each level of page table walk is stored in the page table cache for subsequent page table walk, so as to achieve the purpose of acceleration.
In a second aspect, an embodiment of the present application further provides a multi-level page table walk apparatus, including: the device comprises an acquisition module, a search module and a traversal module; the acquisition module is used for acquiring a page table traversal request; the searching module is used for searching whether page table data hitting the page table traversing request exist in a page table cache, wherein the page table cache is cached with the traversed page table data; the traversing module is used for traversing the next-level page table based on the hit page table data and the page table traversing request until the last-level page table is traversed, wherein the next-level page table is the next-level page table of the page table level corresponding to the hit page table data.
In a third aspect, an embodiment of the present application further provides an electronic device, including: the device comprises a memory and a processor, wherein the processor is connected with the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform a multi-level page table walk method as provided by the above-described first aspect embodiment and/or any one of the possible implementations in combination with the above-described first aspect embodiment.
In a fourth aspect, embodiments of the present application further provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs a multi-stage page table walk method as provided by the embodiments of the first aspect and/or any of the possible implementations in combination with the embodiments of the first aspect.
The beneficial effects of the embodiments of the second aspect to the fourth aspect are the same as those of the embodiments of the first aspect, and are not described here again.
Additional features and advantages of the application will be set forth in the description which follows. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings.
Fig. 1 is a schematic diagram of a 4-level page table walk according to an embodiment of the present application.
Fig. 2 is a schematic flow chart of a multi-level page table walk method according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a principle of finding whether there is hit page table data in a page table cache according to an embodiment of the present application.
Fig. 4 is a schematic block diagram of a multi-level page table walk device according to an embodiment of the present application.
Fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The following examples are given by way of illustration for more clearly illustrating the technical solution of the present application, and are not to be construed as limiting the scope of the application. Those skilled in the art will appreciate that the embodiments described below and features of the embodiments can be combined with one another without conflict.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another entity or action in the description of the application without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Furthermore, the term "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.
In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the term "electrically coupled" may be either directly or indirectly via an intermediate medium.
In order to facilitate an understanding of the traversal process of the multi-level page table, the following describes the traversal process of the 4-level page table of the 48-bit virtual address, in conjunction with the schematic diagram shown in fig. 1. The 48bit virtual address may be divided into A, B, C, D and an offset, A is the address offset of the first stage page table, B is the address offset of the second stage page table, C is the address offset of the third stage page table, D is the address offset of the fourth stage page table, and the offset plus the memory address (T) stored by the fourth stage page table is equal to the final physical address.
The traversal process of the first stage page table is: the starting address (base_register) of the first stage page table plus the address offset (a) of the first stage page table yields a storage address that holds X, i.e., addr (X) =base_register+a, where X is the starting address pointing to the second stage page table. This step requires performing an address addition operation and a read access operation, i.e., reading address Addr (X) to get X.
The traversal process of the second-stage page table is: the starting address (X) of the second stage page table is added to the address offset (B) of the second stage page table to obtain a storage address storing Y, i.e., addr (Y) =x+b, where Y is the starting address pointing to the third stage page table. This step also requires performing an address addition operation and a read access operation, i.e., reading address Addr (Y) to get Y.
The traversal process of the third-stage page table is as follows: the starting address (Y) of the third stage page table plus the address offset (C) of the third stage page table yields a storage address holding Z, i.e., addr (Z) =y+c, where Z is the starting address pointing to the fourth stage page table. This step also requires performing an address addition operation and a read access operation, i.e., reading address Addr (Z) to obtain Z.
The traversal process of the fourth-stage page table is: the starting address (Z) of the fourth-stage page Table plus the address offset (D) of the fourth-stage page Table yields a storage address storing T, i.e., addr (T) =z+d, where T (Table) is the fourth-stage page Table itself, i.e., the real page Table. This step also requires performing an address addition operation and a read access operation, i.e., reading address Addr (T) to get T.
After the above 4 traversals, the access of the 4-level page table is completed, and it can be seen that a page table traversal with 48-bit address requires 4 address addition operations and 4 read access memory operations. Also, each 4-level page table walk requires these 4 address add operations and 4 read memory operations, which results in a very slow walk through the entire page table.
In order to improve the traversing efficiency of a page table and improve the address conversion efficiency, the embodiment of the application provides a multi-stage page table traversing method, a multi-stage page table traversing device, electronic equipment and a storage medium. An improved multi-level page table walk method of an embodiment of the present application will be described with reference to FIG. 2. In one embodiment, the execution body of the multi-level page table walk method may be a chip, such as a processor, AI (ARTIFICIAL INTELLIGENCE ) chip, or the like.
S1: a page table walk request is obtained.
The page table walk request carries a virtual address, for example, a virtual address with 48 bits, and when virtual address translation is required, the page table walk request can be sent out based on the virtual address to be translated. In an alternative embodiment, a page table walk control module, which may be a chip, obtains a page table walk request.
S2: and searching whether page table data hitting the page table traversing request exist in a page table cache.
After the page table traversing request is obtained, in order to improve the traversing efficiency of the page table, multi-level page table traversing is not directly performed based on the page table traversing request, but whether page table data hitting the page table traversing request exist or not is searched in a page table cache, wherein the page table cache stores the traversed page table data. If there is hit page table data, step S3 is performed, and if there is no hit page table data, step S4 is performed.
It is contemplated that there may be many steps that are identical during two different page table traversal. For example, in the case of the 48-bit virtual address access described above, in the case of a continuous memory space access, when the address jumps from one page table to the next, the portions of the address { A, B, C } of the two consecutive page tables are identical, with the only difference being the portion D. In some cases, an ordered memory allocation space (typically a limited address space) is required, and although the memory address spaces may fall on different page tables, the page tables will typically have the same high address portion, e.g., A the same, or { A, B } the same, or even { A, B, C } the same.
The main idea of the accelerating page table traversal design proposal provided by the application is to store the intermediate result of the traversed page table for the subsequent page table traversal and searching, thereby achieving the purpose of accelerating. Thus, the same part of the traversal process of the different page tables does not need to be subjected to repeated and time-consuming operations. If the page table is traversed at level 4, it can be simply deduced that the traversal time of the new page table is respectively shortened to 25%,50% and 75% under the condition that the page table at level 1 (address A part), the page table at level 2 (address { A, B } part) or the page table at level 3 (address { A, B, C } part) is the same, and the traversal performance of the page table can be greatly improved.
In one embodiment, a hardware cache may be added to a page table traversal control module of the chip, which is named as "page table acceleration cache", and may be referred to as "page table cache" for short. The intermediate result of the page table traversal is stored, so that the purpose of accelerating the page table traversal is achieved. The basic idea is that when a page table traversing request is received by the page table control module, whether the previous traversing history record can be used or not is searched in the page table cache, if yes, the traversing process can be shortened, and even all steps of traversing are completely omitted.
The structure selection of the page table cache can be direct mapping (DIRECT MAP), group connection (set-associative) or full correlation (full-associative), and a user can select the own cache structure according to the requirement. The structure of the page table cache is not the key point of the application, and the application focuses on how to use the page table cache to store the intermediate result of the page table traversal so as to achieve the purpose of accelerating the page table traversal.
In one embodiment, page table data stored by a page table cache may include a page table Level (Level), a TAG address, and corresponding data (data). The data corresponding to the TAG address is the data stored in the memory at that address. Taking 4-level page table traversal as an example, the traversal result of each level page table has their own meaning, for example, the traversal result of the page table of the first 3 levels is a pointer to the next level page table, and the traversal result of the last level page table is the last page table itself. Since the traversing result of each Level of page table has different meanings, when they are stored in the page table cache, page table levels, i.e., level 1, level 2, level 3, level 4, need to be stored while storing the TAG address.
In one embodiment, the format of the page table data stored in the page table cache is shown in Table 1.
TABLE 1
Level TAG address Data
1 A X
2 A，B Y
3 A，B，C Z
4 A，B，C，D T
Wherein a in table 1 represents an address offset of the first stage page table, B represents an address offset of the second stage page table, C represents an address offset of the third stage page table, and D represents an address offset of the fourth stage page table.
When the result (data) of the traversal of the first-level page table is stored in the page table cache, the level field is marked as 1, and the TAG address field only needs to store the a part, because the traversal of the first-level page table is useful only for the a part, and the TAG address field can store any value in other parts than the a part.
When the result of the second-level page table walk is stored in the page table cache, the level field is marked as 2, the TAG field only needs to store the { A, B } portion, since the second-level page table walk is useful only for the { A, B } portion, and the TAG field can store any value in addition to the { A, B } portion.
When the result of the traversal of the third-level page table is stored in the page table cache, the level field is marked as 3, and the TAG address field only needs to store the { A, B, C } portion, since the traversal of the third-level page table is useful only for the { A, B, C } portion, and the TAG address field can store any value in addition to the { A, B, C } portion.
When the result of the fourth level page table walk is stored in the page table cache, the level field is marked 4 and the TAG address field stores the { A, B, C, D } portion, i.e., the full address.
The TAG address is not limited to the form shown in table 1, and in an alternative embodiment, the format of the page table data stored in the page table cache may be as shown in table 2.
TABLE 2
Level TAG address Data
1 Base_register+ A X
2 Base_register +A+B Y
3 Base_register+A+B+C Z
4 Base_register+ A+B+C+D T
Where Base_Register represents the starting address.
The implementation process of S2 may be: respectively acquiring the address offset of each stage of page table in the page table traversal request; obtaining a TAG address corresponding to each stage of page table according to the obtained address offset, wherein the TAG address corresponding to the i-th stage page table comprises address offsets from the 1-th stage page table to the i-th stage page table, i is 1 to n in sequence, and n is the maximum page table level; and searching whether page table data corresponding to the TAG address is hit or not in a page table cache according to the TAG address corresponding to each stage of page table. The implementation principle is shown in fig. 3.
When a serial lookup method is adopted to find out whether the page table data corresponding to the TAG address is hit in the page table cache, the TAG address corresponding to the subsequent page table is obtained when a lookup demand exists, for example, only the TAG address corresponding to the first-stage page table can be obtained just at first, if the page table data of the TAG address is not hit in the page table cache, the TAG address corresponding to the subsequent page table is not required to be obtained, if the page table data of the TAG address is hit in the page table cache, the TAG address corresponding to the second-stage page table is obtained, and if the page table data of the TAG address of the second-stage page table is not hit in the page table cache, the TAG address corresponding to the subsequent page table is not required to be obtained.
For ease of understanding, taking the 4-stage page table as an example, when the address offset of each stage page table in the page table walk request is acquired, taking the 48-bit virtual address as an example, address [47:38] is the address offset of the first stage page table (denoted by A), address [37:29] is the address offset of the second stage page table (denoted by B), address [28:21] is the address offset of the third stage page table (denoted by C), and address [20:12] is the address offset of the fourth stage page table (denoted by D). After the address offset of each stage of page table is obtained, the TAG address corresponding to each stage of page table can be obtained according to the obtained address offset, wherein the TAG address corresponding to the i stage of page table comprises the address offsets of the 1 st stage of page table to the i stage of page table, as shown in table 1, the TAG address corresponding to the first stage of page table is { A }, the TAG address corresponding to the second stage of page table is { A, B }, the TAG address corresponding to the third stage of page table is { A, B, C }, the TAG address corresponding to the fourth stage of page table is { A, B, C, D }, and after the TAG address corresponding to each stage of page table is obtained, whether page table data corresponding to the TAG address exist in the page table cache can be searched according to the TAG address corresponding to each stage of page table.
When searching in the page table cache, judging whether hit occurs, and considering the TAG address domain and the level domain at the same time. If the level field is a1, i.e., the first stage page table, only the comparison result of address A portion need be compared. If part A is consistent, i.e., hit. Similarly, if the level field is 2/3/4, only the { A, B }/{ A, B, C }/{ A, B, C, D } portions need to be compared and if they are identical, then a hit occurs.
In one embodiment, when the page table data is as shown in table 2, a start address is required in addition to the obtained address offset to obtain the TAG address corresponding to each stage of page table. In this embodiment, the implementation procedure of S2 may be: respectively acquiring the address offset of each stage of page table in the page table traversal request; according to the acquired address offset and the initial address, a TAG address corresponding to each stage of page table is obtained; and searching whether page table data corresponding to the TAG address is hit or not in a page table cache according to the TAG address corresponding to each stage of page table.
In one embodiment, according to the TAG address corresponding to each level of page table, the process of searching whether the page table data corresponding to the TAG address is hit in the page table cache may be: and (3) adopting a parallel searching method to search whether page table data hitting the TAG address corresponding to each level of page table exist in the page table cache or not. In still another embodiment, according to the TAG address corresponding to each level of page table, the process of searching whether the page table data corresponding to the TAG address is hit in the page table cache may be to use a serial search method to search whether the page table data corresponding to the TAG address hit in each level of page table is hit in the page table cache.
When a serial searching method is adopted, whether the page table data hit the TAG address corresponding to each level of page table exists in the page table cache or not can be judged by adopting a sequential serial searching method, whether the page table data hit the TAG address corresponding to each level of page table exists in the page table cache or not can be judged by adopting an inverse sequential serial searching method, and whether the page table data hit the TAG address corresponding to each level of page table exists in the page table cache or not can be judged by adopting an inverse sequential serial searching method.
Taking the reverse serial lookup method as an example, it may be to preferentially find whether there is page table data hitting the TAG address corresponding to the last stage page table in the page table cache, if so, no further forward finding is performed, if not, find whether there is page table data hitting the TAG address corresponding to the penultimate stage page table in the page table cache, and so on. When the reverse serial lookup method is adopted, whether page table data hit against the TAG address corresponding to the penultimate page table exists in the page table cache or not can be preferentially searched, namely, the page table data hit against the TAG address corresponding to the last page table is directly skipped, and under normal conditions, the address of the traversing request of different page tables is different, so that the page table data hit against the TAG address corresponding to the last page table is skipped, and the page table data hit against the penultimate page table is directly searched from the penultimate page table, and the page table data hit against the penultimate page table is directly skipped.
Taking a sequential serial searching method as an example, if the page table data hit in the TAG address corresponding to the first-stage page table is preferentially searched in the page table cache, if not, stopping searching, if yes, continuing to search backwards, namely, if the page table data hit in the TAG address corresponding to the second-stage page table is searched in the page table cache, and so on.
When a reverse serial searching method is adopted, if page table data hitting the TAG address corresponding to each level of page table is searched in the page table cache, if the page table data is not hit, the page table data is continuously searched until the page table is hit or all page tables are searched. When a sequential serial searching method is adopted, if page table data hitting the TAG address corresponding to each level of page table is searched in the page table cache, if the page table data hit, the page table data is continuously searched backwards until no hit occurs or all page tables are searched. The last page table data hit is subsequently used to make a walk of the next level page table.
S3: and traversing the page table of the next level based on the hit page table data and the page table traversing request until the page table of the last level is traversed.
If the hit page table data exists, traversing the next-level page table based on the hit page table data and a page table traversing request until the last-level page table is traversed, wherein the next-level page table is the next-level page table of the page table level corresponding to the hit page table data. If the hit page table data is the page table data of the last stage page table, stopping traversing.
Taking a 4-stage page table as an example, assuming that the hit page table data is the page table data of the second-stage page table, traversing the third-stage page table based on the hit page table data and a page table traversing request, and continuing traversing the fourth-stage page table until the last-stage page table is traversed after the third-stage page table is traversed.
In an alternative embodiment, the multi-level page table walk method further includes: storing the traversing results of the page tables after the page table levels corresponding to the hit page table data into a page table cache, for example, if the currently hit page table data is the traversing result of the second-stage page table, storing the traversing results of the third page table and the fourth page table into the page table cache after the traversing of the third page table and the fourth page table is completed.
In one embodiment, when a parallel lookup method is used to find whether there is page table data hitting the TAG address corresponding to each level of page table in the page table cache, a plurality of page table data may be hit, and at this time, the implementation process of S3 may be: if the plurality of page table data is hit, acquiring page table data with the largest page table level in the hit plurality of page table data, and traversing the page table with the next level based on the page table data with the largest page table level and the page table traversing request.
A page table walk request may hit multiple page table data in a page table cache. When there are multiple page table data hits, the highest Level (Level) page table data in all hit page table data is selected to accelerate the page table walk, because the higher the Level (Level) hit, the fewer walk steps remain.
S4: performing multi-stage page table traversal based on the page table traversal request, and storing page table data of each stage of page table traversal into the page table cache.
If the page table data is not hit, performing multi-stage page table traversal directly based on the page table traversal request, and storing the page table data of each stage of page table traversal into a page table cache.
For better understanding, it can be more clearly illustrated by an example that the page table cache may hit multiple page table data and how it brings about acceleration of page table traversal. If there are two requests of page tables M and N with consecutive addresses, { a, B, C } n= { a, B, C } M, dn=dm+1 because their page tables are consecutive. In the case where page table M is traversed for the first time and the page table cache is empty, none of the four level page table traversals of M will hit in the page table cache. When the M traversing is completed, the traversing results of the four-stage page table are stored in a page table cache, and the types of the stored TAG addresses correspond to levels 1,Level 2,Level 3,Level 4 respectively. When page table N needs to be traversed, parallel lookup in page table cache hits TAG address of Level 1, level 2, level 3, and TAG address of Level 4 does not hit because { A, B, C } N= { A, B, C } M, but DN-! =dm, i.e. DN is not equal to DM. Because the TAG addresses of Level 1, level 2 and Level 3 hit, page table data corresponding to the TAG address of Level 3 is fetched at this time to accelerate the traversal of the page table N, namely, the traversed result (pointing to the pointer Z of the fourth-stage page table) of the third-stage page table is directly obtained. It can be seen that, in the traversal process of the page table N, the traversal steps of the page table of 1-3 stages can be directly omitted by using the method of the present application, so that the traversal process is greatly accelerated. Of course, the fourth level walk of page table N is also performed as a normal walk.
Similarly, it can be inferred that page table O in a larger address space needs to be traversed, assuming page tables { A, B } O= { A, B } M, CO-! The first 2 stages of the walk of page table 0 may be accelerated by the page table cache, reducing the total walk time, =cm, i.e., CO is not equal to CM.
It is to be understood that all of the technical details above are set forth based on a 4-level page table. However, the thought and design of the page table acceleration proposed by the application have no direct relation with the number of page table stages, and can be applied to page table traversal of any He Jishu. The more the number of page tables, the better the acceleration effect of the design.
In one embodiment, the embodiment of the present application further provides a multi-level page table walk device 100, as shown in fig. 4, where the multi-level page table walk device 100 includes: acquisition module 110, lookup module 120, and traversal module 130.
The obtaining module 110 is configured to obtain a page table walk request.
A lookup module 120, configured to find whether there is page table data hitting the page table walk request in a page table cache, where the page table cache has page table data already traversed.
The traversing module 130 is configured to, if there is hit page table data, perform traversing of a next-level page table based on the hit page table data and the page table traversing request until traversing to a last-level page table, where the next-level page table is a next-level page table of a page table level corresponding to the hit page table data.
Optionally, a lookup module 120 is configured to obtain an address offset of each stage of page table in the page table walk request; obtaining a TAG address corresponding to each stage of page table according to the obtained address offset, wherein the TAG address corresponding to the i-th stage page table comprises address offsets from the 1-th stage page table to the i-th stage page table, i is 1 to n in sequence, and n is the maximum page table level; and searching whether page table data corresponding to the TAG address is hit or not in a page table cache according to the TAG address corresponding to each stage of page table.
Optionally, the lookup module 120 is configured to use a parallel lookup method to find whether there is page table data hitting the TAG address corresponding to each level of page table in the page table cache.
Optionally, the page table data includes: the traversing module 130 is configured to obtain, if multiple pieces of page table data are hit, page table data with a largest page table level among the multiple pieces of page table data hit, and perform traversing of a next-level page table based on the page table data with the largest page table level and the page table traversing request.
Optionally, the lookup module 120 is configured to use a serial lookup method to find whether there is page table data hitting the TAG address corresponding to each level of page table in the page table cache.
Optionally, the lookup module 120 is configured to use an inverted serial lookup method to find whether the page table cache has page table data hitting the TAG address corresponding to each level of page table.
Optionally, the traversing module 130 is further configured to perform multi-level page table traversal based on the page table traversal request if there is no hit page table data, and store the page table data of each level of page table traversal into the page table cache.
The multi-level page table walk device 100 according to the embodiment of the present application has the same implementation principle and technical effects as those of the foregoing method embodiment, and for brevity, reference may be made to the corresponding contents of the foregoing method embodiment where the device embodiment is not mentioned.
As shown in fig. 5, fig. 5 shows a block diagram of an electronic device 200 according to an embodiment of the present application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.
The transceiver 210, the memory 220, and the processor 240 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. Wherein the transceiver 210 is configured to transmit and receive data. The memory 220 is used to store a computer program, such as the software functional module shown in fig. 4, i.e., the multi-level page table walk device 100. The multi-level page table walk device 100 includes at least one software function module that may be stored in the memory 220 in the form of software or Firmware (Firmware) or cured in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute executable modules stored in the memory 220, such as software functional modules or computer programs included in the multi-level page table walk device 100. For example, the processor 240 is configured to perform the multi-level page table walk method described above.
The Memory 220 may be, but is not limited to, a random access Memory (RandomAccessMemory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
The processor 240 may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a microprocessor, etc.; but may also be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field programmable gate array (Field Programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. Or the processor 240 may be any conventional processor or the like.
The electronic device 200 includes, but is not limited to, a mobile phone, a tablet, a computer, etc.
The embodiment of the present application further provides a non-volatile computer readable storage medium (hereinafter referred to as a storage medium) storing a computer program that, when executed by a computer such as the electronic device 200 described above, performs the multi-level page table walk method described above.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a computer-readable storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned computer-readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A multi-level page table walk method, comprising:
Acquiring a page table traversal request;
searching whether page table data hit in the page table cache exist or not, wherein the page table cache stores traversed page table data;
If the hit page table data exists, traversing a next-level page table based on the hit page table data and the page table traversing request until the last-level page table is traversed, wherein the next-level page table is a next-level page table of a page table level corresponding to the hit page table data.
2. The multi-level page table walk method of claim 1, wherein looking up in a page table cache whether there is page table data hitting the page table walk request comprises:
Respectively acquiring the address offset of each stage of page table in the page table traversal request;
Obtaining a TAG address corresponding to each stage of page table according to the obtained address offset, wherein the TAG address corresponding to the i-th stage page table comprises address offsets from the 1-th stage page table to the i-th stage page table, i is 1 to n in sequence, and n is the maximum page table level;
And searching whether page table data corresponding to the TAG address is hit or not in a page table cache according to the TAG address corresponding to each stage of page table.
3. The multi-level page table walk method of claim 2, wherein looking up in the page table cache if there is page table data hit to the corresponding TAG address according to the TAG address corresponding to each level of page table, comprising:
and (3) adopting a parallel searching method to search whether page table data hitting the TAG address corresponding to each level of page table exist in the page table cache or not.
4. A multi-level page table walk method as recited in claim 3 wherein the page table data comprises: page table level, TAG address and corresponding data; traversing a next-level page table based on the hit page table data and the page table traversing request, including:
If the plurality of page table data is hit, acquiring page table data with the largest page table level in the hit plurality of page table data, and traversing the page table with the next level based on the page table data with the largest page table level and the page table traversing request.
5. A multi-level page table walk method as claimed in claim 3 wherein looking up in the page table cache if there is page table data hit to the corresponding TAG address based on the TAG address corresponding to each level of page table comprises:
And (3) searching whether page table data hitting the TAG address corresponding to each level of page table exist in a page table cache by adopting a serial searching method.
6. The multi-level page table walk method of claim 5, wherein using a serial lookup method to find whether there is page table data hitting a TAG address corresponding to each level of page table in the page table cache comprises:
And (3) searching whether page table data hitting the TAG address corresponding to each level of page table exist in a page table cache by adopting an inverted serial searching method.
7. The multi-level page table walk method of claim 1, further comprising:
And if the page table data is not hit, performing multi-stage page table traversal based on the page table traversal request, and storing the page table data of each stage of page table traversal into the page table cache.
8. A multi-level page table walk apparatus, comprising:
The acquisition module is used for acquiring a page table traversal request;
The searching module is used for searching whether page table data hitting the page table traversing request exist in a page table cache, wherein the page table cache is cached with the traversed page table data;
The traversing module is used for traversing the next-level page table based on the hit page table data and the page table traversing request until the last-level page table is traversed, wherein the next-level page table is the next-level page table of the page table level corresponding to the hit page table data.
9. An electronic device, comprising:
the device comprises a memory and a processor, wherein the processor is connected with the memory;
The memory is used for storing programs;
the processor is configured to invoke a program stored in the memory to perform the method of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, performs the method according to any of claims 1-7.
CN202410383635.8A 2024-04-01 2024-04-01 Multi-level page table traversing method and device, electronic equipment and storage medium Active CN117971711B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410383635.8A CN117971711B (en) 2024-04-01 2024-04-01 Multi-level page table traversing method and device, electronic equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410383635.8A CN117971711B (en) 2024-04-01 2024-04-01 Multi-level page table traversing method and device, electronic equipment and storage medium

Publications (2)

Publication Number Publication Date
CN117971711A true CN117971711A (en) 2024-05-03
CN117971711B CN117971711B (en) 2024-06-28

Family

ID=90863075

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410383635.8A Active CN117971711B (en) 2024-04-01 2024-04-01 Multi-level page table traversing method and device, electronic equipment and storage medium

Country Status (1)

Country Link
CN (1) CN117971711B (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10127159B1 (en) * 2017-07-13 2018-11-13 International Business Machines Corporation Link consistency in a hierarchical TLB with concurrent table walks
CN111552654A (en) * 2019-02-08 2020-08-18 三星电子株式会社 Processor for detecting redundancy of page table traversal
CN111881062A (en) * 2020-06-12 2020-11-03 海光信息技术有限公司 Paging method and device of memory pages, CPU chip and computer
US20210365499A1 (en) * 2020-05-21 2021-11-25 Intuit Inc. Method and system for traversing an object graph using traversal context objects
CN114281720A (en) * 2021-12-14 2022-04-05 海光信息技术股份有限公司 Processor, address translation method for processor and electronic equipment
CN114925002A (en) * 2022-05-23 2022-08-19 上海壁仞智能科技有限公司 Electronic device, electronic apparatus, and address conversion method
WO2023122194A1 (en) * 2021-12-22 2023-06-29 SiFive, Inc. Page table entry caches with multiple tag lengths
CN116383102A (en) * 2023-05-30 2023-07-04 北京微核芯科技有限公司 Translation look-aside buffer access method, device, equipment and storage medium

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10127159B1 (en) * 2017-07-13 2018-11-13 International Business Machines Corporation Link consistency in a hierarchical TLB with concurrent table walks
CN111552654A (en) * 2019-02-08 2020-08-18 三星电子株式会社 Processor for detecting redundancy of page table traversal
US20210365499A1 (en) * 2020-05-21 2021-11-25 Intuit Inc. Method and system for traversing an object graph using traversal context objects
CN111881062A (en) * 2020-06-12 2020-11-03 海光信息技术有限公司 Paging method and device of memory pages, CPU chip and computer
CN114281720A (en) * 2021-12-14 2022-04-05 海光信息技术股份有限公司 Processor, address translation method for processor and electronic equipment
WO2023122194A1 (en) * 2021-12-22 2023-06-29 SiFive, Inc. Page table entry caches with multiple tag lengths
CN114925002A (en) * 2022-05-23 2022-08-19 上海壁仞智能科技有限公司 Electronic device, electronic apparatus, and address conversion method
CN116383102A (en) * 2023-05-30 2023-07-04 北京微核芯科技有限公司 Translation look-aside buffer access method, device, equipment and storage medium

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
王宏宇;: "ARM MMU中虚拟地址到物理地址转换的研究", 中国电力教育, no. 3, 20 December 2008 (2008-12-20), pages 343 - 344 *
郝继锋;: "嵌入式虚拟机管理器内存虚拟化方法研究", 航空计算技术, no. 02, 25 March 2017 (2017-03-25), pages 125 - 130 *

Also Published As

Publication number Publication date
CN117971711B (en) 2024-06-28

Similar Documents

Publication Publication Date Title
CN110275864B (en) Index establishing method, data query method and computing device
CN112860592B (en) Data caching method and device based on linked list, electronic equipment and storage medium
US20020138648A1 (en) Hash compensation architecture and method for network address lookup
US20100228914A1 (en) Data caching system and method for implementing large capacity cache
US9009401B2 (en) Multi-updatable least recently used mechanism
CN115168248B (en) Cache memory supporting SIMT architecture and corresponding processor
CN116594925B (en) Address translation system, processor, address translation method and electronic equipment
CN109933543B (en) Data locking method and device of Cache and computer equipment
CN114860627B (en) Method for dynamically generating page table based on address information
US11256630B2 (en) Cache address mapping method and related device
CN114546898A (en) TLB management method, device, equipment and storage medium
US9965482B2 (en) Hash based read and write operations in a storage system
KR20120103095A (en) Memory system and memory mapping method thereof
CN107291630B (en) Cache memory processing method and device
CN114637700A (en) Address translation method for target virtual address, processor and electronic equipment
CN117331853B (en) Cache processing method, device, electronic equipment and medium
CN117971711B (en) Multi-level page table traversing method and device, electronic equipment and storage medium
CN111552653B (en) Page table reading method, device and equipment and computer storage medium
US10095630B2 (en) Sequential access to page metadata stored in a multi-level page table
US20140013054A1 (en) Storing data structures in cache
CN114741338B (en) Bypass conversion buffer, data updating method, memory management unit and chip
CN107967306B (en) Method for rapidly mining association blocks in storage system
JP2008511882A (en) Virtual address cache and method for sharing data using unique task identifiers
CN110362509B (en) Unified address conversion method and unified address space
CN111104435A (en) Metadata organization method, device and equipment and computer readable storage medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant