CN111881062A

CN111881062A - Paging method and device of memory pages, CPU chip and computer

Info

Publication number: CN111881062A
Application number: CN202010534352.0A
Authority: CN
Inventors: 姜莹; 王海洋
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-06-12
Filing date: 2020-06-12
Publication date: 2020-11-03

Abstract

The invention provides a paging method of memory pages, which comprises the following steps: searching according to a base address of a current level page table directory table in a memory page table structure and an addressing address corresponding to the current level page table directory table in a linear address to obtain a current level page table directory entry, and obtaining type information for describing the type of a next level table from the current level page table directory entry, wherein the type comprises the page table directory table and a page table; repeating the steps until the type information indicates that the next-level table is a page table; searching according to the base address of the page table and the addressing address corresponding to the page table in the linear address to obtain a page table entry in the page table, and obtaining a page base address from the page table entry; and determining a page address according to the page base address and the physical page offset. Paging can be performed for memory pages of different sizes.

Description

Paging method and device of memory pages, CPU chip and computer

Technical Field

The invention relates to a paging method and device of memory pages, a CPU chip and a computer.

Background

A page table is a special data structure that is usually used in an operating system to store the correspondence between logical addresses and physical addresses. A page is the smallest granularity that defines a contiguous segment of address space when page table partitioning is performed. For example, assuming a computer system with a 32-bit logical address space, if the page size of the system is 4KB, the page table can be as many as 100 ten thousand entries (2^32/2^ 12). Assuming that each entry (entry) has 4 bytes, each process requires 4MB of physical address space to store the page table itself, which also requires a contiguous segment of address space to be used for storage. Obviously, if one does not want to allocate this page table contiguously in memory, a simple solution is to divide the page table into smaller blocks, i.e. to hierarchy the structure of the page table.

Disclosure of Invention

Problems to be solved by the invention

The invention aims to provide a paging method and device of memory pages, a CPU chip and a computer, which can also query memories with different sizes.

Means for solving the problems

In view of the foregoing problems in the prior art, a technical solution of the present invention is to provide a method for paging a memory page, where the method includes:

searching according to a base address of a current level page table directory table in a memory page table structure and an addressing address corresponding to the current level page table directory table in a linear address to obtain a current level page table directory entry, and obtaining type information for describing the type of a next level table from the current level page table directory entry, wherein the type comprises the page table directory table and a page table;

repeating the steps until the type information indicates that the next-level table is a page table;

searching according to the base address of the page table and the addressing address corresponding to the page table in the linear address to obtain a page table entry in the page table, and obtaining a page base address from the page table entry;

and determining a page address according to the page base address and the physical page offset.

One aspect of the present invention provides a paging device for memory pages, which is characterized in that the paging device includes:

a traversal module, configured to perform lookup according to a base address of a current page table directory table in a memory page table structure and an addressing address corresponding to the current page table directory table in a linear address to obtain a current page table directory entry, and obtain type information used for describing a type of a next page table from the current page table directory entry, where the type includes the page table directory table and the page table, repeat the above steps until the type information indicates that the next page table is the page table, perform lookup according to the base address of the page table and the addressing address corresponding to the page table in the linear address to obtain a page table entry in the page table, and obtain a page base address from the page table entry; and

and the address determining module is used for determining the page address according to the page base address and the physical page offset.

One technical scheme of the invention provides a CPU chip which is characterized by comprising a plurality of crystal grains DIE, wherein each crystal grain DIE comprises at least one processor core;

the processor core performs the paging method for memory pages described above.

One aspect of the present invention provides a computer including the CPU described above.

Effects of the invention

According to the paging method of the memory pages, paging can be performed on the memory pages with different sizes.

Drawings

Fig. 1 shows the structure of a system of one embodiment of the present invention.

FIG. 2 shows a hierarchical page table structure in which a memory management unit implements 2MB pages in the prior art.

FIG. 3 shows a hierarchical page table structure in the prior art that implements a 1GB page using 2-level addressing.

FIG. 4 shows a hierarchical page table structure in which a memory management unit implements 4MB pages in the prior art.

FIG. 5 is a schematic flow chart illustrating a paging method for memory pages according to the present invention.

FIG. 6 illustrates a page table structure that supports multiple page sizes.

FIG. 7 shows a block diagram of a computer device of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be understood that these embodiments are merely provided to enable those skilled in the art to better understand and implement the present invention, and do not limit the scope of the present invention in any way. The exemplary embodiments of the present invention are provided to illustrate aspects of the present invention and should not be construed as limiting the scope of the present invention. When describing exemplary embodiments with reference to block diagrams or flowcharts, each block may represent a method step or an apparatus element for performing a method step. Depending on the implementation, the respective apparatus elements may be configured as hardware, software, firmware, or a combination thereof.

[ System Structure ]

First, the structure of the system of one embodiment of the present invention is explained. As shown in fig. 1, the system architecture 100 may include

terminal devices

101, 102, 103, 104, a network 105, and a server 106. The network 105 serves as a medium for providing communication links between the

terminal devices

101, 102, 103, 104 and the server 106.

In this embodiment, an electronic device (for example, the

terminal device

101, 102, 103, or 104 shown in fig. 1) on which the paging method of the memory page operates may perform transmission of various information through the network 105. Network 105 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few. It is noted that the wireless connection means may include, but is not limited to, a 3G/4G/5G connection, a Wi-Fi connection, a bluetooth connection, a WiMAX connection, a Zigbee connection, a UWB connection, a local area network ("LAN"), a wide area network ("WAN"), an internet network (e.g., the internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as other now known or later developed network connection means. The network 105 may communicate using any currently known or future developed network Protocol, such as HTTP (hypertext transfer Protocol), and may interconnect any form or medium of digital data communication (e.g., a communications network).

A user may use

terminal devices

101, 102, 103, 104 to interact with a server 106 via a network 105 to receive or send messages or the like. Various client applications, such as a video live and play application, a web browser application, a shopping application, a search application, an instant messaging tool, a mailbox client, social platform software, etc., may be installed on the

terminal device

101, 102, 103, or 104.

The

terminal device

101, 102, 103, or 104 may be various electronic devices having a touch display screen and/or supporting web browsing, including, but not limited to, a smart phone, a tablet computer, an e-book reader, an MP3 player (moving picture experts group compression standard audio layer 3), an MP4 (moving picture experts group compression standard audio layer 4) player, a head-mounted display device, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PMP (portable multimedia player), a vehicle-mounted terminal (e.g., a car navigation terminal), and the like, and a mobile terminal such as a digital TV, a desktop computer, and the like.

The server 106 may be a server that provides various services, such as a background server that provides support for pages displayed on the

terminal devices

101, 102, 103, or 104.

It should be understood that the number of terminal devices, networks, and servers in fig. 1 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Here, the terminal device may implement the method of the embodiment of the present invention independently or by running an application in an android system in cooperation with other electronic terminal devices, or may run an application in other operating systems, such as an iOS system, a Windows system, a hongmeng system, or the like, to implement the method of the embodiment of the present invention.

[ paging method for memory pages ]

In the prior art, an operating system of an electronic device accesses a memory when executing a process. The process finds the highest level page table directory table that needs to access the memory by the base address (i.e., physical address) of the highest level page table directory table (PDT) of the accessed memory pre-stored in a register (e.g., CR3 register). In the hierarchical page table structure, a page table directory table includes a plurality of page table directory entries (PDEs), each page table directory entry stores a base address of a next-level page table, and a last-level page table is a page table, i.e., a page table, stores a base address of a page using a Page Table Entry (PTE). FIG. 2 shows a hierarchical page table structure implementing 2MB pages in a Memory Management Unit (MMU). Each level of the table has 512 entries (entries) that are addressed using 9-bit address bits. To be able to support different page sizes, the number of page addressing levels may be varied, for example, as shown in FIG. 3, where 1GB of paging may be implemented, for example, using 2 levels of addressing as in the prior art. The table structure using 512 entries determines that this page table structure can only realize paging of 4kb, 2MB, 1GB, 512GB, 1 TB.

If it is desired to implement other sized pages, such as 4MB pages, as shown in FIG. 4, some changes to the page table structure described above are required in the IO memory management Unit (IOMMU) in the prior art. For example, an identification bit 7 is added to a PTE entry to indicate that the PTE points to a 4MB page, and to ensure that the PTE is still addressed using a 9-bit address, the 4MB page base address occupies two PTEs. This page table structure, while extending the supportable page size, does not reduce the page table entries. In addition, the mechanism for realizing 4MB paging can be extended to realize 8MB paging, 16MB paging and the like, only the identification bit of the PTE needs to be changed, but the identification bit cannot be increased infinitely, the size of the supported paging is still limited by the defined identification bit, and moreover, a plurality of entries of 2MB page tables need to be occupied, which is not favorable for reducing the storage space of the page table. Therefore, the conventional page table structure has the following disadvantages: the supported page size is relatively fixed, and only one page size can be used in one page table structure. Even if the supported page becomes large, the table entries of the page table are not reduced, which is not beneficial to reducing the memory space of the page table.

As described above, a page is the minimum granularity for defining a continuous segment of address space when page table partitioning is performed, and memory usage efficiency is low in the case where the size of a page is defined to be too small and the execution of the process requires the use of memory in a large unit, and in the case where the size of a page is defined to be too large and the execution of the process requires the use of memory only in a small unit. Therefore, the program access method, such as whether there is a large contiguous space in the memory, and how large the unit of memory used by the program, may result in different efficiencies of the same page table structure (same size of pages) in the operating system. On the other hand, it can also be said that the memory usage status and the program access method determine which size of page is most suitable.

In view of the foregoing, the present invention provides a method for paging memory pages. FIG. 5 is a schematic flow chart illustrating a method for paging memory pages according to the present invention. As shown in fig. 5, the following steps are included.

Step 501, performing lookup according to a base address of a current stage page table directory table in a memory page table structure and an addressing address corresponding to the current stage page table directory table in a linear address to obtain a current stage page table directory entry, and obtaining type information for describing a type of a next stage table from the current stage page table directory entry, where the type includes the page table directory table and a page table.

Step 502, repeating the steps until the type information indicates that the next-level table is a page table;

step 503, performing a lookup according to the base address of the page table and an addressing address corresponding to the page table in the linear address to obtain a page table entry in the page table, and obtaining a page base address from the page table entry;

step 504, determining a page address according to the page base address and the physical page offset.

Specifically, it is assumed that the memory page table structure includes n-level tables, n is a positive integer greater than 1, the n-level tables include at least one page table directory table, the page table is located at the mth level, m < n, and m is a positive integer greater than 1. For the page table directory table of the nth level, obtaining the base address from the CR3 register; for the page table directory tables from the (n-1) th level to the (m + 1) th level, obtaining a base address from the directory entries of the previous page table; for the m-th level page table, the base address is derived from the m + 1-th level page table directory entry. Starting from the nth-stage table, reading the page table directory table from the base address, searching the page table directory entry in the page table directory table, and obtaining the information describing the type of the next-stage table and the base address of the next-stage table from the searched page table directory entry. The page table directory entry uses identification bits to describe the type of the next-level table, for example, a 1 in the page table directory entry indicates that the next-level table is a page table directory table, and a 0 in the page table directory entry indicates that the next-level table is a page table. Next, in the case that the identification bit is 1, reading the page table directory table from the base address of the next-level table, and looking up the page table directory entry in the page table directory table, obtaining the information describing the type of the next-level table from the found page table directory entry, and … … the base address of the next-level table, repeating the steps until the identification bit is 0, at this time, the current-level table is the page table directory table of the (m + 1) th level, the page table directory entry is looked up in the page table directory table of the (m + 1) th level, and the base address of the next-level table is obtained from the found page table directory entry. Next, the page table is read from the page table base address, and the page table entry is looked up in the page table, and the page base address is obtained from the looked-up page table entry.

The physical page offset can be calculated from the equation of the physical page offset, memory address width- (n-m) page table directory entry address width-page table entry address width.

In addition, the address width is a fixed value for the page table directory tables of the nth to m +1 th stages.

According to the above-described paging method for memory pages, since the value of the identification bit pointed to the next table in the page table directory entry of the page table directory table is variable, the number of stages of the page table structure is not fixed, and the physical page offset is not fixed. Therefore, by changing the assignment of the identification bit, the level number of the page table structure can be changed, and the physical page offset is further changed, so that the size of the paging is changed.

In addition, the addressing width of the page table in the memory page table structure is a non-fixed value, an index register (index register) may be provided for each page table to identify the addressing width of the page table entry in the page table, and the addressing width indicated by the index value in the index register is used when the page table entry is looked up in the m-th page table. For example, one page table directory table of the m +1 th level points to a plurality of page tables of the m-th level, and the addressing width may be the same or different among the plurality of page tables of the m-th level. Thus, by changing the addressing width of the page table, the physical page offset, and hence the size of the page, can be changed.

Therefore, in the invention, the size of the paging can be changed by changing the number of stages of the page table structure and the addressing width of the page table, and when the memory page is paged, the paging with different sizes can be found according to the difference of the number of stages of the page table structure and the addressing width of the page table.

Corresponding to the above method, a page table structure when paging is performed using this method is described with reference to fig. 6.

In the page table structure, each PDE table entry carries an identification bit to indicate whether the next level points to PDE or PTE, which may be represented by 1 to indicate that the next level is PDE and 0 to indicate that the next level is PTE. Because the identification bits carried by the PDE table entries are different, the number of page table lookup stages is not fixed. The flag bit is not limited to 1 and 0, and may be set in the opposite direction or may be other flag types as long as the next direction is indicated.

All PDEs use the same addressing width, e.g., 9-bit (bit) addressing PDEs, then each set of PDEs is 512 entries.

In the present invention, the PTEs can use different addressing widths, and the memory manager sets an index register for each set of PTEs pointed to by the PDE to identify the addressing width used to address that PTE. Fig. 6 shows that the addressing widths used by the 3 PTEs are respectively set to 8-bit index, 9-bit index, and 8-bit index. Because the addressing width represented by index is different, the number of entries of each group of PTE is different.

The PTE points to the base address of the page, and the page offset addressing width is given by the memory address width minus the sum of all PDE and PTE addressing widths.

According to the hierarchical page table structure, the paging method of the memory page of the present invention can satisfy the requirement of searching memory pages with different sizes by changing the number of page table searching steps and the addressing width used by the PTE.

The paging method of memory pages according to the present invention will be described in detail with reference to the following embodiments.

Example 1

In embodiment 1, how to implement the query of 4MB paging is explained based on fig. 6.

Using a 3-level page table lookup structure, two levels of PDEs plus one level of PTE, the base address of the 4 th level page table directory table is obtained from a register. Stage 4 is PDE, using 9-bit addressing, address bit [ 47: 39] is used as index for searching PDE to obtain a PDE list item. The base address of the level 3 table is read from the entry, along with the attributes of the level 3 table. Here 1 denotes that the level 3 table is a page table directory table.

Reading the 3 rd level table from the base address of the 3 rd level table obtained above, 9 bits of addressing are still used since the 3 rd level table is a page table directory table. Using the address bit [ 38: 30] searching the PDE of the 3 rd level to obtain a PDE list item. The base address of the level 2 table and the attributes of the level 2 table are read from the entry. Where 0 indicates that the level 2 table is a page table.

The level 2 PTE is read at the base address of the level 2 table obtained above, and an index, which indicates that the PTE uses a few bits for addressing, is read from an index register. Where index is 8 bits, meaning that the PTE uses 8-bit addressing. So using address bit [ 29: 22] address the PTE, resulting in the base address of the page.

The previous 3-level (4 th, 3 rd, 2 nd) page table lookup uses a 26-bit address in common, leaving a 22-bit address in the 48-bit address space as the page offset, so the page size is 2^22 ^ 4 MB. From the above obtained page base address plus address bit [ 21: an offset of 0] results in the page address.

Example 2

In embodiment 2, how to implement the query of 2MB paging is explained based on fig. 6.

Using a 3-level page table lookup structure, two levels of PDEs plus one level of PTE, the base address of the 4 th level page table directory table is obtained from a register. Stage 4 is PDE, using 9-bit addressing, address bit [ 47: 39] is used as index for searching PDE to obtain a PDE list item. The base address of the level 3 table and the attributes of the level 3 table are read from the entry. Here 1 denotes that the level 3 table is a page table directory table.

The level 3 table is read from the base address of the level 3 table obtained above, and since level 3 is PDE, 9-bit addressing is still used. Using the address bit [ 38: 30] searching the PDE of the 3 rd level to obtain a PDE list item. The base address of the level 2 table and the attributes of the level 2 table are read from the entry. Where 0 indicates that the level 2 table is a page table.

The level 2 PTE is read from the base address of the level 2 table obtained above, and an index, which indicates that the PTE uses a few bits for addressing, is read from an index register. Here index is 9, indicating that the PTE uses 9-bit addressing. So using address bit [ 29: 21] address the PTE, resulting in the base address of the page.

The 27-bit address is used in the previous 3-level page table lookup, leaving 21-bit addresses in the 48-bit address space as page offsets, so the page size is 2^21 ^2 MB. From the above-obtained page base address plus address bit [ 20: an offset of 0] results in the page address.

Example 3

In embodiment 3, how to implement the query of 8KB paging is explained based on fig. 6.

Using a 4-level page table lookup structure, a three-level PDE adds a level PTE to obtain the base address of the 4 th level page table directory table from a register.

Stage 4 is PDE, using 9-bit addressing, address bit [ 47: 39] is used as index for searching PDE to obtain a PDE list item. The base address of the level 3 table and the attributes of the level 3 table are read from the entry. Here 1 denotes that the level 3 table is a page table directory table.

The level 3 table is read from the base address of the level 3 table obtained above, and since level 3 is PDE, 9-bit addressing is still used. Using the address bit [ 38: 30] searching the PDE of the 3 rd level to obtain a PDE list item. The base address of the level 2 table is read from the entry, along with the attributes of the level 2 table. Where 1 denotes that the level 2 table is a page table directory table.

The stage 2 PDE is read from the base address of the stage 2 table obtained above, using 9-bit addressing, so using the address bit [ 29: 21] addressing the PDE to obtain a PDE table entry. The base address of the level 1 table and the attributes of the level 1 table are read from the entry. Where 0 indicates that the level 1 table is a page table.

The level 1 PTE is read from the base address of the level 1 table obtained above, and an index, which indicates that the PTE uses a few bits for addressing, is read from an index register. Where index is 8, indicating that the PTE uses 8-bit addressing. So using the address bit [ 20: address PTE, get the base address of the page.

The 35-bit address used in the previous 4-level page table lookup leaves 13-bit addresses in the 48-bit address space as page offsets, so the page size bits 2^13 ^ 8 KB. From the above obtained page base address plus address bit [ 12: an offset of 0] results in the page address.

Embodiments 1 to 3 described above illustrate how to implement the 4MB, 2MB, and 8KB paging query in the present invention, and the implementation manners of the above three paging queries can be extended to the implementation of other paging sizes, and only the attribute of the PDE pointing to the next level table and the number of address bits required for searching the PTE need to be modified, so that the query of memory pages with different sizes can be flexibly implemented.

Furthermore, because the number of entries of the PTE is redefinable, the use of fixed entries is no longer required. For example, the PTE with attribute index of 8 has only 256 entries, which reduces the space for storing the PTE.

In the above description, the case where the memory address width is 48 bits and the address width used in the page table directory table is 9 bits has been described as an example, but the present invention is not limited to this, and the memory address width and the address width used in the page table directory table may be different from those described above depending on the operating system, the setting of the user, the support of device hardware, and the like, and the memory address width determined by hardware may be 32 bits, 48 bits, 64 bits, or the like, for example. The foregoing description of the 48-bit storage address width is used for the convenience of understanding the embodiments, and should not be construed in a limiting way, and even in the same memory, the storage address width actually used may be different under different usage environments.

In the above description, the case where the operating system of the electronic terminal manages the hierarchical page table structure by the memory management unit has been described as an example, but the present invention is not limited to this, and the page dividing method of the memory page of the present invention can be applied as long as the address division of the memory is realized by using the page table structure, regardless of the presence or absence of the operating system, the type of the operating system, and the type of the processor.

In the above description, the case where each PDE entry carries a flag bit to determine whether the next stage is a PDE or a PTE has been described as an example, but the present invention is not limited to this, and the flag bit may not be used. For example, as a method for distinguishing the PDE and the PTE, it can be distinguished by an address, and a page table directory table and a page table may have different address segments, respectively. In addition, the entries (entries) may be differentiated from each other, and different numbers of entries may be used for the PDE and the PTE, for example, the PDE is fixed to 512 entries, while the number of entries used by the PTE cannot be 512 entries, and here, 512 entries are merely examples and are not limiting. In addition, the entries may be distinguished by their format, and the formats of the entries that the PDE and the PTE store may be distinguished using different header flags, such as 0 and 1, or different sizes for each entry, etc.

The paging method of the memory page according to the present invention is described above based on the embodiments. In addition, the invention also provides a paging device of the memory pages. The apparatus is described below.

The paging device of memory pages of the present invention comprises:

The traversal module and the address determination module may be one of hardware, software, or a combination of hardware and software, and for specific actions and functions thereof, reference may be made to each step of the paging method for memory pages, and detailed descriptions thereof are omitted here.

Further, the present invention also provides a computer apparatus (electronic apparatus) which is explained below.

Referring now to fig. 7, a schematic diagram of an electronic device (e.g., the terminal device or server of fig. 1) 700 suitable for implementing embodiments of the present invention is shown. The terminal device in the embodiment of the present invention may be various terminal devices in the above system. The electronic device shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present invention.

As shown in fig. 7, the electronic device 700 may include a processing means (e.g., central processing unit, graphics processor, etc.) 701 for controlling the overall operation of the electronic device. The processing device may include one or more processors to execute instructions to perform all or a portion of the steps of the method described above. Further, the processing device 701 may also include one or more modules for processing interactions with other devices.

The storage device 702 is used to store various types of data, and the storage device 702 can be a system, apparatus or device that includes various types of computer-readable storage media or a combination thereof, such as electronic, magnetic, optical, electromagnetic, infrared, or semiconductor, or a combination of any of the above. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The sensor means 703, which senses the information specified to be measured and converts it into a usable output signal according to a certain rule, may comprise one or more sensors. For example, it may include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor or a temperature sensor, etc. for detecting changes in the on/off state, relative positioning, acceleration/deceleration, temperature, humidity, light, etc. of the electronic device.

The processing device 701, the storage device 702, and the sensor device 703 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

The multimedia device 706 may include an input device such as a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, etc. for receiving an input signal from a user, and various input devices may cooperate with various sensors of the sensor device 703 to perform, for example, a gesture operation input, an image recognition input, a distance detection input, etc.; the multimedia device 706 may also include output devices such as a Liquid Crystal Display (LCD), speakers, vibrators, and the like.

The power supply device 707, which is used to provide power to various devices in the electronic equipment, may include a power management system, one or more power supplies, and components to distribute power to other devices.

The communication device 708 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data.

Each of the above devices may also be connected to the I/O interface 705 to implement applications of the electronic device 700.

While fig. 7 illustrates an electronic device 700 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.

In particular, according to an embodiment of the present invention, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, an embodiment of the invention includes a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means, or may be installed from a storage means. The computer program, when executed by a processing device, performs the functions defined in the method of an embodiment of the invention.

In the context of the present invention, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

It is noted that the computer-readable media described above in connection with the present invention may be computer-readable signal media or computer-readable storage media, or any combination of the two. In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.

The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network or connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units described in the embodiments of the present invention may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.

In addition, the invention also provides a computer readable storage medium. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the paging method for memory pages described above.

According to one or more embodiments of the present invention, a method for paging a memory page is provided, where the method includes:

According to one or more embodiments of the present invention, there is provided a method for paging memory pages,

the memory page table structure includes n-level tables, n being a positive integer greater than 1,

the n-level table includes at least one level page table directory table,

the page table is located at the mth level, m is less than n, and m is a positive integer more than 1.

for the page table directory table of the nth level, obtaining a base address from a register;

for the page table directory tables from the (n-1) th level to the (m + 1) th level, obtaining a base address from the directory entries of the previous page table;

for the m-th level page table, the base address is derived from the m + 1-th level page table directory entry.

the page table directory entry uses identification bits to describe type information of the type of the next level table.

the addressing width of each level of page table directory table is a fixed value.

physical page offset-memory address width- (n-m) page table directory entry addressing width-page table entry addressing width.

the addressing width of the page table in the memory page table structure is a non-fixed value.

an index register is provided for each page table to identify the addressing width of the page table entry in the page table.

the memory address is 48 bits wide, and when paging a 4MB page,

reading a fourth-stage page table directory table according to a base address of the fourth-stage page table directory table obtained from the register, and searching by using a 9-bit addressing address corresponding to the fourth-stage page table directory table in the linear address to obtain a fourth-stage page table directory entry;

obtaining a base address of a third-level page table directory table and identification bit information describing the type of the third-level table from a fourth-level page table directory entry, reading the third-level page table directory table from the base address of the third-level page table directory table, and searching by using a 9-bit addressing address corresponding to the third-level page table directory table in linear addresses to obtain a third-level page table directory entry;

obtaining a base address of a second-stage page table and identification bit information describing the type of the second-stage table from a directory entry of a third-stage page table, reading the second-stage page table from the base address of the second-stage page table, and searching by using an 8-bit addressing address corresponding to the second-stage page table in a linear address to obtain a second-stage page table entry;

obtaining a page base address from a second level page table entry;

physical page offset-48 bit-2 x 9-8-22 bit address;

the 4MB page address is the page base address + physical page offset.

the memory address is 48 bits wide, and when paging a 2MB page,

obtaining a base address of a second-stage page table and identification bit information describing the type of the second-stage table from a directory entry of a third-stage page table, reading the second-stage page table from the base address of the second-stage page table, and searching by using an addressing address of 9 bits corresponding to the second-stage page table in linear addresses to obtain a second-stage page table entry;

obtaining a page base address from a second level page table entry;

physical page offset-48 bit-2 x 9-21 bit address;

the 2MB page address is the page base address + physical page offset.

the memory address is 48 bits wide, and when paging 8KB pages,

obtaining a base address of a second-level page table directory table and identification bit information describing the type of the second-level table from a third-level page table directory entry, reading the second-level page table directory table from the base address of the second-level page table directory table, and searching by using a 9-bit addressing address corresponding to the second-level page table directory table in a linear address to obtain a second-level page table directory entry;

obtaining a base address of a first-stage page table and identification bit information describing the type of the first-stage table from a directory entry of a second-stage page table, reading the first-stage page table from the base address of the first-stage page table, and searching by using an addressing address of 8 bits corresponding to the first-stage page table in a linear address to obtain a first-stage page table entry;

obtaining a page base address from a first level page table entry;

physical page offset-48 bit-3 x 9-8-13 bit address;

the 8KB page address is page base address + physical page offset.

According to one or more embodiments of the present invention, there is provided a paging apparatus for memory pages, the apparatus comprising:

According to one or more embodiments of the present invention, there is provided a paging apparatus for memory pages, wherein,

the n-level table includes at least one level page table directory table,

According to one or more embodiments of the present invention, there is provided a CPU chip, characterized by comprising a plurality of DIE, each DIE comprising at least one processor core;

the processor core performs the paging method for memory pages described above.

According to one or more embodiments of the present invention, there is provided a computer characterized by including the CPU described above.

The foregoing description is only exemplary of the preferred embodiments of the invention and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other embodiments in which any combination of the features described above or their equivalents is encompassed without departing from the spirit of the disclosure. For example, the above features and (but not limited to) features having similar functions disclosed in the present invention are mutually replaced to form the technical solution.

Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the invention. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method for paging memory pages, the method comprising the steps of:

2. The method of claim 1,

the n-level table includes at least one level page table directory table,

3. The method of claim 2,

4. The method of claim 3,

5. The method of claim 4,

6. The method of claim 5,

7. The method of claim 6,

8. The method of claim 7,

9. The method of claim 8,

the memory address is 48 bits wide, and when paging a 4MB page,

obtaining a page base address from a second level page table entry;

physical page offset-48 bit-2 x 9-8-22 bit address;

the 4MB page address is the page base address + physical page offset.

10. The method of claim 8,

the memory address is 48 bits wide, and when paging a 2MB page,

obtaining a page base address from a second level page table entry;

physical page offset-48 bit-2 x 9-21 bit address;

the 2MB page address is the page base address + physical page offset.

11. The method of claim 8,

the memory address is 48 bits wide, and when paging 8KB pages,

obtaining a page base address from a first level page table entry;

physical page offset-48 bit-3 x 9-8-13 bit address;

the 8KB page address is page base address + physical page offset.

12. An apparatus for paging memory pages, the apparatus comprising:

13. The apparatus of claim 12,

the n-level table includes at least one level page table directory table,

14. The apparatus of claim 13,

15. The apparatus of claim 14,

16. The apparatus of claim 15,

17. The apparatus of claim 16,

18. The apparatus of claim 17,

19. A CPU chip is characterized by comprising a plurality of crystal grains DIE, wherein each crystal grain DIE comprises at least one processor core;

the processor core performs the method for paging memory pages as claimed in any one of claims 1 to 11.

20. A computer comprising the CPU of claim 19.