CN117971648A - Real-time observation method and system for high-speed signals in chip - Google Patents

Abstract

The invention provides a real-time observation method and a system for high-speed signals in a chip, wherein the method comprises the following steps: determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal; transmitting the high-speed multi-bit signal to a digital-to-analog conversion module included in the chip, wherein the digital-to-analog conversion module converts the high-speed multi-bit signal into an analog signal; and sending the converted analog signals to the outside of the chip for observation. The beneficial effects are that: according to the invention, the high-speed multi-bit signal to be observed is transmitted to the digital-to-analog conversion module included in the chip, converted into the analog signal and then transmitted to the outside of the chip for observation, so that the observation problem of the high-speed change signal in the prior art is solved, and the testability of the high-speed signal in the chip is enhanced; meanwhile, the digital-to-analog conversion module inside the multiplexing chip realizes real-time observation and recording of the high-speed change signal under the condition of not occupying extra resources so as to better analyze and debug the performance of the chip.

Description

Real-time observation method and system for high-speed signals in chip

Technical Field

The invention relates to the technical field of signal processing, in particular to a real-time observation method and system for high-speed signals in a chip.

Background

In digital receiver chips, such as communication chips, circuits such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are typically included. These circuits play an important role in the testing and debugging process of the chip. During testing and debugging, observation of critical signals inside the chip is critical.

For a slowly varying critical control signal, it is generally possible to observe by feeding it to a general purpose input output pin (GPIO). GPIO is a general-purpose digital input/output interface that can be used to connect to external devices or sensors and communicate with the external devices by reading or writing the level state of pins.

However, there may be some limitations to the observation by GPIO of signals that vary at high speed, particularly multi-bit signals that vary at high speed. This is because GPIOs are limited in speed and bandwidth and cannot meet the requirements of high-speed signals. In addition, since GPIOs are shared resources, there may be collisions with other functions or modules, affecting the accuracy of the observation.

It is common today to use memory (memory) inside the chip to store and read the high speed varying signals for observation. By storing the signals in a memory inside the chip, real-time recording and reading of the signals can be achieved, thereby better analyzing and debugging the performance of the chip.

However, there are also some problems with using an on-chip memory to store signals: first, this approach requires additional resources, including memory cells and associated control circuitry; second, since memory is limited, all test and debug requirements may not be met; in addition, since the memory has a limited read/write speed, the real-time performance of the observation signal may be affected.

Disclosure of Invention

In order to solve the technical problems, the invention provides a real-time observation method and a system for high-speed signals in a chip.

The technical problems solved by the invention can be realized by adopting the following technical scheme:

a real-time observation method for high-speed signals in a chip comprises the following steps:

determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

Transmitting the high-speed multi-bit signal to a digital-to-analog conversion module included in a chip, wherein the digital-to-analog conversion module converts the high-speed multi-bit signal into an analog signal;

And sending the converted analog signals to the outside of the chip for observation.

Preferably, the digital-to-analog conversion module for transmitting the high-speed multi-bit signal to the chip further includes:

judging whether the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module;

And transmitting the high-speed multi-bit signal to the digital-to-analog conversion module when the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module.

Preferably, the method further comprises:

when the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module, preprocessing the high-speed multi-bit signal, and transmitting the preprocessed high-speed multi-bit signal to the digital-to-analog conversion module.

Preferably, the preprocessing includes at least one of signal compression, signal truncation, and signal bit segmentation.

Preferably, the digital-to-analog conversion module for transmitting the high-speed multi-bit signal to the chip further includes:

and when the clock domain of the high-speed multi-bit signal is different from the first clock domain of the digital-to-analog conversion module, performing cross-clock domain processing on the high-speed multi-bit signal, and converting the high-speed multi-bit signal into the first clock domain of the digital-to-analog conversion module.

Preferably, the digital-to-analog conversion module converts the high-speed multi-bit signal into an analog signal includes:

and comparing the high-speed multi-bit signal with each bit value of the high-speed multi-bit signal according to a plurality of reference signals preset in the digital-to-analog conversion module, and converting the high-speed multi-bit signal into analog signals with different levels.

The invention also provides a real-time observation system of the high-speed signal in the chip, which is used for implementing the real-time observation method of the high-speed signal in the chip, and comprises the following steps:

The signal determining module is used for determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

The signal transmission module is connected with the signal determination module and used for transmitting the high-speed multi-bit signal to a digital-to-analog conversion module included in the chip, and the digital-to-analog conversion module is used for converting the high-speed multi-bit signal into an analog signal;

And the signal transmitting module is connected with the digital-to-analog conversion module and used for transmitting the converted analog signals to the outside of the chip for observation.

Preferably, the signal transmission module includes:

the bit width judging unit is used for judging whether the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module;

The first signal transmission unit is connected with the bit width judging unit and is used for transmitting the high-speed multi-bit signal to the digital-to-analog conversion module when the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module.

Preferably, the signal transmission module further comprises:

The preprocessing unit is connected with the bit width judging unit and is used for preprocessing the high-speed multi-bit signal when the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module;

And the second signal transmission unit is connected with the preprocessing unit and is used for transmitting the preprocessed high-speed multi-bit signal to the digital-to-analog conversion module.

Preferably, the signal transmission module further comprises:

And the clock domain crossing processing unit is used for performing clock domain crossing processing on the high-speed multi-bit signal and converting the high-speed multi-bit signal into the first clock domain where the digital-to-analog conversion module is located when the clock domain where the high-speed multi-bit signal is located is different from the first clock domain where the digital-to-analog conversion module is located.

The technical scheme of the invention has the advantages that:

according to the invention, the high-speed multi-bit signal to be observed is transmitted to the digital-to-analog conversion module included in the chip, converted into the analog signal and then transmitted to the outside of the chip for observation, so that the observation problem of the high-speed change signal in the prior art is solved, and the testability of the high-speed signal in the chip is enhanced; meanwhile, the digital-to-analog conversion module inside the multiplexing chip realizes real-time observation and recording of the high-speed change signal under the condition of not occupying extra resources so as to better analyze and debug the performance of the chip.

Drawings

FIG. 1 is a flow chart of a method for real-time observation of high-speed signals in a chip according to a preferred embodiment of the invention;

FIG. 2 is a flow chart of bit width determination in a preferred embodiment of the present invention;

FIG. 3 is a flow chart of the cross-clock domain processing in the preferred embodiment of the invention;

FIG. 4 is a flow chart of the digital-to-analog conversion in the preferred embodiment of the invention;

FIG. 5 is a block diagram of a real-time observation system for on-chip high-speed signals according to a preferred embodiment of the present invention;

FIG. 6 is a block diagram showing a signal transmission module according to a preferred embodiment of the present invention;

FIG. 7 is a block diagram showing a signal transmission module according to a preferred embodiment of the present invention;

FIG. 8 is a block diagram showing a signal transmission module according to a preferred embodiment of the present invention;

Fig. 9 is a schematic diagram of a photoelectric conversion chip according to a preferred embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

Referring to fig. 1, in a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, there is now provided a real-time observation method for on-chip high-speed signals, comprising:

s1, determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

S2, transmitting the high-speed multi-bit signal to a digital-to-analog conversion module 41 included in the chip 1, wherein the digital-to-analog conversion module 41 converts the high-speed multi-bit signal into an analog signal;

And S3, transmitting the converted analog signals to the outside of the chip 1 for observation.

Specifically, the key control signals include a slow-change signal and a fast-change high-speed signal, and the slow-change signal can be observed by sending the signal to a General Purpose Input Output (GPIO), so that the embodiment of the invention mainly aims at the observation of the fast-change high-speed signal, especially the high-speed multi-bit signal.

Aiming at the problems that the observation mode of using a memory (memory) inside a chip to store and read signals changing at high speed in the prior art needs extra resources and has poor observation instantaneity. It is contemplated that circuits such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are included substantially in digital receiver chips, such as communication chips. Therefore, in this embodiment, the high-speed multi-bit signal to be observed is transmitted to the digital-to-analog conversion module 41 included in the chip, converted into an analog signal, and then sent to the outside of the chip for observation, so that the observation problem of the high-speed variation signal in the prior art is solved, and the testability of the high-speed signal in the chip is enhanced; meanwhile, the digital-to-analog conversion module 41 inside the chip to be observed is multiplexed, and real-time observation and recording of the high-speed change signal are realized under the condition that extra resources are not occupied, so that the performance of the chip can be better analyzed and debugged.

Further, the digital-to-analog conversion module 41 is a device or module for converting a digital signal into an analog signal, and may be implemented by using an existing digital-to-analog converter. Specifically, the corresponding digital-to-analog converter can be selected according to the requirements of the application scene. By way of example and not limitation, it is preferable to use a high-speed digital-to-analog conversion module 41, for example, to complete conversion of a large number of digital signals to analog signals in a short time, further shorten the digital-to-analog conversion time, and meet the real-time requirements for high-speed signal observation. For example, the multichannel digital-to-analog conversion module 41 is preferably used, so that a plurality of digital signals can be processed simultaneously and converted into analog signals, the parallel processing capability of the system is improved, and resources are saved.

Further, the digital-analog conversion device can also comprise external observation equipment, after digital-analog conversion is completed, the converted analog signals are sent to the observation equipment outside the chip 1, and high-speed multi-bit signal observation is realized through the observation equipment. In some embodiments, the observation device may employ an observation device such as an oscilloscope. An oscilloscope is a commonly used electronic measuring instrument, and can be used for observing and analyzing characteristics of electric signals such as waveforms, amplitudes, frequencies and the like. The oscilloscope has high sampling rate and larger bandwidth, and can meet the requirement of high-speed multi-bit signal observation.

In some embodiments, when selecting the observation device, the selection may be made according to actual needs. Different observation devices may have different characteristics and functions, and may be selected according to characteristics of signals, observation requirements, budget, and other factors. In addition to oscilloscopes, other types of observation devices, such as logic analyzers, spectrum analyzers, etc., may be considered to meet different observation requirements.

As a preferred embodiment, as shown in fig. 2, the digital-to-analog conversion module 41 for transmitting the high-speed multi-bit signal to the chip 1 further includes:

S200, judging whether the bit width of the high-speed multi-bit signal is within the bit width supporting range of the digital-to-analog conversion module 41:

If yes, go to step S202;

if not, go to step S201;

S201, preprocessing a high-speed multi-bit signal;

S202, the high-speed multi-bit signal is transmitted to the digital-to-analog conversion module 41.

Specifically, if the bit width of the high-speed multi-bit signal is within the bit width supporting range of the digital-to-analog conversion module 41, which means that the digital-to-analog conversion module 41 can directly process the high-speed multi-bit signal without performing additional preprocessing, the high-speed multi-bit signal is directly transmitted to the digital-to-analog conversion module 41.

If the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module 41, the high-speed multi-bit signal needs to be preprocessed, and then the preprocessed high-speed multi-bit signal is transmitted to the digital-to-analog conversion module 41 for processing. Further, by preprocessing, the signal exceeding the bit width supporting range can be adjusted to the range supported by the digital-to-analog conversion module 41, so as to ensure that the digital-to-analog conversion module 41 can work normally

As a preferred embodiment, the preprocessing includes at least one of signal compression, signal truncation, and signal bit segmentation.

In some embodiments, the high-speed multi-bit signal is compressed when the bit width of the high-speed multi-bit signal exceeds the bit width support range of the digital-to-analog conversion module 41. By removing the non-observable portions of the signal, the bit width of the signal can be reduced to accommodate the support range of the digital to analog conversion module 41. The compressed signals can reduce the data volume and the transmission bandwidth requirements on the premise of ensuring the accuracy of the observation result. The signal compression may be implemented using known techniques such as huffman coding or entropy coding.

In some embodiments, the signal is truncated when the bit width of the high-speed multi-bit signal exceeds the bit width support range of the digital-to-analog conversion module 41. By reducing some of the observation granularity, i.e. reducing the number of bits of the signal, it is possible to adapt it to the bit-wide support range of the digital-to-analogue conversion module 41. This method can be implemented by simply intercepting the high or low order bits of the signal. Further, for the part with observing significance in the selectable truncated signal, information loss or inaccuracy of an observed result caused by incorrect truncated position is avoided.

In some embodiments, a dac+gpio combined scheme may also be employed to observe high-speed multi-bit signals. Specifically, the high 1/2 bits in the high-speed multi-bit signal to be observed can be observed through GPIO, while the low bits can be observed through DAC conversion into analog signals. This method can be implemented by dividing the signal into two parts, high and low, thereby reducing the bit width requirements of the digital-to-analog conversion block 41.

As a preferred embodiment, as shown in fig. 3, the digital-to-analog conversion module 41 for transmitting the high-speed multi-bit signal to the chip 1 further includes:

S203, when the clock domain of the high-speed multi-bit signal is different from the first clock domain of the digital-to-analog conversion module 41, the high-speed multi-bit signal is processed across the clock domain and converted to the first clock domain of the digital-to-analog conversion module 41.

Specifically, considering that the clock of the high-speed multi-bit signal to be observed may not be the first clock domain DAC clock where the digital-to-analog conversion module 41 is located, it is necessary to perform cross-clock domain processing on the high-speed multi-bit signal and convert the high-speed multi-bit signal to the clock domain of the digital-to-analog conversion module 41, so as to ensure that the signal can be sent out by the DAC at a correct timing, thereby ensuring correct transmission and processing of the signal between different clock domains, and further improving stability and reliability of the system.

In the description of the present invention, it should be understood that the numerical references before the steps do not identify the order in which the steps are performed, but are merely used to facilitate description of the present invention and to distinguish between each step, and thus should not be construed as limiting the present invention. For example, the above-described cross-clock domain processing of S203 is performed before the signal transmission of S202.

As a preferred embodiment, wherein the digital-to-analog conversion module 41 converts the high-speed multi-bit signal into an analog signal, as shown in fig. 4, includes:

s204, comparing the high-speed multi-bit signal with each bit value of the high-speed multi-bit signal according to a plurality of reference signals preset in the digital-to-analog conversion module 41, and converting the high-speed multi-bit signal into analog signals with different levels.

In particular, compared with the prior art that a plurality of GPIO resources are required when a high-speed multi-bit signal is observed through GPIO, and a plurality of oscilloscope probes are required. In this embodiment, the high-speed multi-bit signal is converted into an analog signal through digital-to-analog conversion processing, thereby greatly simplifying the observation process.

Further, comparing a plurality of preset reference signals with each bit value of the high-speed multi-bit signal, and converting the high-speed multi-bit signal into analog signals with different levels, so that each bit value of the high-speed multi-bit signal to be observed in the chip is converted into the level of different analog signals, and real-time observation can be realized only by one oscilloscope probe without occupying a plurality of GPIO resources or using a plurality of oscilloscope probes; meanwhile, dynamic observation can be realized, and the change trend of signals can be observed, so that the defect that the dynamic observation cannot be realized through an oscilloscope in the prior art is overcome.

Referring to fig. 6, the present invention further provides a real-time observation system for an on-chip high-speed signal, for implementing the real-time observation method for an on-chip high-speed signal, including:

the signal determining module 1 is used for determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

The signal transmission module 2 is connected with the signal determination module 1 and is used for transmitting the high-speed multi-bit signal to a digital-to-analog conversion module 41 included in the chip 1, and the digital-to-analog conversion module 41 converts the high-speed multi-bit signal into an analog signal;

the signal transmitting module 3 is connected to the digital-to-analog conversion module 41, and is configured to transmit the converted analog signal to the outside of the chip 1 for observation.

Specifically, in this embodiment, the high-speed multi-bit signal to be observed is transmitted to the digital-to-analog conversion module 41 included in the chip, and is converted into an analog signal and then sent to the outside of the chip for observation, so that the problem of observation of the high-speed change signal in the prior art is solved, and the testability of the high-speed signal in the chip is enhanced; meanwhile, the digital-to-analog conversion module 41 inside the chip to be observed is multiplexed, and real-time observation and recording of the high-speed change signal are realized under the condition that extra resources are not occupied, so that the performance of the chip can be better analyzed and debugged.

As a preferred embodiment, wherein, as shown in fig. 7, the signal transmission module 2 includes:

A bit width judging unit 21 for judging whether the bit width of the high-speed multi-bit signal is within the bit width supporting range of the digital-to-analog conversion module 41;

The first signal transmission unit 22 is connected to the bit width judging unit 21, and is configured to transmit the high-speed multi-bit signal to the digital-to-analog conversion module 41 when the bit width of the high-speed multi-bit signal is within the bit width supporting range of the digital-to-analog conversion module 41.

As a preferred embodiment, as shown in fig. 8, the signal transmission module 2 further includes:

A preprocessing unit 23 connected to the bit width judging unit 21, for preprocessing the high-speed multi-bit signal when the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module 41;

the second signal transmission unit 24 is connected to the preprocessing unit 23, and is configured to transmit the preprocessed high-speed multi-bit signal to the digital-to-analog conversion module 41.

As a preferred embodiment, wherein the signal transmission module 2 further comprises:

The clock domain crossing processing unit 25 is configured to perform clock domain crossing processing on the high-speed multi-bit signal and convert the high-speed multi-bit signal to the first clock domain where the digital-to-analog conversion module 41 is located when the clock domain where the high-speed multi-bit signal is located is different from the first clock domain where the digital-to-analog conversion module 41 is located.

Specifically, considering that the clock of the high-speed multi-bit signal to be observed may not be the first clock domain DAC clock where the digital-to-analog conversion module 41 is located, it is necessary to perform cross-clock domain processing on the high-speed multi-bit signal and convert the high-speed multi-bit signal to the clock domain of the digital-to-analog conversion module 41, so as to ensure that the signal can be sent out by the DAC at a correct timing, thereby ensuring correct transmission and processing of the signal between different clock domains, and further improving stability and reliability of the system.

With respect to more implementation details of the system, a method is already disclosed, and this embodiment will not be repeated.

The method in the embodiment of the invention can be applied to a digital receiver chip, such as a communication chip. The communication chip is a chip for receiving and processing digital signals and is widely applied to the fields of communication equipment, mobile equipment and the like. By applying the real-time observation method of the high-speed signals to the communication chip, the characteristics and the performances of the digital signals can be monitored and analyzed in real time, so that the working efficiency and the reliability of the communication chip are improved.

In some embodiments, the chip may be a photoelectric conversion chip, and the real-time observation method of the high-speed signal is applied to the photoelectric conversion chip. The photoelectric conversion chip is a chip capable of converting an optical signal into an electrical signal, and is widely applied to the fields of optical communication, optical sensing and the like.

In the photoelectric conversion chip, real-time observation of a high-speed signal is very important. Through real-time observation, the characteristics and performances of the electric signals received by the physical layer or other high-speed signals in the physical layer can be monitored and analyzed, so that the design and performances of the chip are optimized, and the photoelectric conversion chip has important significance for improving the working efficiency and reliability of the photoelectric conversion chip.

It should be noted that the real-time observation method of the high-speed signal in the chip is not limited to the photoelectric conversion chip, and can be applied to other types of chips. The real-time observation method of the high-speed signals can provide important references and guidance for the design and performance optimization of the chip no matter what type of the chip.

The embodiment of the invention takes the application of the real-time observation method of the high-speed signals in the chip in the photoelectric conversion chip as an example. Fig. 9 shows a general structure diagram of a photoelectric conversion chip. Fig. 9 includes some common module components in the photoelectric conversion chip, and each module is described as follows:

VGA (Variable GAIN AMPLIFIER): a variable gain amplifier for adjusting a gain of an input optical signal;

ADC (Analog-to-Digital Converter): an analog-to-digital converter that converts the analog optical signal to a digital signal;

PI (Photodiode Interface): a photodiode interface for receiving and processing the light and the electrical signal;

PLL (Phase-Locked Loop): a phase locked loop for generating a stable clock signal;

DAC (Digital-to-Analog Converter): a digital-to-analog converter converting the digital signal into an analog signal;

Rx-DSP (RECEIVER DIGITAL SIGNAL Processor): a receiving end digital signal processor for processing the received digital signal;

Tx-DSP (TRANSMITTERDIGITAL SIGNAL Processor): a transmitting-end digital signal processor for processing a digital signal to be transmitted;

Rx-Protocol (ReceiverProtocol): the receiving end protocol processor is used for analyzing the received data packet;

Tx-Protocol (TransmitterProtocol): a transmitting end protocol processor for encapsulating the data packet to be transmitted;

control FSM (FINITE STATE MACHINE): the control finite state machine is used for controlling each functional module of the chip;

FIFO, FIFOs (First-In, first-Out): a first-in first-out buffer area for temporarily storing data;

SerDes Tx-PCS (Serializer/Deserializer TransmitterPhysical Coding Sublayer): the physical coding sublayer of the transmitting end of the serializer/deserializer is used for serializing and physically coding data;

SerDes Rx-PCS (seralizer/deseriaizer RECEIVER PHYSICAL Coding Sublayer): the physical coding sublayer of the serializer/deserializer receiving end is used for analyzing the received serial data and physical codes;

SerDes Tx-PMA (seriizer/Deseriizer TRANSMITTER PHYSICAL Medium Attachment): a serializer/deserializer transmitting end physical medium additional layer for transmitting data to the physical medium;

SerDes Rx-PMA (serialiser/Deserializer ReceiverPhysical Medium Attachment): an additional layer of physical medium at the serializer/deserializer receiving end for receiving data from the physical medium;

SERDES CDR (seriizer/Deserializer Clock and Data Recovery): serializer/deserializer clock and data recovery to recover clock and data from received serial data;

SERDES PLL (serialiszer/DeserializerPhase-Locked Loop): the serializer/deserializer phase-locked loop is used for generating a stable clock signal.

In some embodiments, the in-chip DAC typically supports high-speed multi-bit. By way of example and not limitation, a typical DAC, such as 1-3 GHz sampling, is 6-11 bit wide. And the frequency of the digital signal in the chip is generally less than 1GHz, if the bit width is within the bit width supported by the DAC, the digital signal can be transmitted to the DAC after being processed by the FIFO to be transmitted to the off-chip observation equipment after being subjected to digital-to-analog conversion, and the real-time observation of the high-speed multi-bit signal is realized. The above-mentioned cross-clock domain processing steps can be implemented through the FIFO, and the above-mentioned method is disclosed in more detail about the cross-clock domain processing, and will not be described herein.

In some embodiments, for the photoelectric conversion signal, when the optical port SerDes works, the receiving channel clock needs to be locked on the opposite sending clock, and PI is needed to control the output clock phase of the PLL, and the control code word of PI is one of key control signals of the photoelectric conversion chip. In the first application of the embodiment of the invention, the PI control code word is sent to the off-chip communication through the DAC of the electric port, so that the clock locking process of the optical port SerDes is observed in real time, the output clock phase of the PLL is monitored and adjusted, and the synchronization of the receiving channel clock and the opposite end sending clock is ensured when the optical port SerDes works.

In some embodiments, in an ethernet multi-port physical layer (PHY) application, the receive clock of a single port needs to be synchronized to the transmit clock of the opposite end, and the receive path also includes PI circuitry to control the PLL output clock; the control codeword of PI is also a critical high-speed multi-bit signal. When a single port is operated, DACs of the same port are typically operated simultaneously, and thus cannot be used to observe internal signals. In the second application of the embodiment of the present invention, for multi-port application, key signals of the port to be tested, such as a key state machine and PI code, may be sent out through DACs of other ports, so as to realize observation.

In some embodiments, in a third application of the embodiment of the present invention, for a system that operates independently of the DAC, such as the SerDes part of the photoelectric conversion chip, where there are some status signals of critical protocols, also signals of high-speed multi-bit variation, and likewise, can be observed by sending out through the DAC of the electrical port

The technical scheme has the advantages that: according to the invention, the high-speed multi-bit signal to be observed is transmitted to the digital-to-analog conversion module included in the chip, converted into the analog signal and then transmitted to the outside of the chip for observation, so that the observation problem of the high-speed change signal in the prior art is solved, and the testability of the high-speed signal in the chip is enhanced; meanwhile, the digital-to-analog conversion module inside the multiplexing chip realizes real-time observation and recording of the high-speed change signal under the condition of not occupying extra resources so as to better analyze and debug the performance of the chip.

The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.

Claims (10)

1. The real-time observation method for the high-speed signal in the chip is characterized by comprising the following steps of:

determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

Transmitting the high-speed multi-bit signal to a digital-to-analog conversion module included in a chip, wherein the digital-to-analog conversion module converts the high-speed multi-bit signal into an analog signal;

And sending the converted analog signals to the outside of the chip for observation.

2. The method of real-time observation of high-speed on-chip signals according to claim 1, wherein said transmitting said high-speed multi-bit signals to a digital-to-analog conversion module included in said chip further comprises:

judging whether the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module;

And transmitting the high-speed multi-bit signal to the digital-to-analog conversion module when the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module.

3. The method for real-time observation of high-speed signals on a chip according to claim 2, further comprising:

when the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module, preprocessing the high-speed multi-bit signal, and transmitting the preprocessed high-speed multi-bit signal to the digital-to-analog conversion module.

4. The method of on-chip high-speed signal real-time observation according to claim 3, wherein the preprocessing comprises at least one of signal compression, signal truncation, and signal bit segmentation.

5. The method of real-time observation of high-speed on-chip signals according to claim 1, wherein said transmitting said high-speed multi-bit signals to a digital-to-analog conversion module included in said chip further comprises:

and when the clock domain of the high-speed multi-bit signal is different from the first clock domain of the digital-to-analog conversion module, performing cross-clock domain processing on the high-speed multi-bit signal, and converting the high-speed multi-bit signal into the first clock domain of the digital-to-analog conversion module.

6. The method of on-chip high-speed signal real-time observation according to claim 1, wherein the digital-to-analog conversion module converting the high-speed multi-bit signal into an analog signal comprises:

and comparing the high-speed multi-bit signal with each bit value of the high-speed multi-bit signal according to a plurality of reference signals preset in the digital-to-analog conversion module, and converting the high-speed multi-bit signal into analog signals with different levels.

7. A real-time observation system for on-chip high-speed signals, characterized by being adapted to implement the method for real-time observation of on-chip high-speed signals according to any one of claims 1 to 6, comprising:

The signal determining module is used for determining a key control signal to be observed, wherein the key control signal at least comprises a high-speed multi-bit signal;

The signal transmission module is connected with the signal determination module and used for transmitting the high-speed multi-bit signal to a digital-to-analog conversion module included in the chip, and the digital-to-analog conversion module is used for converting the high-speed multi-bit signal into an analog signal;

And the signal transmitting module is connected with the digital-to-analog conversion module and used for transmitting the converted analog signals to the outside of the chip for observation.

8. The on-chip high-speed signal real-time observation system according to claim 7, wherein the signal transmission module comprises:

the bit width judging unit is used for judging whether the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module;

The first signal transmission unit is connected with the bit width judging unit and is used for transmitting the high-speed multi-bit signal to the digital-to-analog conversion module when the bit width of the high-speed multi-bit signal is in the bit width supporting range of the digital-to-analog conversion module.

9. The on-chip high-speed signal real-time observation system according to claim 8, wherein the signal transmission module further comprises:

The preprocessing unit is connected with the bit width judging unit and is used for preprocessing the high-speed multi-bit signal when the bit width of the high-speed multi-bit signal exceeds the bit width supporting range of the digital-to-analog conversion module;

And the second signal transmission unit is connected with the preprocessing unit and is used for transmitting the preprocessed high-speed multi-bit signal to the digital-to-analog conversion module.

10. The on-chip high-speed signal real-time observation system according to claim 7, wherein the signal transmission module further comprises:

And the clock domain crossing processing unit is used for performing clock domain crossing processing on the high-speed multi-bit signal and converting the high-speed multi-bit signal into the first clock domain where the digital-to-analog conversion module is located when the clock domain where the high-speed multi-bit signal is located is different from the first clock domain where the digital-to-analog conversion module is located.