CN117971515A

CN117971515A - Operation instruction sending method, device, computer equipment and storage medium

Info

Publication number: CN117971515A
Application number: CN202311811173.7A
Authority: CN
Inventors: 徐基法; 李春香; 崔广银
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-12-26
Filing date: 2023-12-26
Publication date: 2024-05-03

Abstract

The invention relates to the technical field of computers, and discloses an operation instruction sending method, an operation instruction sending device, computer equipment and a storage medium, wherein the method comprises the following steps: receiving an operation instruction and message queue identification information sent by one or more upper computers in at least one upper computer; according to the message queue identification information, adding the operation instruction into a target message queue corresponding to the message queue identification information; identifying a priority of the target message queue; and sequentially sending the operation instructions to the second intermediate processor according to the priority of the target message queue and the arrangement sequence of the operation instructions in the target message queue, so that the second intermediate processor calls an I2C channel to transmit the operation instructions to a corresponding lower computer according to the sequence of receiving the operation instructions. The invention can realize the coordination and use of the I2C channel.

Description

Operation instruction sending method, device, computer equipment and storage medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method and apparatus for sending an operation instruction, a computer device, and a storage medium.

Background

In the field of computer technology, upper computer software may transmit instructions to or read data from a lower device via a bidirectional two-wire synchronous serial (I2C) bus.

When the I2C channel realizes the interaction function between the upper computer software and the lower end equipment, a half duplex mode is generally adopted, namely, data can be transmitted along two directions of the I2C channel, but the I2C channel cannot simultaneously perform data reading and writing operations. In order to perform read and write operations normally, general upper computer software performs locking control on the I2C channel through program codes. And before the upper computer software controls the lower-end equipment, acquiring the I2C channel lock.

However, in the practical application process, there may be a case where a plurality of upper computer software performs data operations on a plurality of lower end devices. The same upper computer software can only control the resource use of the thread where the same upper computer software is located, and cannot control the use of the I2C channel by other upper computer software. In summary, the related art cannot realize the coordinated use of the I2C channel.

Disclosure of Invention

In view of the above, the present invention provides a method, apparatus, computer device and storage medium for sending operation instructions, so as to solve the problem that the I2C channel cannot be used in coordination.

In a first aspect, the present invention provides a method for sending an operation instruction, where the method is applied to an operation instruction transmission system, where the operation instruction transmission system includes at least one upper computer, a first intermediate processor, a second intermediate processor, and at least one lower computer; the method is performed by the first intermediate processor, the method comprising:

receiving an operation instruction and message queue identification information sent by one or more upper computers in at least one upper computer;

According to the message queue identification information, adding the operation instruction into a target message queue corresponding to the message queue identification information;

Identifying a priority of the target message queue;

And sequentially sending the operation instructions to the second intermediate processor according to the priority of the target message queue and the arrangement sequence of the operation instructions in the target message queue, so that the second intermediate processor calls an I2C channel to transmit the operation instructions to a corresponding lower computer according to the sequence of receiving the operation instructions.

The method for sending the operation instruction has the following advantages:

By setting the message transfer station (the first intermediate processor), a message queue with priority is set on the message transfer station, so that the message transfer station can comprehensively arrange operation instructions from an upper computer and sequentially send the operation instructions to the second intermediate processor, and the second intermediate processor can acquire the use right of the I2C channel for the operation instructions one by one. Therefore, the coordination of I2C channels by different upper computers and different upper computer programs can be realized. In addition, the important operation instructions can be processed preferentially through priority transmission operation instructions, actual requirements are met, and serious consequences caused by the fact that the important operation instructions are not executed in time can be avoided.

In an alternative embodiment, the method further comprises:

when a first request sent by a first upper computer is received, acquiring the number of currently unprocessed operation instructions in a first message queue with highest preset priority, wherein the first request is a request sent to a first intermediate processor when the first request determines that the priority of one or more operation instructions to be sent in the first upper computer is greater than a preset priority threshold, and the first upper computer is any upper computer in at least one upper computer;

Determining whether one or more operation instructions to be sent can be accommodated in the first message queue according to the first request and the number of operation instructions which are not processed currently in the first message queue;

when the first message queue can accommodate one or more operation instructions to be sent, sending first response information to the first upper computer, wherein the first response information comprises queue identification information corresponding to the first message queue and is used for informing the first upper computer that one or more instructions to be sent are added to the first message queue later;

Or when the first message queue can not accommodate one or more operation instructions to be sent, creating a second message queue and queue identification information corresponding to the second message queue, wherein the priority of the second message queue is greater than or equal to that of the first message queue;

And sending second response information to the first upper computer, wherein the second response information comprises queue identification information corresponding to the second message queue and is used for informing the first upper computer that one or more operation instructions to be sent are added to the second message queue later.

Specifically, by determining the message queue identification information of the operation instruction with higher priority, the important operation instruction can be preferentially processed, and serious consequences caused by that the important operation instruction is not timely executed can be avoided.

In a second aspect, the present invention provides an operation instruction sending method, where the method is applied to an operation instruction transmission system, where the operation instruction transmission system includes at least one upper computer, a first intermediate processor, a second intermediate processor, and at least one lower computer; the method is performed by the second intermediate processor, the method comprising:

Receiving a first operation instruction sent by the first intermediate processor;

Adding the first operation instruction to a message processing queue;

When the processing order of the first operation instruction arrives according to the arrangement order of the first operation instruction in the message processing queue, extracting address information of a target lower computer and operation content to be executed for the target lower computer from the first operation instruction, wherein the target lower computer is a lower computer corresponding to the first operation instruction;

And according to the address information, the operation content is sent to the target lower computer through the I2C channel, so that the target lower computer executes the operation content.

The method for sending the operation instruction has the following advantages:

By setting the message transfer station (second intermediate processor), a message processing queue is set on the message transfer station, and the message processing queue can acquire the use right of the I2C channel for the operation instructions one by one according to the arrangement order of the operation instructions in the message processing queue. In this way, the coordination of the I2C channel by different operation instructions can be realized.

In an alternative embodiment, the method further comprises:

and after receiving a reply message corresponding to the first operation instruction fed back by the target lower computer through the I2C channel, processing a second operation instruction after the first operation instruction.

Specifically, after receiving the feedback message corresponding to the operation instruction, the next operation instruction is processed, so that only one piece of information (operation instruction or reply message) can be ensured to be in the I2C channel from the second intermediate processor to the lower computer, and the half duplex working mechanism of the I2C channel can be satisfied, namely the I2C channel can be used in a coordinated manner.

In an optional implementation manner, after the reply message corresponding to the first operation instruction and fed back by the target lower computer is received through the I2C channel, the method further includes:

Extracting address information of a target upper computer stored in the first operation instruction;

and feeding back the reply message to the target upper computer according to the address information of the target upper computer.

Specifically, the second intermediate process feeds back the reply message to the target upper computer, so that the target upper computer can know the execution result of each operation instruction in time. The operation instruction may also be reissued after the execution failure. In this way, serious consequences of failure in execution of the operation instruction can be avoided.

In a third aspect, the present invention provides an operation instruction sending method, where the method is applied to an operation instruction transmission system, where the operation instruction transmission system includes at least one upper computer, a first intermediate processor, a second intermediate processor, and at least one lower computer; the method is executed by any one of at least one upper computer, and comprises the following steps:

acquiring an operation instruction and attribute parameters corresponding to the operation instruction;

Determining the target priority of the operation instruction according to the attribute parameters;

when the target priority is smaller than or equal to a preset priority threshold, determining target queue identification information corresponding to the operation instruction according to the mapping relation between the priority and the queue identification information of the message queue and the target priority;

And sending the operation instruction and the target queue identification information to the first intermediate processor, so that the first intermediate processor adds the operation instruction to a target message queue corresponding to the target queue identification information according to the target queue identification information.

The method for sending the operation instruction has the following advantages:

the upper computer can determine a queue identification information for each operation instruction, wherein the queue identification information is related to the priority, so that after the upper computer sends the operation instructions and the queue identification information corresponding to the operation instructions to the first intermediate processor, the first intermediate processor can overall arrange each operation instruction according to the priority of each message queue, and send the operation instructions with high priority to the second intermediate processor in sequence, so that the second intermediate processor can acquire the use right of the I2C channel for the operation instructions one by one. Therefore, the coordination of I2C channels by different upper computers and different upper computer programs can be realized. In addition, the important operation instructions can be processed preferentially through priority transmission operation instructions, actual requirements are met, and serious consequences caused by the fact that the important operation instructions are not executed in time can be avoided.

In an alternative embodiment, when the target priority is greater than the preset priority threshold, the method further comprises:

A first request is sent to the first intermediate processor, wherein the first request is used for indicating the first intermediate processor to obtain the number of currently unprocessed operation instructions in a first message queue with highest preset priority, and response information is sent to the upper computer according to the number of currently unprocessed operation instructions in the first message queue;

Receiving response information sent by the first intermediate processor, wherein the response information comprises queue identification information of the first message queue or queue identification information of a second message queue, the queue identification information of the second message queue is a message queue created by the first intermediate processor when the first message queue is determined to not accommodate the operation instruction, and the priority of the second message queue is greater than or equal to that of the first message queue.

In a fourth aspect, the present invention provides an operation instruction transmitting apparatus, comprising:

The receiving module is used for receiving the operation instruction and the message queue identification information sent by one or more upper computers in the at least one upper computer;

The adding module is used for adding the operation instruction into a target message queue corresponding to the message queue identification information according to the message queue identification information;

an identification module for identifying a priority of the target message queue;

And the sending module is used for sequentially sending the operation instructions to a second intermediate processor according to the priority of the target message queue and the arrangement sequence of the operation instructions in the target message queue, so that the second intermediate processor calls an I2C channel to transmit the operation instructions to a corresponding lower computer according to the sequence of receiving the operation instructions.

In a fifth aspect, the present invention provides an operation instruction transmitting apparatus, the apparatus comprising:

the receiving module is used for receiving a first operation instruction sent by the first intermediate processor;

an adding module, configured to add the first operation instruction to a message processing queue;

The extraction module is used for extracting address information of a target lower computer and operation content to be executed for the target lower computer from the first operation instruction when the processing order of the first operation instruction arrives according to the arrangement order of the first operation instruction in the message processing queue, wherein the target lower computer is the lower computer corresponding to the first operation instruction;

and the sending module is used for sending the operation content to a target lower computer through an I2C channel according to the address information so that the target lower computer executes the operation content.

A sixth aspect, an obtaining module, configured to obtain an operation instruction and an attribute parameter corresponding to the operation instruction;

The determining module is used for determining the target priority of the operation instruction according to the attribute parameters; when the target priority is smaller than or equal to a preset priority threshold, determining target queue identification information corresponding to the operation instruction according to the mapping relation between the priority and the queue identification information of the message queue and the target priority;

And the sending module is used for sending the operation instruction and the target queue identification information to the first intermediate processor so that the first intermediate processor can add the operation instruction into a target message queue corresponding to the target queue identification information according to the target queue identification information.

In a seventh aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the method for sending the operation instructions according to any implementation manner corresponding to the first aspect, the second aspect, the third aspect or any aspect.

In an eighth aspect, the present invention provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the method for sending an operation instruction according to any embodiment of the first aspect, the second aspect, the third aspect, or any one of the aspects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an operation instruction transmission system according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for sending operation instructions executed by a first intermediate processor according to an embodiment of the invention;

FIG. 3 is a schematic diagram of the composition of a data packet according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for sending operation instructions executed by a second intermediate processor according to an embodiment of the present invention;

FIG. 5 is a flowchart of an operation instruction sending method executed by a host computer according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method for sending operation instructions executed by the operation instruction transmission system according to an embodiment of the present invention;

FIG. 7 is a flow chart of a method of determining message queue identification information performed by an operating instruction transmission system according to an embodiment of the invention;

FIG. 8 is a flow chart of a method performed by a host computer for determining message queue identification information according to an embodiment of the invention;

FIG. 9 is a flow chart of a method for sending operation instructions executed by another second intermediate processor according to an embodiment of the present invention;

fig. 10 is a block diagram of the structure of an operation instruction transmitting apparatus according to an embodiment of the present invention;

fig. 11 is a block diagram of the structure of an operation instruction transmitting apparatus according to an embodiment of the present invention;

fig. 12 is a block diagram of the structure of an operation instruction transmitting apparatus according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the technical field of computers, an operation instruction is generally transmitted between an upper computer and a lower computer through an I2C bus. The I2C bus is typically used in a half duplex mode for transmission of operating instructions. In such an operating mode, only one operating instruction can be transmitted at a time in the I2C bus.

The embodiment of the invention provides a method for sending operation instructions, which achieves the coordination use of I2C channels by sequencing and transmitting the operation instructions.

The scheme is applied to an operation instruction transmission system, and the structure of the operation instruction transmission system can be as shown in fig. 1 and can comprise at least one upper computer, a first intermediate processor, a second intermediate processor and at least one lower computer. The upper computer is a device that sends out an operation instruction, and may be a computer device, for example, a terminal, a server, and the like. The first intermediate processor and the second intermediate processor may each be a server. The first intermediate processor and the second intermediate processor may be the same server or different servers. The lower computer may be a device controlled by the upper computer, for example, a fan device, a temperature device, a waveform drawing device, and the like. The second intermediate processor may establish a connection with each lower computer via an I2C bus (i.e., an I2C channel).

The scheme also provides a message processing application program which can be matched with the operation instruction transmission system. The message processing application may include a client program, a server program, a consumer program. The client program can be installed on an upper computer, and at least one upper computer application program is installed on the upper computer and is generally used for determining corresponding message queue identification information for operation instructions generated by the upper computer application program. In practical applications, the client program may be loaded into each of the upper computer applications, and the communication address of the first intermediate processor may be specified in the upper computer application. The server-side program is installed on the first intermediate processor, and the server-side program is typically configured to provide a plurality of message queues. The consumption end program can be installed on the second intermediate processor and used with the control I2C driver program, and the received operation instructions are analyzed in sequence and the use right of the I2C channel is obtained so as to send the operation instructions to the corresponding lower computer. The message processing application may specifically be RocketMQ.

According to an embodiment of the present invention, there is provided a method embodiment of operating instruction transmission, it should be noted that the steps shown in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that herein.

In this embodiment, a method for sending an operation instruction is provided, which can be used in the operation instruction transmission system described above. FIG. 2 is a flow chart of a method of operating instruction transmission, performed by a first intermediate processor, as shown in FIG. 2, according to an embodiment of the invention, the flow comprising the steps of:

step S201, receiving an operation instruction and message queue identification information sent by one or more upper computers in at least one upper computer.

The operation instruction may be a read operation instruction or a write operation instruction.

Specifically, each operation instruction may correspond to one message queue identification information. The operation instruction and the message queue identification may be sent by the host computer to the first intermediate processor in the form of a data packet. As shown in fig. 3, the specific form of the data packet may be "option: read+ fromAdd:0x01+address:0x13+length:20b+topic: topic01", or may also be" option: write+ fromAdd:0x01+address:0x13+data: action1+ topic: topic02", wherein the option indicates the type of the operation instruction, fromAdd indicates which upper computer the operation instruction comes from, address indicates the address of the lower computer, that is, the device address where the operation instruction needs to be sent, length indicates the length of the read data, data indicates the content of the write data, and topic indicates the message queue identification information.

In some alternative embodiments, the data packet may further include identification information of the operation instruction, and the like.

Step S202, according to the message queue identification information, an operation instruction is added to a target message queue corresponding to the message queue identification information.

Specifically, a plurality of message queues may be established in the first intermediate processor, and each message queue may include message queue identification information, the message queue itself, and a priority. The message queue can correspondingly store some operation instructions, and the operation instructions can be arranged in the message queue from front to back according to the receiving time.

The specific process of adding an operation instruction to a target message queue corresponding to the message queue identification information according to the message queue identification information may include the following two ways:

First, for each operation instruction, the first intermediate processor may determine a target message queue from a plurality of message queues according to message queue identification information corresponding to the operation instruction. Further, the operation instruction is added to the target message queue.

Second, the corresponding operation instruction and the message queue identifier may be that the host computer sends the operation instruction and the message queue identifier to the first intermediate processor in the form of a data packet, where the first intermediate processor may extract the message queue identifier information from the received data packet, and determine the target message queue from the multiple message queues. Further, the operation instruction is added to the target message queue. If the data packet includes the identification information of the operation instruction, the first intermediate processor may add the identification information of the operation instruction to the target message queue, and store the operation instruction under the preset directory.

In step S203, the priority of the target message queue is identified.

In particular, the first intermediate processor may monitor in real time the number of operating instructions in the first message queue having the highest priority (referred to as the first priority). And when the number of the operation instructions in the first message queue is monitored to be not zero, processing the operation instructions in sequence according to the arrangement sequence of the operation instructions in the first message queue. When the number of operation instructions in the first message queue is monitored to be zero, determining a second priority (the second priority is only smaller than the first priority and larger than other priorities) according to a pre-stored priority list and the first priority. Further, the first intermediate processor may identify the priority of the message queue until a second message queue corresponding to the second priority is selected, process the operation instructions in the second message queue, and so on.

Step S204, according to the priority of the target message queue and the arrangement order of the operation instructions in the target message queue, the operation instructions are sequentially sent to the second intermediate processor.

Specifically, after all the instructions in the other message queues having the higher priority than the target message queue are processed, the operation instructions in the target message queue may be processed, and the operation instructions may be sequentially sent to the second intermediate processor. Or after all the instructions in other message queues with higher priority than the target message queue are processed, according to the arrangement order of the identification information of the operation instructions in the target message queue, the operation instructions corresponding to the identification information of each operation instruction can be obtained from a preset catalog and sent to the second intermediate processor. After receiving the operation instructions, the second intermediate processor can call the use right of the I2C channel for each operation instruction according to the time sequence of the received operation instructions, and the operation instructions are transmitted to the corresponding lower computer one by one.

According to the method for sending the operation instructions, the message transfer station (the first intermediate processor) is arranged, and the message queue with the priority is set on the message transfer station, so that the message transfer station can comprehensively arrange the operation instructions from the upper computer and send the operation instructions to the second intermediate processor in sequence, and the second intermediate processor can acquire the use right of the I2C channel for the operation instructions one by one. Therefore, the coordination of I2C channels by different upper computers and different upper computer programs can be realized. In addition, the important operation instructions can be processed preferentially through priority transmission operation instructions, actual requirements are met, and serious consequences caused by the fact that the important operation instructions are not executed in time can be avoided.

In this embodiment, a method for sending an operation instruction is provided, which can be used in the operation instruction transmission system described above. FIG. 4 is a flow chart of a method of operating instruction transmission, performed by a second intermediate processor, as shown in FIG. 4, according to an embodiment of the invention, the flow comprising the steps of:

Step S401, receiving a first operation instruction sent by a first intermediate processor.

The first operation instruction may be a read operation instruction or a write operation instruction. The first operation instruction may include an upper computer address, a lower computer address, a type of operation instruction, operation content, and the like. When the first operation instruction is a read operation instruction, the operation content may include a read data length, and when the first operation instruction is a write operation instruction, the operation content may include a write data content. In some alternative embodiments, the type of operating instructions may be part of the operating content.

Step S402, adding a first operation instruction to a message processing queue.

In particular, the second intermediate processor may comprise at least one message processing queue. When the second intermediate processor has only one message processing queue, the second intermediate processor can sequentially add the operation instructions to the message processing queue according to the sequence of the received operation instructions.

In some alternative embodiments, either of the following two processes may be performed prior to step S402:

First, when the second intermediate processor includes a plurality of message processing queues and each message processing queue may correspond to one priority, the second intermediate processor may determine the priority of the operation instruction according to the reception time and the degree of urgency of the operation instruction and add the operation instruction to the message processing queue corresponding to the priority. The emergency degree can be obtained from the operation instruction, or the emergency degree can be sent to the first intermediate processor by the upper computer and then sent to the second intermediate processor by the first intermediate processor. The priority may be proportional to the early and late times of reception and proportional to the magnitude of the degree of urgency.

Second, when the second intermediate processor includes a plurality of message processing queues, each message processing queue corresponds to a lower computer. Thus, when the first operation instruction is received, the second intermediate processor can extract the address of the target lower computer from the first operation instruction, and determine the corresponding message processing queue according to the address of the target lower computer. Or the second intermediate processor may extract the message queue identification information from the first operation instruction (the message queue identification information may be identification information of the target lower computer), and determine the corresponding message processing queue according to the message queue identification information. Different message processing queues correspond to different priorities.

In this way, the second intermediate processor may add the first operation instruction to the message processing queue corresponding to the target lower computer. The first intermediate processor determines the priority of the operation instruction for the first operation instruction, so that the operation instruction which is earlier or more important can be processed, the accumulation of early messages can be avoided, and the timely execution of the important operation instruction can be realized.

In step S403, when it is determined that the processing order of the first operation instruction arrives according to the arrangement order of the first operation instruction in the message processing queue, address information of the target lower computer and operation contents to be executed for the target lower computer are extracted from the first operation instruction.

The target lower computer is a lower computer corresponding to the first operation instruction.

Specifically, the message processing queue may store some operation instructions, and the operation instructions are arranged in the message processing queue from front to back according to the receiving time. The second intermediate processor may process each of the operation instructions according to the order in which the respective operation instructions are arranged in the message processing queue. When the processing order of the first operation instruction reaches according to the arrangement order of the first operation instruction in the message processing queue, the second intermediate processor can analyze the first operation instruction to obtain the address information of the target lower computer and the operation content to be executed for the target lower computer.

In addition, the second intermediate processor can also extract the address of the upper computer from the operation instruction, and write all the extracted information into the system file as a record, so that when a reply message corresponding to the operation instruction is received, the reply message can be timely fed back to the upper computer corresponding to the address of the upper computer, and the completion of the processing of the operation instruction is determined. At this time, the second intermediate processor may delete the extraction information corresponding to the operation instruction and start the processing of the next operation instruction.

Step S404, according to the address information, the operation content is sent to the target lower computer through the I2C channel.

Specifically, the second intermediate processor may determine the target lower computer according to the address information, and send the operation content to the target lower computer through the I2C channel. After receiving the operation content, the target lower computer can perform corresponding reading operation or writing operation. For example, when the target lower computer is a temperature device and the operation content includes a read data length and an operation type, the target lower computer may read a temperature value detected by itself and feed back the temperature value to the upper computer, or when the operation content includes a write data content (a reduced temperature value or an increased temperature value, etc.) and an operation type, the target lower computer may regulate the temperature of itself according to the write data content.

According to the method for sending the operation instructions, the message transfer station (the second intermediate processor) is arranged, the message processing queue is arranged on the message transfer station, and the message processing queue can acquire the use right of the I2C channel for the operation instructions one by one according to the arrangement sequence of the operation instructions in the message processing queue. In this way, the coordination of the I2C channel by different operation instructions can be realized.

In this embodiment, a method for sending an operation instruction is provided, which can be used in the operation instruction transmission system described above. Fig. 5 is a flowchart of a method for sending an operation instruction according to an embodiment of the present invention, which is executed by any one of the upper computers, as shown in fig. 5, and the flowchart includes the following steps:

in step S501, an operation instruction and an attribute parameter corresponding to the operation instruction are acquired.

The operation instruction may be a read operation instruction or a write operation instruction. The operation instruction may be generated according to the detected operation of the user, or may be an operation instruction triggered when a preset condition is satisfied. The operation instruction may include an upper computer address, a lower computer address, operation contents, operation types, and the like. When the operation instruction is a read operation instruction, the operation content may include a read data length, and when the operation instruction is a write operation instruction, the operation content may include a write data content. In some alternative implementations, the type of operation may be part of the content of the operation. The attribute parameters may include one or more of the type of the upper computer, the type of the upper computer program, the type of the operation instruction, the emergency degree of the operation instruction, whether the return of data is required, the preset execution time, and the like.

Step S502, determining the target priority of the operation instruction according to the attribute parameters.

Specifically, the upper computer may pre-store a correspondence between attribute parameters and weight values. For each operation instruction, the upper computer can determine a weight value corresponding to each attribute parameter according to each acquired attribute parameter and corresponding relation, and then determine the target priority according to each attribute parameter and the weight value corresponding to each attribute parameter.

Or for each operation instruction, the upper computer can input each attribute parameter into the priority determination model to obtain the target priority. The prioritization model may be a machine learning model, such as a fast elite multi-objective genetic algorithm (Non Dominated Sorting Genetic Algorithm-II, NSGA-II), or the like.

In step S503, when the target priority is less than or equal to the preset priority threshold, the target queue identification information corresponding to the operation instruction is determined according to the mapping relationship between the priority and the queue identification information of the message queue and the target priority.

Specifically, the upper computer may determine whether the target priority is less than or equal to the preset priority threshold, and if so, may determine the target queue identification information according to the mapping relationship between the priority and the queue identification information of the message queue and the target priority.

In some alternative embodiments, the calculated target priority may be preset to be less than or equal to the preset priority threshold in step S502, so that the upper computer may not perform the size judgment between the target priority and the preset priority threshold in step S503.

Step S504, the operation instruction and the target queue identification information are sent to the first intermediate processor.

Specifically, the upper computer may send the operation instruction and the target queue identification information to the first intermediate processor in the form of a data packet (for example, as shown in fig. 3), or may send the operation instruction and the target queue identification information to the first intermediate processor respectively. Thus, when the first intermediate processor receives the operation instruction and the target queue identification information, the first intermediate processor can determine the corresponding target message queue according to the target queue identification information, and add the operation instruction to the target message queue corresponding to the target queue identification information.

According to the method for sending the operation instructions provided by the embodiment, the upper computer can determine one queue identification information for each operation instruction, and the queue identification information is related to the priority, so that after the upper computer sends the operation instructions and the queue identification information corresponding to the operation instructions to the first intermediate processor, the first intermediate processor can comprehensively arrange each operation instruction according to the priority of each message queue, and send the operation instructions with high priority to the second intermediate processor in sequence, so that the second intermediate processor can acquire the use right of the I2C channel for the operation instructions one by one. Therefore, the coordination of I2C channels by different upper computers and different upper computer programs can be realized. In addition, the important operation instructions can be processed preferentially through priority transmission operation instructions, actual requirements are met, and serious consequences caused by the fact that the important operation instructions are not executed in time can be avoided.

In this embodiment, a method for sending an operation instruction is provided, which can be used in the operation instruction transmission system described above. Fig. 6 is a flowchart of a method of transmitting an operation instruction according to an embodiment of the present invention, which is performed by an operation instruction transmission system, as shown in fig. 6, and includes the steps of:

In step S601, the target upper computer obtains the operation instruction and the attribute parameters corresponding to the operation instruction.

In step S602, the target upper computer determines the target priority of the operation instruction according to the attribute parameters.

Step S603, when the target upper computer determines that the priority of the operation instruction is less than or equal to a preset priority threshold, determining target queue identification information corresponding to the operation instruction according to the mapping relation between the priority and the queue identification information of the message queue and the target priority;

In step S604, the target host computer sends the operation instruction and the target queue identification information to the first intermediate processor.

The specific processing of step S601 to step S604 is similar to the specific processing of step S501 to step S504, and will not be described here.

In step S605, the first intermediate processor adds an operation instruction to the target message queue corresponding to the target queue identification information according to the target queue identification information.

In step S606, the first intermediate processor identifies the priority of the target message queue.

In step S607, the first intermediate processor sequentially sends the operation instructions to the second intermediate processor according to the priority of the target message queue and the arrangement order of the operation instructions in the target message queue.

The specific processing of step S605 to step S607 is similar to that of step S202 to step S203, and will not be described here.

In step S608, the second intermediate processor adds the operation instruction to the message processing queue.

In step S609, when the second intermediate processor determines that the processing order of the first operation instruction arrives according to the arrangement order of the operation instructions in the message processing queue, the address information of the target lower computer and the operation content to be executed for the target lower computer are extracted from the first operation instruction.

The target lower computer is a lower computer corresponding to the first operation instruction;

in step S610, the second intermediate processor sends the operation content to the target lower computer through the I2C channel according to the address information.

The specific processing of steps S608 to S610 is similar to the specific processing of steps S402 to S404, and will not be described here.

In step S611, the target lower computer executes the operation content.

Specifically, after receiving the operation content, the target lower computer may perform a corresponding read operation or write operation. For example, when the target lower computer is a temperature device and the operation content includes a read data length and an operation type, the target lower computer may read a temperature value detected by itself and feed back the temperature value to the upper computer, or when the operation content includes a write data content (a reduced temperature value or an increased temperature value, etc.) and an operation type, the target lower computer may regulate the temperature of itself according to the write data content.

According to the method for sending the operation instructions, two message transfer stations are arranged, one message transfer station is used for carrying out overall arrangement (a first intermediate processor) on all the operation instructions, one message transfer station is used for processing all the operation instructions and calling the use right (a second intermediate processor) of the I2C channel, and an upper computer is used for presetting priority for the operation instructions. Therefore, the coordination of the I2C channel can be realized through the coordination processing of the upper computer, the first intermediate processor and the second intermediate processor. And the priority and the message queue are set, so that the important operation instruction is processed preferentially, and serious consequences caused by the fact that the important operation instruction is not executed in time can be avoided.

The following describes how to determine the message queue identification information corresponding to the operation instruction by using two specific embodiments.

Example 1

In this embodiment, a method for determining identification information of a message queue is provided, which can be used in the above operation instruction transmission system. Fig. 7 is a flowchart of a method of determining message queue identification information, performed by an operation instruction transmission system, according to an embodiment of the present invention, as shown in fig. 7, the flowchart including the steps of:

in step S701, when the first upper computer determines that the priority of the operation instruction is greater than the preset priority threshold, a first request is sent to the first intermediate processor.

The first upper computer is any one of at least one upper computer in the operation instruction transmission system. The first request may carry the number of operation instructions.

Specifically, for each operation instruction, the upper computer may determine whether the priority of the operation instruction is greater than a preset priority threshold, and if so, it indicates that there is no message queue corresponding to the priority in the first intermediate processor, and the priority of the operation instruction is higher, which is important and needs to be executed in time. At this time, the first host computer may send a first request to the first intermediate processor.

A plurality of operation instructions may exist in the first upper computer at the same time, and priorities of one or more operation instructions may exist in the plurality of operation instructions are all greater than a preset priority threshold. To avoid resource waste caused by each operation instruction issuing a first request, the number of the plurality of operation instructions may be added to the first request.

In step S702, the first intermediate processor obtains the number of currently unprocessed operation instructions in the first message queue with the highest preset priority.

Specifically, when the first intermediate processor receives the first request, the first intermediate processor may first identify the first message queue with the highest preset priority, and determine the number of currently unprocessed operation instructions in the first message queue.

In step S703, the first intermediate processor determines whether one or more operation instructions can be accommodated in the first message queue according to the first request and the number of operation instructions currently unprocessed in the first message queue.

Specifically, the first intermediate processor may determine whether the first number of operating instructions may be accommodated in the first message queue based on the first number of operating instructions extracted from the first request, the second number of operating instructions, and the third number of operating instructions. The second number value may be the determined number of operation instructions currently unprocessed in the first message queue, and the third number value is the maximum number of operation instructions that the first message queue can accommodate. Still further, the first intermediate processor may determine a number of operational instructions that may be accommodated by a remaining space of the first message queue.

In step S704, the first intermediate processor sends response information to the first upper computer according to the determination result of whether the first message queue can accommodate one or more operation instructions.

Specifically, step S704 may include:

first, when the first intermediate processor determines that one or more operation instructions to be sent can be accommodated in the first message queue, first response information is sent to the first upper computer.

The first response information may include queue identification information corresponding to the first message queue.

Specifically, when the first intermediate processor determines that all operation instructions corresponding to the first request can be accommodated in the first message queue, queue identification information corresponding to the first message queue can be obtained, and the queue identification information is added into the first response information and sent to the first upper computer.

Second, when the first intermediate processor determines that one or more operation instructions to be sent cannot be accommodated in the first message queue, creating a second message queue and queue identification information corresponding to the second message queue.

Wherein the priority of the second message queue may be greater than or equal to the priority of the first message queue.

Specifically, when the first intermediate processor determines that all the operation instructions corresponding to the first request cannot be accommodated in the first message queue, a first new message queue and queue identification information corresponding to the message queue, namely, the second message queue and the queue identification information of the second message queue, can be created.

Third, the first intermediate processor sends second response information to the first upper computer.

The second response information may include queue identification information corresponding to the second message queue.

Specifically, the first intermediate processor may add queue identification information of the second message queue to the second response information, and send the second response information to the first upper computer.

In some optional embodiments, when determining that the first message queue can only accommodate a part of the operation instructions corresponding to the first request, the first intermediate processor may send third response information to the first upper computer, where the third response information may include queue identification information corresponding to the first message queue and queue identification information corresponding to the second message queue.

Step S705, the first upper computer determines the message queue identification information according to the response information.

Specifically, the first upper computer may extract the message queue identification information from the received response information, which may specifically be: when the response information received by the first upper computer is the first response information, the queue identification information of the first message queue can be extracted from the first response information. When the response information received by the first upper computer is the second response information, the queue identification information of the second message queue can be extracted from the first response information.

Thus, the first upper computer can send the operation instruction and the extracted message queue identification information to the first intermediate processor correspondingly. The first intermediate processor may add the operation instruction to the message queue corresponding to the message queue identification information. When the message queue identification information is the queue identification information of the first message queue, the operation instruction is added into the first message queue. And when the message queue identification information is the queue identification information of the second message queue, adding the operation instruction into the second message queue.

According to the method for sending the operation instruction, the important operation instruction can be processed preferentially through determining the message queue identification information of the operation instruction with higher priority, and serious consequences caused by the fact that the important operation instruction is not executed in time can be avoided.

Example 2

In this embodiment, a method for determining identification information of a message queue is provided, which can be used in the above operation instruction transmission system. Fig. 8 is a flowchart of a method for determining message queue identification information, which is performed by any one of the upper computers in the operation instruction transmission system according to an embodiment of the present invention, as shown in fig. 8, the flowchart includes the steps of:

step S801, an operation instruction is acquired, and identification information of a target lower computer is determined according to the operation instruction.

Specifically, the upper computer may extract the identification information of the target lower computer from the operation instruction after the operation instruction is acquired.

Step S802, determining message queue identification information corresponding to the operation instruction according to the identification information of the target lower computer and the corresponding relation between the pre-acquired equipment identification information and the queue identification information.

Wherein, each queue identification information page in the corresponding relation between the equipment identification information and the queue identification information corresponds to a priority.

Specifically, the upper computer may determine, according to the identification information of the target lower computer, message queue identification information corresponding to the identification information of the target lower computer in a correspondence between the device identification information and the queue identification information.

In some optional embodiments, when it is detected that the temperature device is within the preset temperature threshold range in the current cycle, the upper computer may automatically generate an operation instruction for increasing the rotational speed of the fan, determine whether the priority of the queue identification information corresponding to the fan is the highest, if not, determine the queue identification information with the highest priority of the queue identification information, and determine the queue identification information with the highest priority as the message queue identification information corresponding to the operation instruction for increasing the rotational speed of the fan.

According to the method for sending the operation instruction, the upper computer can preset the queue identification information corresponding to each lower computer, so that the priority of the operation instruction is not required to be calculated, and processing resources can be saved.

In this embodiment, a method for sending an operation instruction is provided, which can be used in the operation instruction transmission system described above. Fig. 9 is a flowchart of a method of operating instruction transmission, performed by a second intermediate processor, as shown in fig. 9, according to an embodiment of the present invention, the flowchart including the steps of:

In step S901, after receiving a reply message corresponding to the first operation instruction fed back by the target lower computer through the I2C channel, a second operation instruction after the first operation instruction is processed.

Wherein the target lower computer is any one of a plurality of lower computers.

Specifically, after executing the first operation instruction, the target lower computer may feed back a reply message corresponding to the first operation instruction to the second intermediate process. If the first operation instruction is a read operation instruction, the reply message fed back by the target lower computer can include the content read on the target lower computer. If the first operation instruction is a write operation instruction, the feedback reply message may include an execution result of the first operation instruction, for example, execution success or execution failure.

When the second intermediate processor receives the reply message through the I2C channel, the second operation instruction may be subjected to subsequent processing, which is similar to the specific processing in step S403 and step S404, and will not be described herein.

In step S902, address information of the target upper computer stored in the first operation instruction is extracted.

Specifically, the second intermediate processor may extract the address information of the target upper computer from the first operation instruction, and then delete the first operation instruction in the message processing queue.

In some optional embodiments, the second intermediate processor may further extract address information of the target host computer corresponding to the first operation instruction from the system file (step S403).

In step S903, a reply message is fed back to the target host according to the address information of the target host.

Specifically, the second intermediate processor may send the reply message to the target upper computer corresponding to the address information of the target upper computer, so that the target upper computer may learn the processing result of the first operation instruction.

According to the method for sending the operation instruction, after the feedback message corresponding to the operation instruction is received, the next operation instruction is processed, so that only one piece of information (operation instruction or reply message) can be ensured in the I2C channel from the second intermediate processor to the lower computer, the half duplex working mechanism of the I2C channel can be met, and the I2C channel can be used in a coordinated mode. In addition, the second intermediate processing feeds back the reply message to the target upper computer, so that the target upper computer can know the execution result of each operation instruction in time. The operation instruction may also be reissued after the execution failure. In this way, serious consequences of failure in execution of the operation instruction can be avoided.

The embodiment also provides an operation instruction sending device, which is used for implementing the above embodiment and the preferred implementation manner, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides an operation instruction transmitting apparatus, as shown in fig. 10, including:

A receiving module 1001, configured to receive an operation instruction and message queue identification information sent by one or more of the at least one upper computer;

An adding module 1002, configured to add an operation instruction to a target message queue corresponding to the message queue identification information according to the message queue identification information;

An identifying module 1003, configured to identify a priority of the target message queue;

The sending module 1004 is configured to send the operation instructions to the second intermediate processor in sequence according to the priority of the target message queue and the arrangement order of the operation instructions in the target message queue, so that the second intermediate processor invokes the I2C channel to transmit the operation instructions to the corresponding lower computer according to the order of receiving the operation instructions.

In some alternative embodiments, the receiving module 1001 is further configured to:

determining whether one or more operation instructions to be sent can be accommodated in the first message queue according to the first request and the number of the operation instructions which are not processed currently in the first message queue;

When the first message queue can accommodate one or more operation instructions to be sent, sending first response information to the first upper computer, wherein the first response information comprises queue identification information corresponding to the first message queue and is used for informing the first upper computer that the one or more operation instructions to be sent can be added into the first message queue later;

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The present embodiment provides an operation instruction transmitting apparatus, as shown in fig. 11, including:

A receiving module 1101, configured to receive a first operation instruction sent by a first intermediate processor;

An adding module 1102, configured to add a first operation instruction to a message processing queue;

The extracting module 1103 is configured to extract, from the first operation instruction, address information of a target lower computer and operation content to be executed for the target lower computer when it is determined that the processing order of the first operation instruction arrives according to the arrangement order of the first operation instruction in the message processing queue, where the target lower computer is a lower computer corresponding to the first operation instruction;

And the sending module 1104 is used for sending the operation content to the target lower computer through the I2C channel according to the address information so that the target lower computer executes the operation content.

In some alternative embodiments, the receiving module 1101 is further configured to:

In some alternative embodiments, the extracting module 1103 is further configured to:

extracting address information of a target upper computer stored in a first operation instruction;

and feeding back a reply message to the target upper computer according to the address information of the target upper computer.

The present embodiment provides an operation instruction transmitting apparatus, as shown in fig. 12, including:

an obtaining module 1201, configured to obtain an operation instruction and an attribute parameter corresponding to the operation instruction;

A determining module 1202, configured to determine a target priority of the operation instruction according to the attribute parameter; when the target priority is smaller than or equal to a preset priority threshold, determining target queue identification information corresponding to the operation instruction according to the mapping relation between the priority and the queue identification information of the message queue and the target priority;

The sending module 1203 is configured to send the operation instruction and the target queue identification information to the first intermediate processor, so that the first intermediate processor adds the operation instruction to the target message queue corresponding to the target queue identification information according to the target queue identification information.

In some alternative embodiments, when the target priority is greater than the preset priority threshold, the sending module 1203 is further configured to:

A first request is sent to a first intermediate processor, wherein the first request is used for indicating the first intermediate processor to acquire the number of currently unprocessed operation instructions in a first message queue with highest preset priority, and response information is sent to an upper computer according to the number of the currently unprocessed operation instructions in the first message queue;

Receiving response information sent by the first intermediate processor, wherein the response information comprises queue identification information of a first message queue or queue identification information of a second message queue, the queue identification information of the second message queue is a message queue created by the first intermediate processor when the first message queue is determined to be incapable of accommodating an operation instruction, and the priority of the second message queue is greater than or equal to that of the first message queue.

Any of the above embodiments of the operation instruction transmitting apparatus are presented in the form of functional units, where the units refer to ASIC (Application SPECIFIC INTEGRATED Circuit) circuits, processors and memories that execute one or more software or firmware programs, and/or other devices that can provide the above functions.

The embodiment of the invention also provides computer equipment, which is provided with the operation instruction sending device shown in the figure 10 or the figure 11 or the figure 12.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 13, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 13.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. The method is applied to an operation instruction transmission system, and comprises at least one upper computer, a first intermediate processor, a second intermediate processor and at least one lower computer, wherein each upper computer is provided with a client program in a message processing application program, the client program is used for determining message queue identification information for a generated operation instruction, the first intermediate processor is provided with a server program in the message processing application program, the second intermediate processor is provided with a control I2C driver and a consumption end program in the message processing application program, the consumption end program is used for analyzing the operation instruction and determining a target lower computer, the control I2C driver is used for acquiring the use right of an I2C channel so as to execute the operation instruction, and the target lower computer is any one of the lower computers; the method is executed by the first intermediate processor running the server program, and the method includes:

Identifying a priority of the target message queue;

2. The method according to claim 1, wherein the method further comprises:

And sending second response information to the first upper computer, wherein the second response information comprises queue identification information corresponding to the second message queue and is used for informing the first upper computer that one or more instructions to be operated are added to the second message queue later.

3. An operation instruction sending method is characterized in that the method is applied to an operation instruction transmission system, the operation instruction transmission system comprises at least one upper computer, a first intermediate processor, a second intermediate processor and at least one lower computer, each upper computer is provided with a client program in a message processing application program, the client program is used for determining message queue identification information for generated operation instructions, the first intermediate processor is provided with a server program in the message processing application program, the server program is used for sequencing received operation instructions, and the second intermediate processor is provided with a control I2C driver program and a consumer program in the message processing application program; the method is performed by the second intermediate processor running the consumer program and the control I2C driver, the method comprising:

Adding the first operation instruction to a message processing queue;

4. A method according to claim 3, characterized in that the method further comprises:

5. The method according to claim 4, wherein after receiving a reply message corresponding to the first operation instruction fed back by the target lower computer through the I2C channel, the method further comprises:

6. The method is applied to an operation instruction transmission system, and is characterized in that the operation instruction transmission system comprises at least one upper computer, a first intermediate processor, a second intermediate processor and at least one lower computer, wherein a client program in a message processing application program is configured on each upper computer, a server program in the message processing application program is configured in the first intermediate processor, the server program is used for sequencing received operation instructions, a control I2C driver and a consumption program in the message processing application program are configured in the second intermediate processor, the consumption program is used for analyzing the operation instructions, a target lower computer is determined, the control I2C driver is used for acquiring the use right of an I2C channel so as to execute the operation instructions, and the target lower computer is any one of the at least one lower computer; the method is executed by any one of at least one upper computer running the client program, and the method comprises:

7. The method of claim 6, wherein when the target priority is greater than the preset priority threshold, the method further comprises:

8. An operation instruction transmitting apparatus, characterized in that the apparatus comprises:

9. An operation instruction transmitting apparatus, characterized in that the apparatus comprises:

10. An operation instruction transmitting apparatus, characterized in that the apparatus comprises:

The acquisition module is used for acquiring the operation instruction and attribute parameters corresponding to the operation instruction;

11. A computer device, comprising:

a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of transmitting operation instructions according to any one of claims 1 to 7.

12. A computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the operation instruction transmission method according to any one of claims 1 to 7.