CN117970989A

CN117970989A - Voltage stabilizer circuit

Info

Publication number: CN117970989A
Application number: CN202311516528.XA
Authority: CN
Inventors: 张长洪
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2023-11-14
Filing date: 2023-11-14
Publication date: 2024-05-03

Abstract

Embodiments of the present disclosure provide a voltage regulator circuit, comprising: an output module and a zero compensation module; wherein the output module is configured to determine a first frequency of the secondary pole at the first current in dependence on the first current flowing through the load element, the first frequency of the secondary pole being positively related to the first current; the zero compensation module is configured to adjust the capacitance value of the dynamic zero according to the first current, determine the second frequency of the dynamic zero according to the capacitance value of the dynamic zero, wherein the second frequency of the dynamic zero is the same as the first frequency of the secondary pole, the capacitance value of the dynamic zero is in negative correlation with the first current, the second frequency is in positive correlation with the first current, the second frequency compensates the first frequency, the second frequency of the dynamic zero follows the first frequency of the secondary pole, the dynamic zero tracks the frequency change of the secondary pole, the frequency dynamic compensation of the secondary pole is achieved, and the negative feedback system can stably work no matter what state the voltage stabilizer circuit is in.

Description

Voltage stabilizer circuit

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology and related technology, and in particular, to a voltage regulator circuit.

Background

Along with the development of semiconductor integrated circuits, portable electronic products mainly powered by batteries play an increasingly important role in daily life, and voltage regulation circuits are required in battery powered systems, so that LDO regulators (Low Dropout Regulator, low dropout regulators) are widely designed and used as one of the core units of the voltage regulation circuits due to their characteristics of simple structure, fast response speed, strong power supply ripple suppression capability, and the like. In LDO voltage regulator systems, the amount of current required by the load varies with the operating state of the load, and the impedance provided by the load varies due to the different load currents, which often results in unstable operation of the closed loop system formed by the LDO voltage regulator and its load.

In the prior art, the stable operation of the system is improved by designing a loop compensation circuit. The zero compensation is a common loop compensation method, and the adverse effect of the secondary pole on the loop stability is counteracted by setting a compensation zero, so that a feedback loop obtains a certain phase margin, and the loop is stable. In a linear voltage regulator circuit, since the load current varies in a large range, typically by at least 3 orders of magnitude, the output resistance of the linear voltage regulator is generally inversely proportional to the load current, and therefore the secondary dominant pole of the linear voltage regulator also varies by at least 3 orders of magnitude. The compensation method of the fixed zero point generally cannot meet the stability requirements under all load conditions, so a compensation method of the dynamic zero point following the load current change is commonly used. The most used dynamic zero compensation method is realized by using a method of connecting a fixed capacitor in series with a variable resistor, and the circuit area of the voltage stabilizer is larger because the capacitor is fixed and the capacitance value is large.

Disclosure of Invention

Embodiments described herein provide a voltage regulator circuit that solves the problems of the prior art.

According to the present disclosure, there is provided a voltage regulator circuit including: an output module and a zero compensation module;

Wherein the output module is configured to determine a first frequency of a secondary pole at a first current flowing through a load element, the first frequency of the secondary pole being positively related to the first current;

The zero compensation module is configured to adjust a capacitance value of a dynamic zero according to the first current, determine a second frequency of the dynamic zero according to the capacitance value of the dynamic zero, wherein the second frequency of the dynamic zero is identical to the first frequency of the secondary pole, the capacitance value of the dynamic zero is inversely related to the first current, the second frequency is positively related to the first current, and the second frequency compensates the first frequency.

In some embodiments of the present disclosure, the zero compensation module includes a load current sampling unit, a mirroring unit, and a dynamic zero generation unit;

Wherein the load current sampling unit is configured to collect a first current flowing through the load element and output a second current to the mirroring unit;

the mirror unit is configured to determine an amplification gain of the dynamic zero generating unit based on the second current;

the dynamic zero generating unit is configured to determine a capacitance value of a first capacitor according to the amplification gain, and determine a second frequency of the dynamic zero according to the capacitance value of the dynamic zero and an impedance of the dynamic zero.

In some embodiments of the present disclosure, the current sampling unit includes a first transistor, the mirroring unit includes a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor, and the dynamic zero generating unit includes a third resistor and a first capacitor;

The first end of the first transistor and the first end of the fourth transistor are respectively and electrically connected with a power supply voltage node, the second end of the first transistor is respectively and electrically connected with the first end of the second transistor, the control end of the second transistor and the control end of the third transistor, the second end of the second transistor, the second end of the third transistor and the second end of the second resistor are respectively and electrically connected with a grounding node, the first end of the third transistor is respectively and electrically connected with the second end of the first resistor and the first end of the second resistor, the first end of the first resistor is respectively and electrically connected with the first end of the first capacitor and the second end of the fourth transistor, and the second end of the first capacitor is respectively and electrically connected with the second end of the third resistor and the control end of the fourth transistor.

In some embodiments of the disclosure, the first capacitance is an adjustable capacitance.

In some embodiments of the present disclosure, the dynamic zero generation unit is further configured to determine a third frequency of the dominant pole from the amplification gain and the impedance of the dominant pole, the third frequency being positively correlated with the first current.

In some embodiments of the disclosure, the third resistor is an adjustable resistor.

In some embodiments of the present disclosure, the output module includes an output power tube, a second capacitor, a fourth resistor and a fifth resistor, where a first end of the output power tube is electrically connected to a power supply voltage node, a second end of the output power tube is electrically connected to the first end of the second capacitor and the first end of the fourth resistor, a second end of the second capacitor and a second end of the fifth resistor are electrically connected to a ground node, and a second end of the fourth resistor is electrically connected to the first end of the fifth resistor.

In some embodiments of the present disclosure, the system further comprises a voltage stabilizing module and a driving module;

The voltage stabilizing module is configured to determine an error signal based on a preset reference voltage and an output feedback voltage, and adjust the output voltage based on the error signal;

the driving module is configured to output a driving signal to an output power tube according to the error voltage.

In some embodiments of the present disclosure, the voltage stabilizing module includes an amplifier, a first end of the amplifier is electrically connected to a reference voltage node, a second end of the amplifier is electrically connected to a second end of the fourth resistor, and a third end of the amplifier is electrically connected to the first end of the third resistor, the control end of the first transistor, and the first end of the driving module, respectively;

The driving module is a unit gain driving circuit.

In some embodiments of the present disclosure, the first transistor and the fourth transistor are PMOS transistors, and the second transistor and the third transistor are NMOS transistors.

According to the voltage stabilizer circuit provided by the embodiment of the disclosure, the zero compensation module adjusts the capacitance value of the dynamic zero according to the first current flowing through the load element, and determines the second frequency of the dynamic zero according to the capacitance value of the dynamic zero, wherein the capacitance value of the dynamic zero is in negative correlation with the first current flowing through the load element, namely, the capacitance value of the dynamic zero is dynamically adjusted according to the conversion quantity of the first current, so that the second frequency of the dynamic zero follows the first frequency of the secondary pole, the dynamic zero tracks the frequency change of the secondary pole, the frequency dynamic compensation of the secondary pole is realized, and the negative feedback system can stably work no matter what state the voltage stabilizer circuit is in, and the effective compensation of the voltage stabilizer circuit is realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

fig. 1 is a schematic circuit diagram of a voltage regulator circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic circuit diagram of a prior art voltage regulator circuit according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, since the source and drain of the transistor are symmetrical and the on-current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in embodiments of the present disclosure, the control terminal of the transistor is referred to as a first terminal, the drain of the transistor is referred to as a second terminal, and the source of the transistor is referred to as a third terminal. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Based on the problems existing in the prior art, the embodiment of the present disclosure provides a voltage regulator circuit, and fig. 1 is a schematic circuit diagram of the voltage regulator circuit provided in the embodiment of the present disclosure, as shown in fig. 1, the voltage regulator circuit includes: an output module 40 and a zero compensation module 30; wherein the output module 40 is configured to determine a first frequency of the secondary pole C at the first current I1, the first frequency of the secondary pole being positively related to the first current I1, based on the first current I1 flowing through the load element; the zero compensation module 30 is configured to adjust the capacitance value of the dynamic zero D according to the first current I1, and determine a second frequency of the dynamic zero according to the capacitance value of the dynamic zero D, where the second frequency of the dynamic zero is the same as the first frequency of the secondary pole, the capacitance value of the dynamic zero is inversely related to the first current, the second frequency is positively related to the first current, and the second frequency compensates the first frequency.

Zero drift is a phenomenon that when an input signal of an amplifying circuit is zero, a static working point is changed due to the influence of factors such as temperature change, unstable power supply voltage and the like, and is amplified and transmitted step by step, so that the voltage of an output end of the circuit deviates from an original fixed value and floats up and down. In order to solve the zero drift, a zero compensation module can be added into the circuit, and the zero drift is compensated by the zero compensation module. The zero compensation module in the embodiment can generate miller compensation through the compensation resistor and the compensation capacitor, and compensate zero drift generated by the secondary pole point in the voltage stabilizer circuit.

In the prior art, the voltage regulator circuit includes a voltage regulator module 10', a driving module 20', a zero compensation module 30 'and an output module 40', as shown in fig. 2, the voltage regulator module 10 'includes an amplifier EA', the driving module 20 'includes a unity gain driving circuit Buff', the zero compensation module 30 'includes a first resistor R1' and a first capacitor C1', the output module 40' includes an output power tube Mprw ', a second resistor R2', a third resistor R3 'and a second capacitor C2', a first end of the amplifier EA 'is electrically connected with a reference voltage node Vref', a second end of the amplifier EA is electrically connected with a first end of the third resistor R3', a third end of the amplifier EA' is electrically connected with a first end of the unity gain driving circuit Buff 'and a first end of the first resistor R1', a second end of the unity gain driving circuit Buff 'is electrically connected with a control end of the output power tube Mprw', a first end of the output power tube Mprw 'is electrically connected with a power voltage node Vcc', a second end of the output power tube Mprw 'is electrically connected with a second end of the second resistor R2', a second end of the third resistor R2 'and a second end of the third resistor R3' is electrically connected with a second end of the third resistor R1', a third end of the third resistor C2' is electrically connected with a second end of the third resistor C2', a third end of the third resistor C2' is electrically connected with a second end of the third resistor C1', and a third end of the third resistor C2' is electrically connected with a third end of the third resistor C1', and a third end of the output resistor is electrically connected with a third end of the output resistor b 3' is electrically connected with a third end of the output node is.

Since the output impedance Rea 'of the amplifier EA' is large, the output point a of the amplifier EA 'is the main pole point in the voltage stabilizing negative feedback loop, the frequency of the voltage stabilizing negative feedback loop is the frequency of the main pole point a, the equivalent capacitance of the main pole point a is Ca' (the equivalent capacitance of the main pole point a is related to the amplifier EA 'and the unit gain driving circuit Buff'), and the frequency of the main pole point a satisfies: The purpose of the unit gain driving circuit Buff ' is to reduce the impedance of the output point B of the unit gain driving circuit Buff ' so that the frequency of the output point B of the unit gain driving circuit Buff ' has negligible influence on the stability of the voltage stabilizing negative feedback loop. Since the output load capacitance (i.e., the second capacitance C2 ') of the voltage regulator circuit has a large variation range (uF level to hundred uF level), the load current Iload ' output by the voltage regulator circuit has a large range (0 to ampere level), i.e., the equivalent impedance Rout ' of the second end C of the output power tube Mprw ' has a large variation range (when no load is output, the equivalent impedance Rout ' is extremely large, and the equivalent impedance Rout ' is extremely small when heavy load is output), the frequency of the second end C of the output power tube Mprw ' will vary greatly, the frequency of the second end C of the output power tube Mprw ' will have a certain influence on the frequency of the main pole a, and therefore the second end C of the output power tube Mprw ' is the secondary pole in the voltage-stabilizing negative feedback loop, and the frequency of the secondary pole D satisfies When the output load current Iload 'is no-load and the second capacitor C2' is extremely large, the frequency of the secondary pole point C is close to the frequency of the primary pole a, even the secondary pole point C enters the bandwidth, two poles are arranged in the bandwidth, and the voltage stabilizing negative feedback loop is unstable. In the prior art, in order to solve the problem of unstable voltage stabilizing negative feedback loop, by setting the zero compensation module 30', the zero compensation module 30' comprises a first resistor R1' and a first capacitor C1', the first resistor R1' is an adjustable resistor, the first capacitor C1' is a fixed capacitor, the zero compensation module 30' generates a dynamic zero D based on the first resistor R1' and the first capacitor, and changes the frequency of the dynamic zero D acting on the primary pole a by adjusting the adjustable resistor R1', so as to realize that the frequency of the dynamic zero D follows the frequency of the secondary pole C, and the dynamic zero D compensates the frequency of the secondary pole C. However, in the prior art, since the frequency of the secondary pole C varies greatly, the capacitance value of the first capacitor C1 'set by the zero compensation module 30' is large, so that the overall area of the voltage regulator circuit is large.

In order to solve the problems existing in the prior art, in the voltage stabilizer circuit provided in the embodiment of the present disclosure, the zero compensation module 30 adjusts the capacitance value of the dynamic zero D according to the first current I1 flowing through the load element, and determines the second frequency of the dynamic zero D according to the capacitance value of the dynamic zero D, where the capacitance value of the dynamic zero is inversely related to the first current flowing through the load element, that is, dynamically adjusts the capacitance value of the dynamic zero according to the transformation amount of the first current, so as to implement the second frequency of the dynamic zero to follow the first frequency of the secondary pole, and the dynamic zero to track the frequency variation of the secondary pole, so as to implement the frequency dynamic compensation of the secondary pole, and achieve the effective compensation of the voltage stabilizer circuit in any state where the negative feedback system can stably operate.

As a specific embodiment, as shown in fig. 1, the zero compensation module includes a load current sampling unit, a mirroring unit, and a dynamic zero generating unit; the load current sampling unit is configured to collect a first current flowing through the load element and output a second current to the mirror image unit; an image unit configured to determine an amplification gain of the dynamic zero point generation unit based on the second current; and a dynamic zero generating unit configured to determine a capacitance value of the first capacitor according to the amplification gain, and determine a second frequency of the dynamic zero according to the capacitance value of the first capacitor and the impedance of the dynamic zero.

In a specific embodiment, the current sampling unit includes a first transistor M1, the mirror unit includes a second transistor M2, a third transistor M3, a fourth transistor M4, a first resistor R1 and a second resistor R2, and the dynamic zero generating unit includes a third resistor R3 and a first capacitor C1; the first end of the first transistor M1 and the first end of the fourth transistor M4 are respectively electrically connected to the power supply voltage node Vcc, the second end of the first transistor M1 is respectively electrically connected to the first end of the second transistor M2, the control end of the second transistor M2 and the control end of the third transistor M3, the second end of the second transistor M2, the second end of the third transistor M3 and the second end of the second resistor R2 are respectively electrically connected to the ground node, the first end of the third transistor M3 is respectively electrically connected to the second end of the first resistor R1 and the first end of the second resistor R2, the first end of the first resistor R1 is respectively electrically connected to the first end of the first capacitor C1 and the second end of the fourth transistor M4, and the second end of the first capacitor C1 is respectively electrically connected to the second end of the third resistor R3 and the control end of the fourth transistor M4.

The first capacitor C1 is an adjustable capacitor.

The output module includes an output power tube Mprw, a second capacitor C2, a fourth resistor R4 and a fifth resistor R5, a first end of the output power tube Mprw is electrically connected to the power supply voltage node Vcc, a second end of the output power tube Mprw is electrically connected to the first end of the second capacitor C2 and the first end of the fourth resistor R4, a second end of the second capacitor C2 and a second end of the fifth resistor R4 are electrically connected to the ground node, and a second end of the fourth resistor R4 is electrically connected to the first end of the fifth resistor R5.

The load current sampling unit can acquire a second current I2 with the same change rate as the first current I1, and the ratio of the second current I2 to the first current I1 satisfies K1:1, namely the load current sampling unit only needs to acquire the change rate of the first current I1. Referring to fig. 1, if the first current flowing through the load element is I1, the second current flowing through the first transistor M1 is i2=k1×i1, and K1 is far smaller than 1.

When the second current flowing through the first transistor M1 is I2, the second transistor M2 of the mirroring unit mirrors the second current I2 flowing through the first transistor M1 to the third transistor M3, and the equivalent impedance of the third transistor M3 is related to the second current I2 mirrored by the second transistor M2, the larger the second current I2 is, the smaller the equivalent impedance of the third transistor M3 is, the smaller the second current I2 is, the larger the equivalent impedance of the third transistor M3 is, i.e., the equivalent impedance of the third transistor M3 is inversely related to the second current I2, i.e., the equivalent impedance of the third transistor M3 is inversely related to the first current I1.

Since the first resistor R1, the second resistor R2, the third transistor M3 and the fourth transistor M4 form a common-source unipolar amplifier, the amplification gain of the common-source unipolar amplifier is Av, and according to the miller theorem, the equivalent capacitance of the dynamic zero D relative to the source of the fourth transistor M4 is (1+av) ×cc, that is, the adjusted capacitance value of the dynamic zero is (1+av) ×cc, the second frequency generated by the dynamic zero at the main pole point a satisfies: Where av=r (k×w/L (vgs_m3-Vth)), R3 is the resistance of the third resistor, R is the load resistor of the dynamic zero generating unit, r=r1+ (r2// r_m3), r_m3=k2×f (1/I1), r_m3 is the equivalent resistance of the third transistor at the second current, R2// r_m3 is the resistance corresponding to the parallel connection of the equivalent resistance of the first resistor and the equivalent resistance of the third transistor, f is the correlation function of the equivalent resistance of the third transistor and the first current I1 flowing through the load element, vgs_m3 is the gate-source voltage of the third transistor, W/L is the width-length ratio of the third transistor, vth is the threshold voltage of the third transistor, and vgs_m3, W/L and Vth are fixed values, so that the second frequency generated by the dynamic zero at the main pole point a is related to the load resistor of the dynamic zero generating unit, that is related to the equivalent resistance of the third transistor. Since the equivalent impedance of the third transistor is inversely related to the second current, that is, the equivalent impedance of the third transistor is inversely related to the first current, when the first current decreases, the equivalent impedance r_m3 of the third transistor increases, r=r1+ (r2// r_m3) increases, the amplification gain Av of the dynamic zero generating unit increases, the equivalent capacitance (1+av) Cc of the dynamic zero relative to the source of the fourth transistor increases, and the second frequency of the dynamic zero decreases without changing the resistance of the third resistor; when the first current increases, the equivalent impedance r_m3 of the third transistor decreases, r=r1+ (r2// r_m3) decreases, the amplification gain Av of the dynamic zero generating unit decreases, the equivalent capacitance (1+av) Cc of the dynamic zero relative to the source of the fourth transistor decreases, and the second frequency increases under the condition that the resistance of the third resistor is unchanged, that is, the second frequency of the dynamic zero is positively correlated with the first current.

The capacitance value of the output module, i.e. the capacitance value of the second capacitor, is usually fixed, but when the first current changes, the resistance value of the load resistor in the output module is affected, i.e. the resistance value of the load resistor changes with the current in the circuit. As can be seen from the pole frequency formula, the first frequency of the secondary pole satisfies: when the first current I1 decreases, the output load increases, the first frequency of the secondary pole decreases under the condition that the capacitance value of the second capacitor is unchanged, when the first current increases, the output load decreases, and under the condition that the capacitance value of the second capacitor is unchanged, the first frequency of the secondary pole increases, that is, the first frequency of the secondary pole and the first current are positively correlated. Therefore, in the embodiment of the application, the first capacitor of the zero compensation module is inversely related to the first current, so that the change rates of the load resistor and the first capacitor are controlled to be consistent, and the compensation of the second frequency of the dynamic zero to the first frequency of the secondary pole is realized.

The second frequency corresponding to the compensation zero point is changed by adjusting the equivalent capacitance of the dynamic zero point D relative to the source stage of the fourth transistor M4, and the equivalent capacitance of the dynamic zero point D relative to the source stage of the fourth transistor M4 is related to the first current of the load element, so that the second power generated by the dynamic zero point can compensate the first power corresponding to the fundamental secondary point, a compensation zero point which dynamically changes along with the frequency of the secondary point can be generated in the voltage stabilizer circuit no matter what the power of the load element is, the frequency of the secondary point is offset through the second frequency of the compensation zero point, the effective dynamic compensation of the frequency of the secondary point is realized, the stable output voltage is output, and the oscillation of the voltage stabilizer circuit is avoided.

On the basis of the above embodiment, in combination with fig. 1, the dynamic zero generating unit is further configured to determine a third frequency of the dominant pole according to the amplification gain and the impedance of the dominant pole, the third frequency being positively correlated with the first current.

Wherein the third resistor is an adjustable resistor.

In the embodiment of the present disclosure, on the basis of compensating the frequency of the secondary pole point by the dynamic zero, by setting the third resistor R3 as an adjustable resistor, the third frequency of the primary pole satisfies: That is, the third frequency of the main pole a also changes with the first current, when the first current decreases, the equivalent impedance r_m3 of the third transistor increases, r=r1+ (r2// r_m3) increases, the amplification gain Av of the dynamic zero generating unit increases, the equivalent capacitance (1+av) Cc of the dynamic zero with respect to the source of the fourth transistor increases, and when the resistance of the third resistor does not change, the third frequency of the main pole decreases; when the first current increases, the equivalent impedance r_m3 of the third transistor decreases, r=r1+ (r2// r_m3) decreases, the amplification gain Av of the dynamic zero generating unit decreases, the equivalent capacitance (1+av) Cc of the dynamic zero relative to the source of the fourth transistor decreases, and the third frequency of the main pole increases, i.e. the third frequency of the main pole is positively correlated with the first current, under the condition that the resistance of the third resistor is unchanged. Therefore, on the basis of compensating the frequency of the secondary pole by the dynamic zero, the third frequency of the primary pole A is changed along with the first current, namely the bandwidth is increased, so that the voltage stabilizing negative feedback loop responds faster, and the power supply voltage rejection ratio (PSRR) is better.

Specifically, when the first current decreases, from the first frequency of the pole decreases, the equivalent impedance r_m3 of the third transistor increases, r=r1+ (r2// r_m3) increases, the amplification gain Av of the dynamic zero generating unit increases, the equivalent capacitance (1+av) Cc of the dynamic zero with respect to the source of the fourth transistor increases, the second frequency of the dynamic zero decreases, and the third frequency of the main pole decreases, with the resistance of the third resistor unchanged; when the first current increases, the equivalent impedance r_m3 of the third transistor decreases from the first frequency of the pole, r=r1+ (r2// r_m3) decreases, the amplification gain Av of the dynamic zero generating unit decreases, the equivalent capacitance (1+av) Cc of the dynamic zero with respect to the source of the fourth transistor decreases, the second frequency increases and the third frequency of the main pole increases with the resistance of the third resistor unchanged.

That is, in the initial state, the second frequency of the dynamic zero point is the same as the first frequency of the slave pole, the first frequency of the slave pole changes along with the change of the first current, the change amount of the first frequency of the slave pole is positively correlated with the first current, the second frequency of the dynamic zero point also changes, the change amount of the second frequency of the dynamic zero point is positively correlated with the first current, that is, the changed second frequency of the dynamic zero point always follows the first frequency of the slave pole, and the second frequency generated by the dynamic zero point is the same as the first frequency of the slave pole, so that the first frequency of the slave pole is counteracted, and the stable output voltage is ensured to be output by the voltage stabilizer circuit. In addition, on the basis of the frequency compensation of the dynamic zero to the slave pole, the third frequency of the master pole is also changed along with the first current and is positively correlated with the first current, namely when the first current is increased, the third frequency of the master pole is increased, the bandwidth of the voltage stabilizer circuit is improved, the response speed is improved, and the power supply voltage rejection ratio (PSRR) is improved.

With continued reference to fig. 1, based on the above embodiments, the voltage regulator circuit further includes a voltage regulator module 10 and a driving module 20; a voltage stabilizing module configured to determine an error signal based on a preset reference voltage and an output feedback voltage, and adjust the output voltage based on the error signal; the driving module is configured to output a driving signal to the output power tube according to the error voltage.

The voltage stabilizing module 10 includes an amplifier EA, a first end of the amplifier EA is electrically connected to the reference voltage node Vref, a second end of the amplifier EA is electrically connected to a second end of the fourth resistor R4, and a third end of the amplifier EA is electrically connected to a first end of the third resistor R3, a control end of the first transistor M1, and a first end of the driving module 30, respectively; the driving module is a unit gain driving circuit.

The LDO is a linear voltage regulator, and because the voltage in the circuit is unstable, the output voltage of the voltage regulator circuit also fluctuates, the output voltage can be divided by a plurality of voltage dividing resistors, the difference between the divided output feedback voltage and the reference voltage is used as an error signal, and the output voltage can be regulated by the error signal, so that the divided output feedback voltage is close to the reference voltage.

As shown in fig. 1, a voltage signal input by a power supply voltage node Vcc passes through an output power tube Mprw to obtain an output voltage Vout, the output voltage Vout is divided by a fourth resistor R4 and a fifth resistor R5, a first input terminal of an error amplifier EA receives a reference voltage, and a second input terminal of the error amplifier EA receives the divided output feedback voltage; the error amplifier takes the difference value between the reference voltage and the divided output feedback voltage as an error signal, and realizes negative feedback adjustment of the output voltage based on the error signal.

In addition, in the above embodiment, by setting the driving module as the unity gain driving circuit, the output impedance of the second end of the driving module is ensured to be low, and the pole of the second end B point of the driving module is far away from the main pole a point, so that the influence of the pole of the second end B point of the driving module on the loop stability is negligible.

In the above embodiment, the first transistor M1 and the fourth transistor M4 are PMOS transistors, and the second transistor M2 and the third transistor M3 are NMOS transistors.

On the basis of the above embodiments, the embodiments of the present disclosure further provide an electronic device, where the electronic device includes the voltage regulator circuit according to any one of the above embodiments, and has the beneficial effects according to any one of the above embodiments, which is not illustrated one by one.

The electronic device includes a memory and a processor communicatively coupled to each other via a system bus. It should be noted that only electronic devices having components are shown in the figures, but it should be understood that not all of the illustrated components are required to be implemented and that more or fewer components may be implemented instead. It will be understood by those skilled in the art that the electronic device herein is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and its hardware includes, but is not limited to, a microprocessor, an Application SPECIFIC INTEGRATED Circuit (ASIC), a Programmable gate array (Field-Programmable GATE ARRAY, FPGA), a digital Processor (DIGITAL SIGNAL Processor, DSP), an embedded device, and the like.

The electronic device may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The electronic device can perform man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch pad or voice control equipment and the like.

The memory includes at least one type of readable storage medium including a non-volatile memory (non-volatile memory) or a volatile memory, for example, a flash memory (flash memory), a hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a random access memory (random access memory, RAM), a read-only memory (ROM), an erasable programmable read-only memory (erasable programmable read-only memory, EPROM), an electrically erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-only memory, EEPROM), a programmable read-only memory (programmable read-only memory, PROM), a magnetic memory, a magnetic disk, a optical disk, etc., and the RAM may include a static RAM or a dynamic RAM. In some embodiments, the memory may be an internal storage unit of the electronic device, such as a hard disk or a memory of the electronic device. In other embodiments, the memory may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, or a flash memory card (FLASH CARD) or the like, which are provided on the electronic device. Of course, the memory may also include both internal storage units of the electronic device and external storage devices. In this embodiment, the memory 410 is typically used to store an operating system and various types of application software installed on the electronic device, such as program codes of the above-described methods. In addition, the memory can be used to temporarily store various types of data that have been output or are to be output.

The processor is typically used to perform the overall operations of the electronic device. In this embodiment, the memory is used to store program codes or instructions, the program codes include computer operation instructions, and the processor is used to execute the program codes or instructions stored in the memory 410 or process data, such as the program codes for executing the above-mentioned method.

Herein, the bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, a peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The bus system may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.

Further aspects and scope of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A voltage regulator circuit, comprising: an output module and a zero compensation module;

2. The voltage regulator circuit of claim 1, wherein the zero compensation module comprises a load current sampling unit, a mirroring unit, and a dynamic zero generation unit;

3. The voltage regulator circuit of claim 2, wherein the current sampling unit comprises a first transistor, the mirror unit comprises a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor, and the dynamic zero generating unit comprises a third resistor and a first capacitor;

4. A voltage regulator circuit according to claim 3, wherein the first capacitance is an adjustable capacitance.

5. A voltage regulator circuit according to claim 3, wherein the dynamic zero generation unit is further configured to determine a third frequency of a dominant pole from the amplification gain and the impedance of the dominant pole, the third frequency being positively correlated with the first current.

6. The voltage regulator circuit of claim 5, wherein the third resistor is an adjustable resistor.

7. The voltage regulator circuit of claim 1, wherein the output module comprises an output power tube, a second capacitor, a fourth resistor and a fifth resistor, wherein a first end of the output power tube is electrically connected to a power supply voltage node, a second end of the output power tube is electrically connected to the first end of the second capacitor and the first end of the fourth resistor, respectively, a second end of the second capacitor and a second end of the fifth resistor are electrically connected to a ground node, respectively, and a second end of the fourth resistor is electrically connected to the first end of the fifth resistor.

8. The voltage regulator circuit of claim 7, further comprising a voltage regulator module and a driver module;

9. The voltage regulator circuit of claim 8, wherein the voltage regulator module comprises an amplifier, a first end of the amplifier being electrically connected to a reference voltage node, a second end of the amplifier being electrically connected to the second end of the fourth resistor, a third end of the amplifier being electrically connected to the first end of the third resistor, the control end of the first transistor, and the first end of the drive module, respectively;

The driving module is a unit gain driving circuit.

10. The voltage regulator circuit of claim 3, wherein the first transistor and the fourth transistor are PMOS transistors and the second transistor and the third transistor are NMOS transistors.