CN117970070A - Boolean satisfaction-based compression method and device for automatic circuit test vector - Google Patents
Boolean satisfaction-based compression method and device for automatic circuit test vector Download PDFInfo
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Abstract
The application discloses a method and a device for compressing automatic circuit test vectors based on Boolean satisfaction. Wherein the method comprises the following steps: acquiring an original test vector set and a test fault set of a target chip, wherein the original test vector set comprises a plurality of test vectors; performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set to determine a tested fault subset of the test fault set; establishing a local fault dictionary by using a second test vector subset of the original test vector set and an unmeasured fault subset of the test fault set, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the unmeasured fault subset; and calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector. The application solves the technical problem that vector compression is time-consuming in the related art.
Description
Technical Field
The application relates to the field of chip testing, in particular to a method and a device for compressing automatic circuit testing vectors based on Boolean satisfaction.
Background
This section is intended to provide a background or context for the matter recited in the claims or specification, which is not admitted to be prior art by inclusion in this section.
Static test vector compression (STATIC TEST Vector Compression) is a technique used in chip testing that aims to reduce the memory requirements and test time of test data while maintaining full coverage of chip functionality. In chip testing, a large number of test vectors are required to verify the function and performance of the chip. These test vectors are a series of input data that are used to excite the chip and observe the output results. However, the number of test vectors is often very large, especially for complex chip designs, which may lead to a substantial increase in memory requirements and test time.
The static test vector compression technique realizes compression of test vectors by utilizing redundancy and repeatability among test vectors and state information inside a chip. Specifically, it can achieve compression in several ways:
1) Compression based on encoding: the method uses encoding techniques to convert the test vectors into a more compact representation. For example, run-Length Encoding (Run-Length Encoding) may be used to encode consecutive identical bit patterns into a count value, thereby reducing storage space.
2) Compression based on pattern matching: the method achieves compression by identifying and storing a repeating pattern between test vectors. When the same test vector or similar sequence of test vectors is found, the pattern need only be stored once and then reproduced using the corresponding instructions or parameters.
3) Compression based on state compression: the method uses state information inside the chip to compress the test vector. By storing and reusing the internal states of the chip during testing, the number of test vectors required may be reduced. This may be achieved by sharing state information between test vectors or by state restoration techniques.
The static test vector compression technique can significantly reduce the storage requirement and test time of test data, thereby reducing the cost and complexity of chip testing. However, static test vector compression techniques also face some challenges. For example, the compression and decompression process may increase test time because additional calculations and operations are required. In addition, the design and implementation of the compression algorithm needs to take the characteristics and test requirements of the chip into consideration, so as to ensure that the compressed test vector can still effectively cover the functions of the chip.
In view of the above problems, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the application provides a method and a device for compressing an automatic circuit test vector based on Boolean satisfaction, which at least solve the technical problem that vector compression is time-consuming in the related art.
According to an aspect of an embodiment of the present application, there is provided a method for compressing a circuit automatic test vector based on boolean satisfaction, including: acquiring an original test vector set and a test fault set of a target chip, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults; performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises the tested fault subset and an undetected fault subset, the tested fault subset is used for storing tested faults, and the undetected fault subset is used for storing undetected test faults; establishing a local fault dictionary by using the second test vector subset and the untested fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset; and calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector.
Optionally, performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set includes: dividing the original test vector set into a first test vector subset and a second test vector subset according to a preset proportion, wherein the number of test vectors in the second test vector subset is greater than that of the test vectors in the first test vector subset; and carrying out fault simulation on all test faults in the test fault set by using the first test vector subset, and determining the tested fault subset.
Optionally, establishing a local fault dictionary using the second subset of test vectors and the subset of unmeasured faults includes: performing fault simulation on test faults in the untested fault subset by using the test vectors in the second test vector subset to obtain the relation between each test vector and all test faults; and establishing the local fault dictionary by utilizing the relation between each test vector and all test faults, wherein each row of the local fault dictionary corresponds to one test vector or test fault, each column corresponds to one test fault or test vector, any row and column of crossed elements are used for representing the relation between the corresponding test vector and the corresponding test fault, the element has a value of 1 and indicates that the test vector can detect the test fault, and the element has a value of 0 and indicates that the test vector cannot detect the test fault.
Optionally, after calling Pure MaxSAT the problem solver to solve the local fault dictionary, so as to obtain a reduced test vector, the method further includes: and taking the obtained simplified test vectors of the second test vector subset and the first test vector subset as final test vectors of the target chip.
Optionally, obtaining the original test vector set of the target chip includes: before an automatic test vector generation (ATPG) tool is called to generate a test vector for the target chip, setting a test mode of the ATPG tool to be a specified test mode, wherein the specified test mode is used for indicating the number n of vectors required by one test fault, and the value of n is 2 or 3; and calling the automatic test vector generation ATPG tool to generate the original test vector set for the target chip.
Optionally, calling Pure MaxSAT a problem solver to solve the local fault dictionary, thereby obtaining a reduced test vector, including: processing the local fault dictionary to obtain a WCNF file to be input into a Pure MaxSAT problem solver, wherein the WCNF file is recorded with a data structure of the local fault dictionary; and inputting the WCNF file into the Pure MaxSAT problem solver to solve the problem to obtain the simplified test vector.
Optionally, in the process of inputting the WCNF file into the Pure MaxSAT problem solver for solving, the method further includes: identifying a key vector in the WCNF file, wherein the key vector is a test vector which can only detect a certain test fault; the key vectors are solved as vectors that must be preserved.
According to another aspect of the embodiment of the present application, there is also provided a device for compressing an automatic test vector of a circuit based on boolean satisfaction, including: the device comprises an acquisition unit, a test fault detection unit and a test fault detection unit, wherein the acquisition unit is used for acquiring an original test vector set and a test fault set of a target chip, the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults; a determining unit, configured to perform fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determine a tested fault subset of the test fault set, where the original test vector set includes the first test vector subset and a second test vector subset, and the test fault set includes the tested fault subset and an untested fault subset, and the tested fault subset is used to store tested faults, and the untested fault subset is used to store untested test faults; the creating unit is used for utilizing the second test vector subset and the untested fault subset to create a local fault dictionary, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset; and the compression unit is used for calling Pure MaxSAT a problem solver to solve the local fault dictionary so as to obtain a simplified test vector.
According to another aspect of the embodiments of the present application, there is also provided a storage medium including a stored program that executes the above-described method when running.
According to another aspect of the embodiments of the present application, there is also provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the method described above by the computer program.
According to one aspect of the present application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the steps of any of the embodiments of the method described above.
In the embodiment of the application, an original test vector set and a test fault set of a target chip are obtained, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults; performing fault simulation on all test faults in a test fault set by using a first test vector subset of an original test vector set, determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises a tested fault subset and an unmeasured fault subset, the tested fault subset is used for storing tested faults, and the unmeasured fault subset is used for storing unmeasured test faults; establishing a local fault dictionary by using the second test vector subset and the unmeasured fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the unmeasured fault subset; calling Pure MaxSAT a problem solver to solve a local fault dictionary so as to obtain a simplified test vector, in the scheme, establishing the local fault dictionary, selecting a small batch of vectors for fault simulation, screening out the unmeasured faults and the rest vectors to form the local fault dictionary, and reducing the vectors of the fault dictionary into Pure MaxSAT problems; providing an expansion candidate vector set method, providing more candidate vectors for vector reduction by an n-detect mode in an ATPG algorithm, and improving the reduction effect; the special solver for specially solving Pure MaxSAT problems in the SAT problem is introduced into STC, and the rapid STC problem solving is realized through the efficient local search algorithm design. The technical problem that vector compression is time-consuming in the related art can be solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a flow chart of an alternative Boolean satisfaction based compression method for circuit automatic test vectors according to an embodiment of the application;
FIG. 2 is a schematic diagram of an alternative Boolean-satisfaction-based compression scheme for circuit automatic test vectors according to embodiments of the application;
FIG. 3 is a schematic diagram of an alternative Boolean-satisfaction-based compression scheme for circuit automatic test vectors according to embodiments of the application;
FIG. 4 is a schematic diagram of an alternative Boolean satisfaction based compression device for circuit automatic test vectors according to embodiments of the application; and
Fig. 5 is a block diagram of a structure of a terminal according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In static test vector compression STC, the STC problem can be converted into a Pure Maximum Satisfiability (Pure MaxSAT) special case in Partial Maximum Satisfiability (Partial MaxSAT) problem by creating a fault dictionary, i.e., a record of the fault set that each test vector can detect, partial MaxSAT, i.e., in one boolean expression, the truth assignment of the required variables must satisfy all hard clauses and the maximum number of soft clauses; pure MaxSAT under the above precondition, it is required that all hard clauses in the boolean expression are pure clauses having the same polarity (positive) and all soft clauses are pure clauses having opposite polarity (negative).
The Pure MaxSAT problem that the fault dictionary is built and solved is converted into is two critical time bottlenecks in the STC, however the STC is a set of NP-Complete problems, i.e., there is no one algorithm so that the problem is effectively solved in linear time.
For a circuit of a test vector set consisting of n test vectors and a fault set consisting of m faults, fault simulation needs to be performed on each vector to build a fault dictionary, and each fault is simulated, so that excessive calculation complexity is brought in actual production and application.
To solve the above-described problem of STC, a multi-objective test set optimization method (DPSO) based on particle swarm may be used to search for the compressed test set using a heuristic algorithm that optimizes the objective guided particle swarm for maximum failure detection rate, minimum number of tests, and minimum test cost. A line weighted local search method (Row Weighting Local Search, RWLS) provides a preprocessing step that effectively reduces search space prior to local search and employs multiple tabu strategies to effectively avoid repetition and cycling of the search to search for compressed test sets. In addition, there are genetic algorithm-based solving algorithms of a single-target optimized particle swarm algorithm and a special set coverage problem solver.
The STC problem solving algorithm greatly increases the solving time under the condition of overlarge problem scale. The increase in time comes mainly from two aspects: firstly, a large amount of time is needed for establishing a fault dictionary for fault simulation, each vector is needed to perform fault simulation on all faults, the scale of a fault set linearly grows along with the increase of the scale of a circuit, and the vector does not linearly grow but also rises, so that the scale of the fault dictionary is excessively linearly grown; secondly, the problem of STC is very difficult to solve due to the increase of the size of the fault dictionary, and the solving time of the solver generally increases in a super-linear manner along with the linear increase of the size of the fault dictionary.
STC effect is severely limited by the quality of the vector, which is generally evaluated by the number of faults that can be measured by a vector, the greater the number, the better the quality. However, since the conventional ATPG algorithm (ATPG is called Automatic TEST PATTERN Generation, which is a process of automatically generating test pattern vectors by a program used in the test of semiconductor electric appliances), the test vectors are sequentially loaded on input pins of a device, and output signals are collected and compared with the budgeted test vectors to judge the test result.
In order to efficiently implement digital circuit automatic test vector static compression (STC) and improve performance, according to an aspect of an embodiment of the present application, a method embodiment of a method for compressing a circuit automatic test vector based on boolean satisfaction is provided. The scale of the fault dictionary can be greatly reduced by establishing the local fault dictionary, so that the fault simulation time required by establishing the fault dictionary and the time for solving the Pure MaxSAT problem solver are greatly reduced; by providing a wider range of candidate test vectors via the "n-detect" mode in the ATPG algorithm, better vector reduction can be achieved.
FIG. 1 is a flow chart of an alternative Boolean satisfaction based circuit automatic test vector compression method according to an embodiment of the application, as shown in FIG. 1, the method may include the steps of:
step S102, an original test vector set and a test fault set of a target chip are obtained, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults.
In the technical scheme of the application, when the original test vector set of the target chip is obtained, the test mode of the automatic test vector generation tool is set to be a designated test mode, the designated test mode is used for indicating the number n of vectors required by a test fault, the value of n is 2 or 3, and then the automatic test vector generation ATPG tool is called to generate the original test vector set for the target chip. In an Automatic TEST PATTERN Generation (ATPG) algorithm, n-detect is a fault detection metric used for evaluating the capability of a test mode to detect faults in a chip, and in the technical scheme of the application, the value of n is smaller, so that the method has higher test efficiency: the smaller value of n means that the test mode can meet the requirement only by detecting a small number of faults, which can reduce the number of the test modes and the test time and improve the test efficiency.
Step S104, performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises a tested fault subset and an unmeasured fault subset, the tested fault subset is used for storing tested faults, and the unmeasured fault subset is used for storing unmeasured test faults.
In the technical scheme of the application, the original test vector set can be divided into a first test vector subset and a second test vector subset according to a preset proportion, and the number of test vectors in the second test vector subset is far more than that of the test vectors in the first test vector subset, for example, the preset proportion is 1:9; and carrying out fault simulation on all the test faults in the test fault set by using the first test vector subset, and determining a tested fault subset.
And S106, utilizing the second test vector subset and the untested fault subset to establish a local fault dictionary, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset.
In the technical scheme of the application, the test faults in the non-tested fault subset are simulated by using the test vectors in the second test vector subset, so that the relation between each test vector and all the test faults is obtained; and establishing a local fault dictionary by utilizing the relation between each test vector and all test faults, wherein each row of the local fault dictionary corresponds to one test vector or test fault, each column corresponds to one test fault or test vector, any row and column of crossed elements are used for representing the relation between the corresponding test vector and the corresponding test fault, the test fault can be detected by the test vector when the value of the element is 1, and the test fault cannot be detected by the test vector when the value of the element is 0.
And S108, calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector.
In the technical scheme of the application, the local fault dictionary is processed to obtain a WCNF file to be input into a Pure MaxSAT problem solver, wherein the WCNF file is recorded with a data structure of the local fault dictionary; and inputting the WCNF file into the Pure MaxSAT problem solver to solve the problem to obtain the simplified test vector.
During the process of inputting the WCNF file into the Pure MaxSAT problem solver for solving, identifying a key vector in the WCNF file, wherein the key vector is the only test vector capable of detecting a certain test fault;
and after the Pure MaxSAT problem solver is called to solve the local fault dictionary so as to obtain the simplified test vectors, the obtained simplified test vectors of the second test vector subset and the first test vector subset are used as final test vectors of the target chip.
Through the steps, an original test vector set and a test fault set of the target chip are obtained, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults; performing fault simulation on all test faults in a test fault set by using a first test vector subset of an original test vector set, determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises a tested fault subset and an unmeasured fault subset, the tested fault subset is used for storing tested faults, and the unmeasured fault subset is used for storing unmeasured test faults; establishing a local fault dictionary by using the second test vector subset and the unmeasured fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the unmeasured fault subset; calling Pure MaxSAT a problem solver to solve a local fault dictionary so as to obtain a simplified test vector, in the scheme, establishing the local fault dictionary, selecting a small batch of vectors for fault simulation, screening out the unmeasured faults and the rest vectors to form the local fault dictionary, and reducing the vectors of the fault dictionary into Pure MaxSAT problems; providing an expansion candidate vector set method, providing more candidate vectors for vector reduction by an n-detect mode in an ATPG algorithm, and improving the reduction effect; the special solver for specially solving Pure MaxSAT problems in the SAT problem is introduced into STC, and the rapid STC problem solving is realized through the efficient local search algorithm design. The technical problem that vector compression is time-consuming in the related art can be solved.
The application provides a digital circuit test vector reduction scheme based on Pure MaxSAT solver, which is characterized in that: aiming at two bottlenecks of the large-scale circuit STC problem, a fault dictionary is established to need too many time bottlenecks of fault simulation, and solving difficulty is bottleneck caused by too large scale of the fault dictionary. As an alternative example, the following further details the technical solution of the present application in connection with the specific embodiments:
The general framework of this scheme is described below with the example in fig. 2, and is largely divided into four steps of performing a commercial DFT procedure (DFT is collectively referred to as Design for Testability, i.e., test-designable, a design technique and method aimed at enhancing testability of an integrated circuit, which is a series of techniques and strategies employed in the design process of an integrated circuit to ensure that the design is effectively tested and fault-detected), building a fault dictionary, CNF generation, and solving by a specialized SAT solver. Fig. 2 shows a schematic diagram of the entire flow.
1) A commercial DFT procedure is performed. The conventional ATPG algorithm running in commercial DFT tools is typically "1-detect", meaning that when a fault is detected it is discarded and only test vectors are generated for faults that are not currently detected.
Commercial DFT (Design for Testability, test programmable) flow is a series of techniques and methods employed in the design of integrated circuits to ensure the testability and reliability of the design. Commercial DFT flow typically includes the following key steps:
1.1 Test requirement analysis: at the beginning of the design, the goals, constraints, and requirements of the test are determined. This includes defining test coverage targets, fault models, test resource budgets, and the like.
1.2 DFT planning: and (5) according to the test requirements, making a test strategy and planning. It is determined which DFT techniques and methods to use and how they apply in the design.
1.3 Scan chain design): scan chains are a commonly used DFT technique that is used to simplify the loading and output of test patterns. In a scan chain design, registers in the design are converted to a scannable form so that test patterns can enter and exit the circuit through the scan chain.
1.4 Boundary scan design): boundary scan is a scanning technique used to test input and output interfaces in a design. By adding scan chains over the input and output interfaces, the functionality and communication of these interfaces can be effectively tested.
1.5 Fault simulation and test pattern generation: the design is fault simulated using a fault simulation tool to evaluate the coverage and fault detection capabilities of the test pattern. And generating a test mode according to the fault simulation result so as to activate and detect faults in the design.
1.6 ATPG is a technique for automatically generating test patterns. By using the ATPG tool, a test pattern capable of detecting faults in the design is automatically generated according to the fault model and the test requirements.
1.7 The commercial DFT flow may also include some special Test techniques such as BIST (Built-In Self-Test), boundary Scan, etc. These techniques may provide self-test and self-verification functions inside the chip, reducing reliance on external test equipment.
1.8 Verification and simulation): after the design is completed, verification and simulation are performed to ensure the correctness and testability of the design under various operating conditions. This includes functional verification, timing verification, simulation of test patterns, and the like.
The goal of the commercial DFT procedure is to ensure that the design has good test coverage, high fault detection capability and reliability. By integrating the related technology and method of test in the design process, the test efficiency of the chip can be improved, the test cost can be reduced, and the product quality and reliability can be improved.
In the ATPG algorithm, "n-test" refers to a fault detection metric that measures the minimum number of test vectors required to detect each fault in a circuit. It specifies the number of vectors needed to detect all faults at least n times, where n is typically set to 2 or more. For example, if set to "2-detect", this means that at least two vectors are required to detect the fault to achieve the required fault coverage. The metrics may be used to evaluate the effectiveness of the test set and optimize the number of test vectors needed to achieve the desired fault coverage. In general, the "n-detect" metric will increase the number of test vectors generated by the ATPG algorithm.
Thus, when running the ATPG algorithm in a commercial DFT tool, the "2-detect" and "3-detect" modes are also specified in hopes of generating more candidate test vectors, regardless of the larger "n-detect" which would result in longer ATPG execution times and an excessive number of vectors generated.
2) And establishing a fault dictionary. The scheme selects 10% of vectors generated by the commercial ATPG tool for fault simulation, discards detectable faults, and obtains reserved 90% of vectors and faults which cannot be detected at present for unidirectional vector fault simulation. This creates a fault dictionary that records the faults that each vector can detect. The selected 10% vector is directly retained without reduction.
3) WCNF. The special SAT solver of the present solution design is a Pure MaxSAT solver, whose input file is referred to as WCNF (weighted conjunctive normal form), and in order to describe the WCNF generation process, the following definitions and symbols are used. Let t= { T 1,T2,…,Tm } be a given set of test vectors, where T i is a single test vector and m is a count of T. The set of stuck-at faults (SAFs) is denoted as f= { F 1,F2,……,Fn }, where F j is a single testable fault and n is a count of F. The fault dictionary describing the mapping between test vectors and faults may be represented as a matrix, m rows representing test vectors and n columns representing faults. For test vector t i and fault f j, the value of the matrix is denoted as r (t i,fj), if test vector t i (row) is able to detect fault f j (column), then the value of the matrix takes r (t i,fj) =1, otherwise r (t i,fj) =0.
Fig. 3 shows a process of converting a fault dictionary into CNF. TestSet (f j) represents a vector set in which a fault f j can be detected, C j represents the j-th clause in WCNF, where the number of clauses equals the vector count plus the fault count in the fault dictionary, i.e., m+n.
4) A dedicated SAT solver. The scheme designs a special part Pure MaxSAT solver which combines preprocessing of the identification key vectors and aims at accelerating the solving process. A key vector is defined as a vector that can uniquely detect a specific fault in a fault dictionary. By querying TestSet (f j) for size, we can identify key vectors. If TestSet (f j) is equal to 1, this indicates that fault f j can only be detected by this key vector and that this vector must be preserved. This information can then be used to accelerate the initial solution.
In summary, the invention provides a test vector static compression method based on Pure MaxSAT solver, which establishes a local fault dictionary through single vector fault simulation and can be converted into WCNF to be input to Pure MaxSAT solver to obtain a reduced vector set, thereby achieving the purpose of reducing test period and test cost. Verification is performed on the ISCAS and reference circuits of ITC99, with the result that the invention is verified for validity.
The invention verifies on ISCAS and ITC99 reference circuits, comprehensively evaluates the vector quantity and test period before and after the test vector set contract, and shows the effectiveness of the invention relative to the traditional heuristic strategy. The method and the device can solve the STC problem more quickly under the condition that the program occupies less memory, and the reduction effect of the complete fault dictionary is not greatly different.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.
According to another aspect of the embodiment of the present application, there is also provided a device for compressing a boolean satisfaction-based circuit automatic test vector for implementing the above-mentioned boolean satisfaction-based circuit automatic test vector compression method. FIG. 4 is a schematic diagram of an alternative Boolean satisfaction based circuit automatic test vector compression apparatus according to an embodiment of the present application, as shown in FIG. 4, which may include:
An obtaining unit 41, configured to obtain an original test vector set and a test fault set of a target chip, where the original test vector set includes a plurality of test vectors, and the test fault set includes a plurality of test faults;
A determining unit 43, configured to perform fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determine a tested fault subset of the test fault set, where the original test vector set includes the first test vector subset and a second test vector subset, and the test fault set includes the tested fault subset and an untested fault subset, and the tested fault subset is used to store tested faults, and the untested fault subset is used to store untested test faults;
A creating unit 45, configured to create a local fault dictionary by using the second subset of test vectors and the subset of untested faults, where the local fault dictionary is used to record an association between test vectors in the second subset of test vectors and test faults in the subset of untested faults;
and the compression unit 47 is used for calling Pure MaxSAT a problem solver to solve the local fault dictionary so as to obtain a simplified test vector.
Optionally, the determining unit is further configured to: dividing the original test vector set into a first test vector subset and a second test vector subset according to a preset proportion, wherein the number of test vectors in the second test vector subset is greater than that of the test vectors in the first test vector subset; and carrying out fault simulation on all test faults in the test fault set by using the first test vector subset, and determining the tested fault subset.
Optionally, the creating unit is further configured to: performing fault simulation on test faults in the untested fault subset by using the test vectors in the second test vector subset to obtain the relation between each test vector and all test faults; and establishing the local fault dictionary by utilizing the relation between each test vector and all test faults, wherein each row of the local fault dictionary corresponds to one test vector or test fault, each column corresponds to one test fault or test vector, any row and column of crossed elements are used for representing the relation between the corresponding test vector and the corresponding test fault, the element has a value of 1 and indicates that the test vector can detect the test fault, and the element has a value of 0 and indicates that the test vector cannot detect the test fault.
Optionally, the compression unit is further configured to, after calling Pure MaxSAT the problem solver to solve the local fault dictionary, obtain a reduced test vector, use the obtained reduced test vector of the second test vector subset and the first test vector subset as a final test vector of the target chip.
Optionally, the obtaining unit is further configured to: before an automatic test vector generation (ATPG) tool is called to generate a test vector for the target chip, setting a test mode of the ATPG tool to be a specified test mode, wherein the specified test mode is used for indicating the number n of vectors required by one test fault, and the value of n is 2 or 3; and calling the automatic test vector generation ATPG tool to generate the original test vector set for the target chip.
Optionally, the compression unit is further configured to: processing the local fault dictionary to obtain a WCNF file to be input into a Pure MaxSAT problem solver, wherein the WCNF file is recorded with a data structure of the local fault dictionary; and inputting the WCNF file into the Pure MaxSAT problem solver to solve the problem to obtain the simplified test vector.
Optionally, the compression unit is further configured to: during the process of inputting the WCNF file into the Pure MaxSAT problem solver for solving, identifying a key vector in the WCNF file, wherein the key vector is a test vector which can only detect a certain test fault; the key vectors are solved as vectors that must be preserved.
Acquiring an original test vector set and a test fault set of a target chip through the module, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults; performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises the tested fault subset and an undetected fault subset, the tested fault subset is used for storing tested faults, and the undetected fault subset is used for storing undetected test faults; establishing a local fault dictionary by using the second test vector subset and the untested fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset; calling Pure MaxSAT a problem solver to solve the local fault dictionary so as to obtain a simplified test vector, in the scheme, establishing the local fault dictionary, selecting a small batch of vectors for fault simulation, screening out the unmeasured faults and the rest vectors to form the local fault dictionary, and reducing the vectors of the fault dictionary into Pure MaxSAT problems; providing an expansion candidate vector set method, providing more candidate vectors for vector reduction by an n-detect mode in an ATPG algorithm, and improving the reduction effect; the special solver for specially solving Pure MaxSAT problems in the SAT problem is introduced into STC, and the rapid STC problem solving is realized through the efficient local search algorithm design. The technical problem that vector compression is time-consuming in the related art can be solved.
It should be noted that the above modules are the same as examples and application scenarios implemented by the corresponding steps, but are not limited to what is disclosed in the above embodiments. It should be noted that, the above modules may be implemented in a corresponding hardware environment as part of the apparatus, and may be implemented in software, or may be implemented in hardware, where the hardware environment includes a network environment.
According to another aspect of the embodiment of the present application, there is also provided a server or a terminal for implementing the above-mentioned compression method of the automatic test vector for a circuit based on boolean satisfaction.
Fig. 5 is a block diagram of a terminal according to an embodiment of the present application, and as shown in fig. 5, the terminal may include: one or more (only one is shown in the figure) processors 501, memory 503, and transmission means 505, as shown in fig. 5, the terminal may further comprise input output devices 507.
The memory 503 may be used to store software programs and modules, such as program instructions/modules corresponding to the method and apparatus for compressing a boolean-satisfaction-based circuit automatic test vector in the embodiments of the present application, and the processor 501 executes the software programs and modules stored in the memory 503 to perform various functional applications and data processing, that is, implement the method for compressing a boolean-satisfaction-based circuit automatic test vector. Memory 503 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid state memory. In some examples, the memory 503 may further include memory located remotely from the processor 501, which may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 505 is used for receiving or transmitting data via a network, and may also be used for data transmission between the processor and the memory. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 505 includes a network adapter (Network Interface Controller, NIC) that may be connected to other network devices and routers via a network cable to communicate with the internet or a local area network. In one example, the transmission device 505 is a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.
Wherein in particular the memory 503 is used for storing application programs.
The processor 501 may call an application stored in the memory 503 via the transmission means 505 to perform the following steps:
acquiring an original test vector set and a test fault set of a target chip, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults;
Performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises the tested fault subset and an undetected fault subset, the tested fault subset is used for storing tested faults, and the undetected fault subset is used for storing undetected test faults;
Establishing a local fault dictionary by using the second test vector subset and the untested fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset;
and calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector.
Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the structure shown in fig. 5 is only illustrative, and the terminal may be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile internet device (Mobile INTERNET DEVICES, MID), a PAD, etc. Fig. 5 is not limited to the structure of the electronic device. For example, the terminal may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in fig. 5, or have a different configuration than shown in fig. 5.
Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program for instructing a terminal device to execute in association with hardware, the program may be stored in a computer readable storage medium, and the storage medium may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
The embodiment of the application also provides a storage medium. Alternatively, in the present embodiment, the above-described storage medium may be used for program code for executing a compression method of a circuit automatic test vector based on boolean satisfaction.
Alternatively, in this embodiment, the storage medium may be located on at least one network device of the plurality of network devices in the network shown in the above embodiment.
Alternatively, in the present embodiment, the storage medium is configured to store program code for performing the steps of:
acquiring an original test vector set and a test fault set of a target chip, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults;
Performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises the tested fault subset and an undetected fault subset, the tested fault subset is used for storing tested faults, and the undetected fault subset is used for storing undetected test faults;
Establishing a local fault dictionary by using the second test vector subset and the untested fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset;
and calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector.
Alternatively, specific examples in this embodiment may refer to examples described in the foregoing embodiments, and this embodiment is not described herein.
Alternatively, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The integrated units in the above embodiments may be stored in the above-described computer-readable storage medium if implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing one or more computer devices (which may be personal computers, servers or network devices, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In several embodiments provided by the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, such as the division of the units, is merely a logical function division, and may be implemented in another manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.
Claims (10)
1. A method for compressing a boolean satisfaction-based circuit automatic test vector, comprising:
acquiring an original test vector set and a test fault set of a target chip, wherein the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults;
Performing fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determining a tested fault subset of the test fault set, wherein the original test vector set comprises the first test vector subset and a second test vector subset, the test fault set comprises the tested fault subset and an undetected fault subset, the tested fault subset is used for storing tested faults, and the undetected fault subset is used for storing undetected test faults;
Establishing a local fault dictionary by using the second test vector subset and the untested fault subset, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset;
and calling Pure MaxSAT a problem solver to solve the local fault dictionary, so as to obtain a simplified test vector.
2. The method of claim 1, wherein performing fault simulation on all test faults in the test fault set using the first subset of test vectors of the original set of test vectors, determining a subset of tested faults of the test fault set comprises:
Dividing the original test vector set into a first test vector subset and a second test vector subset according to a preset proportion, wherein the number of test vectors in the second test vector subset is greater than that of the test vectors in the first test vector subset;
And carrying out fault simulation on all test faults in the test fault set by using the first test vector subset, and determining the tested fault subset.
3. The method of claim 1, wherein using the second subset of test vectors and the subset of unmeasured faults to build a local fault dictionary comprises:
performing fault simulation on test faults in the untested fault subset by using the test vectors in the second test vector subset to obtain the relation between each test vector and all test faults in the second test vector subset;
And establishing the local fault dictionary by utilizing the relation between each test vector and all test faults in the second test vector subset, wherein each row of the local fault dictionary corresponds to one test vector or test fault, each column corresponds to one test fault or test vector, elements crossing any row and column are used for representing the relation between the corresponding test vector and the corresponding test fault, the elements represent that the test vector can detect the test fault when the value of the elements is 1, and the elements represent that the test vector cannot detect the test fault when the value of the elements is 0.
4. The method of claim 1, wherein obtaining the original set of test vectors for the target chip comprises:
Before an automatic test vector generation (ATPG) tool is called to generate a test vector for the target chip, setting a test mode of the ATPG tool to be a specified test mode, wherein the specified test mode is used for indicating the number n of vectors required by one test fault, and the value of n is 2 or 3;
And calling the automatic test vector generation ATPG tool to generate the original test vector set for the target chip.
5. The method of claim 1, wherein invoking Pure MaxSAT a problem solver to solve the local fault dictionary results in a reduced test vector, comprising:
Processing the local fault dictionary to obtain a WCNF file to be input into a Pure MaxSAT problem solver, wherein the WCNF file is recorded with a data structure of the local fault dictionary;
And inputting the WCNF file into the Pure MaxSAT problem solver to solve the problem to obtain the simplified test vector.
6. The method of claim 5, wherein in inputting the WCNF file into the Pure MaxSAT problem solver for solving, the method further comprises:
Identifying a key vector in the WCNF file, wherein the key vector is a test vector which can only detect a certain test fault;
The key vectors are solved as vectors that must be preserved.
7. The method of any one of claims 1 to 6, wherein after invoking Pure MaxSAT a problem solver to solve the local fault dictionary to obtain a reduced test vector, the method further comprises:
And taking the obtained simplified test vectors of the second test vector subset and the first test vector subset as final test vectors of the target chip.
8. A boolean satisfaction-based compression device for automatic test vectors of circuits, comprising:
the device comprises an acquisition unit, a test fault detection unit and a test fault detection unit, wherein the acquisition unit is used for acquiring an original test vector set and a test fault set of a target chip, the original test vector set comprises a plurality of test vectors, and the test fault set comprises a plurality of test faults;
A determining unit, configured to perform fault simulation on all test faults in the test fault set by using a first test vector subset of the original test vector set, and determine a tested fault subset of the test fault set, where the original test vector set includes the first test vector subset and a second test vector subset, and the test fault set includes the tested fault subset and an untested fault subset, and the tested fault subset is used to store tested faults, and the untested fault subset is used to store untested test faults;
the creating unit is used for utilizing the second test vector subset and the untested fault subset to create a local fault dictionary, wherein the local fault dictionary is used for recording the association between the test vectors in the second test vector subset and the test faults in the untested fault subset;
and the compression unit is used for calling Pure MaxSAT a problem solver to solve the local fault dictionary so as to obtain a simplified test vector.
9. A storage medium comprising a stored program, wherein the program when run performs the method of any one of the preceding claims 1 to 7.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor performs the method of any of the preceding claims 1 to 7 by means of the computer program.
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