CN117954479A - Planar grid power device and manufacturing method thereof - Google Patents
Planar grid power device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 238000000926 separation method Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 163
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 210000000746 body region Anatomy 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
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- 230000015572 biosynthetic process Effects 0.000 claims 2
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- 238000010586 diagram Methods 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Abstract
The invention provides a planar gate power device and a manufacturing method thereof, wherein the method comprises the steps of providing a substrate, and manufacturing an epitaxial layer on the upper side of the substrate; forming a JFET region on the epitaxial layer; growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer; injecting the element of the first conductivity type into the polysilicon, performing well pushing operation, and then forming a polysilicon gate through an etching process; etching the middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer at the lower side of the polysilicon gate to form a separation groove, wherein the lower end of the separation groove is arranged in the JFET region; a dielectric layer is deposited within the separation trench and on top of the polysilicon gate and the exposed epitaxial layer. The invention optimizes the thickness of the oxide layer at the edge of the JFET region and the grid electrode, avoids the concentration of high electric field in the region, improves the withstand voltage, reduces the grid electrode charge Qg and the grid electrode Cgs, and greatly reduces the on-resistance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planar gate power device and a manufacturing method thereof.
Background
In a planar Metal Oxide Semiconductor (MOS) field effect transistor, in the off state, the voltage is blocked between the drain and source of the device by a reverse biased p-type body/n-epi junction. In the on state, current is conducted between the n+ source and the n-epi through the n-type channel. During switching, the n-epi under the gate is charged or discharged through the gate capacitance. Thus, the switching speed depends largely on the gate-n-epi overlap region.
Devices with different structures in the prior art all have certain defects, and the defects are as follows:
The gate-n-epi overlap area of conventional planar gate devices is large, although the distance between two adjacent p-type body regions can be reduced to reduce the gate capacitance and gate charge Qg. However, if they are too close to each other, a high resistance will be induced in the upper portion of the n-epi between two adjacent p-type body regions, which will induce a high on-resistance of the device.
Devices of a generally split gate structure have a higher switching speed than conventional planar gate devices. At the same time, the space between adjacent p-type body regions is not reduced to maintain substantially the same on-resistance. However, in the off state, the electric field may concentrate at the edge of the split gate-n-epi overlap region, causing premature breakdown of the device.
A device with an additional dummy gate connects the additional dummy gate to the source electrode. The virtual gate has the function of a field plate, and can optimize the electric field at the edge of the gate electrode in the off state. The problem of breakdown in advance is solved. However, the dummy gate creates additional capacitance at the sidewalls of the split gate, which can cause degradation of the switching speed compared to the device switching speed of a typical split gate structure.
Planar power MOSFET with split gate and semi-insulating field plates connected to source electrode at sidewalls. The device in the off state, the semi-insulating field plate may act like a dummy gate, and may also suppress high electric fields near the gate electrode and thus prevent premature breakdown. But the on-resistance of the JFET region is still large, affecting the switching speed and switching losses.
Disclosure of Invention
In view of the above, the present invention provides a planar gate power device and a method of manufacturing the same.
In order to solve the above technical problem, in a first aspect, the present invention provides a method for manufacturing a planar gate power device, including:
Providing a substrate of a first conductivity type, and manufacturing an epitaxial layer on the upper side of the substrate;
Forming a JFET region on the epitaxial layer through JFET injection and JFET push-well operation;
Growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer;
injecting the element of the first conductivity type into the polysilicon, performing well pushing operation, and then forming a polysilicon gate through an etching process;
injecting elements of a second conductivity type into the epitaxial layer which is not covered by the polycrystalline silicon grid electrode and the grid oxide layer to form a body region;
injecting an element of a first conductivity type into one side of the body region, which is close to the polysilicon gate, and forming a source region through a push-well operation;
etching the middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer at the lower side of the polysilicon gate to form a separation groove, wherein the lower end of the separation groove is arranged in the JFET region;
depositing a dielectric layer in the separation groove and on the upper sides of the polysilicon gate and the exposed epitaxial layer, and etching a connecting hole on the dielectric layer;
injecting elements of a second conductivity type into the epitaxial layer at the lower side of the connecting hole to form a deep source region;
And manufacturing a metal layer on the upper side of the dielectric layer and in the connecting hole, and etching the metal layer to form source electrode metal and gate electrode metal.
Furthermore, a gap is formed in the middle of the dielectric layer in the separation trench, so that the source metal is filled into the gap, and the lower end of the gap is arranged deep into the JFET region.
Further, the dielectric layer comprises a filling oxide layer and a dielectric oxide layer which are formed in sequence.
Furthermore, a silicon nitride or silicon oxynitride interlayer is arranged between the filling oxide layer and the dielectric oxide layer.
Further, the first conductivity type is N-type, and the second conductivity type is P-type.
In a second aspect, the invention provides a planar gate power device, which comprises a substrate of a first conductivity type, wherein an epitaxial layer is arranged on the upper side of the substrate, a JFET region is formed on the epitaxial layer through JFET injection and JFET push-well operation, a gate oxide layer is arranged on the upper side of the epitaxial layer, a polysilicon gate of the first conductivity type is arranged on the upper side of the gate oxide layer, a body region of a second conductivity type is arranged in the epitaxial layer, a source region of the first conductivity type is arranged on one side, close to the polysilicon gate, of the body region, a separation groove is formed by etching the gate oxide layer and the epitaxial layer on the middle part and the lower side of the polysilicon gate, the lower end of the separation groove is arranged in the JFET region, a medium layer is deposited on the upper side of the polysilicon gate and the exposed epitaxial layer, a connecting hole is formed by etching on the medium layer, a deep source region of the second conductivity type is arranged in the body region on the outer side of the source region, a metal layer is formed in the upper side of the medium layer and the connecting hole, and a metal layer is formed by etching the metal layer and gate metal is formed by etching the metal.
Furthermore, a gap is formed in the middle of the dielectric layer in the separation trench, so that the source metal is filled into the gap, and the lower end of the gap is arranged deep into the JFET region.
Further, the dielectric layer comprises a filling oxide layer and a dielectric oxide layer which are formed in sequence.
Furthermore, a silicon nitride or silicon oxynitride interlayer is arranged between the filling oxide layer and the dielectric oxide layer.
Further, the first conductivity type is N type, and the second conductivity type is P type
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the separation groove is formed by etching, the lower end of the separation groove is deep into the JFET region, the dielectric layer and the source metal are filled between the separated polysilicon grid electrodes, so that the field plate function can be realized, the grid electrodes and the drain electrodes are shielded, the thickness of the oxide layers at the edges of the JFET region and the grid electrodes is optimized, the high electric field concentration in the region is avoided, the voltage resistance is improved, the grid charges Qg and the grid electrodes Cgs are reduced, and the on-resistance is greatly reduced.
Drawings
FIG. 1 is a schematic illustration of polysilicon deposited on a gate oxide layer;
FIG. 2 is a schematic diagram of polysilicon gate after polysilicon is etched;
FIG. 3 is a schematic illustration of the body and source regions fabricated in the epitaxial layer;
FIG. 4 is a schematic illustration after etching separation trenches;
Fig. 5 is a schematic structural diagram of a planar gate power device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a dielectric layer of a planar gate power device with a filled oxide layer and a dielectric oxide layer;
FIG. 7 is a schematic diagram of a planar gate power device with an interlayer disposed between a filler oxide layer and a dielectric oxide layer;
Reference numerals illustrate: 1. a substrate; 2. an epitaxial layer; 3. a JFET region; 4. a gate oxide layer; 5. polycrystalline silicon; 6. a polysilicon gate; 7. a body region; 8. a source region; 9. separation grooves; 10. a dielectric layer; 101. filling an oxide layer; 102. a dielectric oxide layer; 103. an interlayer; 11. a deep source region; 12. source metal.
Detailed Description
The invention will be further illustrated by the following drawings and specific examples, which are carried out on the basis of the technical solutions of the invention, it being understood that these examples are only intended to illustrate the invention and are not intended to limit the scope of the invention.
The embodiment of the invention provides a manufacturing method of a planar gate power device, which comprises the following steps:
Referring to fig. 1, a substrate 1 of a first conductivity type is provided, and an epitaxial layer 2 is fabricated on an upper side of the substrate 1. The following will specifically describe an example in which the first conductivity type is N-type and the second conductivity type is N-type. The substrate 1 is generally N-type (100) crystal orientation doped with arsenic or antimony, and has a resistivity of typically less than 0.1 Ω. The resistivity and thickness of the epitaxial layer 2 are determined by the different device withstand voltages.
The JFET region 3 is formed on the epitaxial layer 2 by JFET implantation and JFET push-well operation. Specifically, the element implanted in the JFET implantation operation is preferably phosphorus, the implantation dosage is preferably 1E12-1E13atom/cm 3, and the implantation energy is preferably 60-150Kev. The temperature of the JFET push-well operation is 1050-1200 ℃ and the time is 50-150 minutes. The JFET region 3 formed may reduce the on-resistance of the device.
A gate oxide layer 4 is grown on the upper side of the epitaxial layer 2 and polysilicon 5 is deposited on the upper side of the gate oxide layer 4. The thickness of the gate oxide layer 4 is preferably 700 to 1500 angstroms and the thickness of the polysilicon 5 is preferably 6000 to 9000 angstroms.
The polysilicon 5 is implanted with an N-type element and subjected to a push-well operation, and then the polysilicon gate 6 is formed through an etching process. The element implanted into the polysilicon 5 is preferably phosphorus, the dose of implantation is preferably 1E15-3E15 atoms/cm 3, and the energy of implantation is preferably 40-60Kev. The temperature of the push-trap operation is preferably 800-1150 ℃ and the time is 10-20 seconds. In addition, when the polysilicon gate electrode 6 is formed by etching, the gate oxide layer 4 on the lower side of the etched polysilicon 5 is also etched, and the etched structure is shown in fig. 2.
Referring to fig. 3, an epitaxial layer 2, which is not covered by a polysilicon gate 6 and a gate oxide layer 4, is implanted with a P-type element to form a body region 7. Specifically, the element to be implanted is preferably boron, the implantation energy is preferably 60-120Kev, and the implantation dosage can be adjusted according to the requirement of VTH parameters, and is usually about 1E13-8E13 atoms/cm 3.
An N-type element is implanted at a side of the body region 7 near the polysilicon gate 6, and a source region 8 is formed by a push-well operation. Specifically, the element to be implanted is preferably phosphorus, the dose to be implanted is preferably 1E15-1E16atom/cm 3, and the energy to be implanted is preferably 50Kev-100Kev. The temperature of the push trap is preferably 900-950 ℃ and the time is preferably 25-50 minutes.
Referring to fig. 4, the gate oxide layer 4 and the epitaxial layer 2 in the middle of and under the polysilicon gate electrode 6 are etched to form a separation trench 9, and the lower end of the separation trench 9 is disposed in the JFET region 3.
A dielectric layer 10 is deposited in the separation trench 9 and on top of the polysilicon gate 6 and the exposed epitaxial layer 2 and a connection hole is etched in the dielectric layer 10.
P-type elements are implanted into the epitaxial layer 2 at the lower side of the connection hole to form a deep source region 11. Specifically, the element implanted here may be boron, and the dose implanted is preferably 1E15-3E15 atoms/cm 3, and the energy implanted is preferably 120-160Kev.
Referring to fig. 5 to 7, a metal layer is formed on the upper side of the dielectric layer 10 and in the connection hole, and the metal layer is etched to form a source metal 12 and a gate metal (not shown in the drawings), and the gate metal is connected to the polysilicon gate 6.
In addition, a passivation layer, preferably 7000-12000 angstrom thick silicon nitride, can be deposited on the upper side of the metal layer, and then etched to form Gate and Source opening regions, so that device leakage caused by movable ions on the chip surface can be reduced.
It is also possible to thin the substrate 1 from its underside to a residual thickness of about 200-300um and then evaporate the back gold layer, preferably a Ti-Ni-Ag (titanium-nickel-silver) layer, on the underside of the substrate 1.
Referring to fig. 6 and 7, the dielectric layer 10 may fill the inside of the separation trench 9, and a portion of the dielectric layer 10 that is deep into the JFET region 3 may serve as a field plate. Referring to fig. 5, it is more preferable that a gap is formed in the middle of the dielectric layer 10 in the isolation trench 9, so that the source metal 12 fills the gap, and the lower end of the gap is disposed deep into the JFET region 3, so that the source metal 12 is deep into the JFET region 3, and the deep source metal 12 can not only serve as a field plate, but also assist in depletion, and reduce the surface electric field.
Referring to fig. 6, in order to improve reliability, the dielectric layer 10 includes a filling oxide layer 101 and a dielectric oxide layer 102 sequentially formed. The filler oxide layer 101 and the dielectric oxide layer 102 are both preferably silicon dioxide. Referring to fig. 7, a silicon nitride or silicon oxynitride interlayer 103 is also preferably provided between the fill oxide layer 101 and the dielectric oxide layer 102.
As can be easily understood by those skilled in the art in combination with fig. 1 to 7, the present invention further provides a planar gate power device, which includes a substrate 1 of a first conductivity type, and an epitaxial layer 2 is disposed on an upper side of the substrate 1. The following will specifically describe an example in which the first conductivity type is N-type and the second conductivity type is N-type. The substrate 1 is generally N-type (100) crystal orientation doped with arsenic or antimony, and has a resistivity of typically less than 0.1 Ω. The resistivity and thickness of the epitaxial layer 2 are determined by the different device withstand voltages.
The JFET region 3 is formed on the epitaxial layer 2 through JFET injection and JFET push-well operation. Specifically, the element implanted in the JFET implantation operation is preferably phosphorus, the implantation dosage is preferably 1E12-1E13atom/cm 3, and the implantation energy is preferably 60-150Kev. The temperature of the JFET push-well operation is 1050-1200 ℃ and the time is 50-150 minutes. The JFET region 3 formed may reduce the on-resistance of the device.
The upper side of the epitaxial layer 2 is provided with a gate oxide layer 4, the thickness of the gate oxide layer 4 is preferably 700-1500 angstroms, the upper side of the gate oxide layer 4 is provided with an N-type polycrystalline silicon gate electrode 6, the polycrystalline silicon gate electrode 6 is formed by depositing polycrystalline silicon 5 on the upper side of the gate oxide layer 4, injecting N-type elements into the polycrystalline silicon 5, then performing a push-well operation and an etching process, the thickness of the polycrystalline silicon 5 is preferably 6000-9000 angstroms, the injected elements into the polycrystalline silicon 5 are preferably phosphorus, the injected dose is preferably 1E15-3E15 atoms/cm 3, and the injected energy is preferably 40-60Kev. The temperature of the push-trap operation is preferably 800-1150 ℃ and the time is 10-20 seconds. In addition, when the polysilicon gate electrode 6 is formed by etching, the gate oxide layer 4 on the lower side of the etched polysilicon 5 is also etched, and the etched structure is shown in fig. 2.
A P-type body region 7 is provided in the epitaxial layer 2, specifically, the body region 7 is formed by implanting a P-type element into the epitaxial layer 2 without the polysilicon gate electrode 6 and the gate oxide layer 4, wherein the implanted element is preferably boron, the implantation energy is preferably 60-120Kev, the implantation dose can be adjusted according to the requirement of VTH parameters, and generally about 1E13-8E13atom/cm 3.
A source region 8 of the first conductivity type is provided on the body region 7 on the side close to the polysilicon gate 6, and specifically, the source region 8 is formed by implanting an element of the N type, preferably phosphorus, at a dose of preferably 1E15-1E16 atoms/cm 3, and an energy of preferably 50Kev-100Kev, and by performing a push-well operation. The temperature of the push trap is preferably 900-950 ℃ and the time is preferably 25-50 minutes.
The middle part of the polysilicon gate 6 and the gate oxide layer 4 and the epitaxial layer 2 at the lower side thereof are etched to form a separation trench 9, the lower end of the separation trench 9 is arranged in the JFET region 3, a dielectric layer 10 is deposited in the separation trench 9 and on the upper sides of the polysilicon gate 6 and the exposed epitaxial layer 2, a connecting hole is etched on the dielectric layer 10, a P-type deep source region 11 is arranged in a body region 7 at the outer side of the source region 8, specifically, the deep source region 11 is formed by injecting a P-type element into the epitaxial layer 2 at the lower side of the connecting hole, the injected element can be boron, the injected dose is preferably 1E15-3E15 atoms/cm 3, and the injected energy is preferably 120-160Kev.
A metal layer is formed on the dielectric layer 10 and in the connection hole, and the metal layer is etched to form a source metal 12 and a gate metal (not shown in the figure), and the gate metal is connected to the polysilicon gate 6.
In addition, a passivation layer, preferably 7000-12000 angstrom thick silicon nitride, can be deposited on the upper side of the metal layer, and then etched to form Gate and Source opening regions, so that device leakage caused by movable ions on the chip surface can be reduced.
It is also possible to thin the substrate 1 from its underside to a residual thickness of about 200-300um and then evaporate the back gold layer, preferably a Ti-Ni-Ag (titanium-nickel-silver) layer, on the underside of the substrate 1.
Referring to fig. 6 and 7, the dielectric layer 10 may fill the inside of the separation trench 9, and a portion of the dielectric layer 10 that is deep into the JFET region 3 may serve as a field plate. Referring to fig. 5, it is more preferable that a gap is formed in the middle of the dielectric layer 10 in the isolation trench 9, so that the source metal 12 fills the gap, and the lower end of the gap is disposed deep into the JFET region 3, so that the source metal 12 is deep into the JFET region 3, and the deep source metal 12 can not only serve as a field plate, but also assist in depletion, and reduce the surface electric field.
Referring to fig. 6, in order to improve reliability, the dielectric layer 10 includes a filling oxide layer 101 and a dielectric oxide layer 102 sequentially formed. The filler oxide layer 101 and the dielectric oxide layer 102 are both preferably silicon dioxide. Referring to fig. 7, a silicon nitride or silicon oxynitride interlayer 103 is also preferably provided between the fill oxide layer 101 and the dielectric oxide layer 102.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to a person of ordinary skill in the art. Modifications and alterations may be made without departing from the principles of this invention, and such modifications and alterations should also be considered as being within the scope of the invention.
Claims (10)
1. A method of fabricating a planar gate power device, comprising:
Providing a substrate of a first conductivity type, and manufacturing an epitaxial layer on the upper side of the substrate;
Forming a JFET region on the epitaxial layer through JFET injection and JFET push-well operation;
Growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer;
injecting the element of the first conductivity type into the polysilicon, performing well pushing operation, and then forming a polysilicon gate through an etching process;
injecting elements of a second conductivity type into the epitaxial layer which is not covered by the polycrystalline silicon grid electrode and the grid oxide layer to form a body region;
injecting an element of a first conductivity type into one side of the body region, which is close to the polysilicon gate, and forming a source region through a push-well operation;
etching the middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer at the lower side of the polysilicon gate to form a separation groove, wherein the lower end of the separation groove is arranged in the JFET region;
depositing a dielectric layer in the separation groove and on the upper sides of the polysilicon gate and the exposed epitaxial layer, and etching a connecting hole on the dielectric layer;
injecting elements of a second conductivity type into the epitaxial layer at the lower side of the connecting hole to form a deep source region;
And manufacturing a metal layer on the upper side of the dielectric layer and in the connecting hole, and etching the metal layer to form source electrode metal and gate electrode metal.
2. The method of claim 1, wherein a gap is provided in the middle of the dielectric layer in the separation trench, so that the source metal fills the gap, and the lower end of the gap is disposed deep into the JFET region.
3. The method of manufacturing a planar gate power device of claim 1, wherein the dielectric layer comprises a fill oxide layer and a dielectric oxide layer formed sequentially.
4. The method of manufacturing a planar gate power device of claim 3, further comprising providing a silicon nitride or silicon oxynitride interlayer between the filler oxide layer and the dielectric oxide layer.
5. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
6. The utility model provides a planar gate power device, its characterized in that includes the substrate of first conductivity type, the upside of substrate is equipped with the epitaxial layer, it forms the JFET district to go up to inject through JFET and JFET pushes away the trap operation preparation on the epitaxial layer, the upside of epitaxial layer is equipped with the gate oxide, the upside of gate oxide is equipped with the polycrystalline silicon grid of first conductivity type, be equipped with the body district of second conductivity type in the epitaxial layer, the body district is close to one side of polycrystalline silicon grid and is equipped with the source district of first conductivity type, the middle part of polycrystalline silicon grid and gate oxide and the epitaxial layer of downside are through the etching formation separation slot, the lower extreme setting of separation slot is in the JFET district, separate the inslot and the polycrystalline silicon grid and the epitaxial layer upside that exposes deposit there is the dielectric layer, the etching forms the connecting hole on the dielectric layer, be equipped with the source district of second conductivity type in the body district outside, the upside and the connecting hole metal layer in the preparation metal layer is through the etching formation source metal and gate metal.
7. The planar gate power device of claim 6, wherein a gap is provided in the middle of the dielectric layer in the separation trench to fill the source metal into the gap, and a lower end of the gap is disposed deep into the JFET region.
8. The planar gate power device of claim 6, wherein the dielectric layer comprises a fill oxide layer and a dielectric oxide layer formed sequentially.
9. The planar gate power device of claim 8, wherein a silicon nitride or silicon oxynitride interlayer is further disposed between the filler oxide layer and the dielectric oxide layer.
10. The planar gate power device of claim 6, wherein the first conductivity type is N-type and the second conductivity type is P-type.
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