CN117954411A - Flat type packaging structure supporting double-sided pins and process - Google Patents

Abstract

The invention relates to a flat type packaging structure supporting double-sided pins and a process thereof, comprising an anisotropic single-row pin, an anisotropic double-row staggered pin, an anisotropic double-row symmetrical pin structure and a corresponding pin processing process. The different-direction single-row pin structure adopts single-row pins, single-side pins are arranged in a straight line, opposite-side pins of the packaging structure are opposite in direction, and a round identifier is used for pin identification guidance in the upper left corner of the packaging structure; the structure of the different-direction double-row staggered pins adopts double-row pins, single-side pins are arranged in a straight line, adjacent pins are opposite in direction, and the upper left corner of the packaging structure uses a half-notch identifier to conduct pin identification guidance. Compared with the traditional technology, the invention can increase the pin density by one time under the condition of nearly the same cost, or can save half of the volume space under the condition of the same pin density, thereby improving the flexibility of the chip. The great increase of the pin density enables the chip to realize more data transmission in the same time period, thereby increasing the data transmission rate.

Description

Flat type packaging structure supporting double-sided pins and process

Technical Field

The invention relates to the technical field of integrated circuit packaging, in particular to a flat packaging structure supporting double-sided pins and a process.

Background

With the rapid development of electronic technology and the continuous expansion of product functions, the requirement on the integration scale of chips is higher and higher, so that the requirement on packaging technology is higher and higher. The packaging is mainly completed in the subsequent engineering of semiconductor manufacture, namely, the technology of arranging, fixing and connecting the semiconductor components and other components on a frame or a substrate by utilizing a film technology and a micro-connection technology, leading out wiring terminals, and encapsulating and fixing the wiring terminals through plastic insulating media to form an integral main body structure. The most basic function of the package is to protect the circuit chip from the surrounding environment (including physical, chemical). In the original microelectronic package, a metal can was used as a housing, and a completely airtight method was used to protect fragile electronic components from the outside. However, with the development of integrated circuit technology, the functions of the package are also gradually changed, and the most important function of the package at the present stage is the function of maintaining the electrical characteristics of the chip.

The major packaging technologies are still single sided packages such as Small Out-LINE PACKAGE, SOP, quad flat package (Quad FLAT PACKAGE, QFP). The SOP structure starts at the end of the 70 s and is a component packaging form, and common packaging materials include: plastic, ceramic, glass, metal, etc., basically adopts plastic packaging, has a wide application range, is mainly applied to various integrated circuits, and gradually derives a J-pin Small Outline Package (Small Out-Line J-LEADED PACKAGE, SOJ), a reduced Outline Package (SHRINK SMALL Outline Package, SSOP), a thin reduced Outline Package (THIN SHRINK SMALL Outline Package, TSSOP), a Small Outline transistor (Small Outline Transistor, SOT), a Small Outline integrated circuit (Small Outline Integrated Circuit, SOIC), etc. all play a role in the integrated circuits.

The square flat package technology has small distance between chip pins, fine pins and is used in large-scale or very large-scale integrated circuit, and the pin number is over 100. Common square flat package sizes are typically expressed in mm, with common square flat package external dimensions of 7mm by 7mm,14x14mm, or 20x20mm, etc. The number of pins of square flat packages can vary from tens to hundreds, with common numbers of pins being 32, 48, 64, 100, 144, 208, etc. Pitch refers to the center distance between adjacent pins, typically expressed in millimeters, with typical pin pitches of 0.4mm, 0.5mm, 0.65mm, 0.8mm, etc. However, for the single-sided package structure, the density of package pins is low, so that the size and the pin number of the package are limited, and the requirement of higher and higher integration of chips is difficult to meet.

In order to solve the problems, the invention designs a square flat package-based structure, and corresponding pin processing equipment and process. The structure is characterized in that fixed homodromous pins on one side of a chip are converted into different-directional pins, and meanwhile, the fixed homodromous pins are divided into three specific patterns under one structure according to the distribution mode of the pins. The structure can improve the system integration level and the packaging density, and simultaneously improve the data transmission rate of the chip and further optimize the heat dissipation performance. Meanwhile, the pin processing equipment is designed, more than three types of pins can be processed by one piece of equipment, and the processing technology related to the pin processing equipment is designed.

Disclosure of Invention

Aiming at the problems in the prior art, the application provides a QFP packaging structure supporting double-sided pins, wherein the packaging structure comprises an anisotropic single-row pin, an anisotropic double-row staggered pin or an anisotropic double-row symmetrical pin structure; the two sides of the different-direction single-row pin structure adopt single-row pins which are arranged in a straight line, the extending directions of the single-row pins at the two sides are opposite, and the upper left corner of the packaging structure uses a circular identifier to conduct pin identification guidance; the structure of the anisotropic double-row staggered pins adopts double-row pins, each row of pins are in linear arrangement, the extending directions of adjacent pins are opposite, and the upper left corner of the packaging structure uses a half-notch identifier to conduct pin identification guidance; the structure of the different-direction double-row symmetrical pins adopts double-row pins, the double-row pins are symmetrically arranged, the directions of the transverse adjacent pins are the same, the directions of the vertical adjacent pins are opposite, and the left upper corner of the front surface of the packaging structure uses a half-notch identifier to conduct pin identification guidance.

Preferably, the pin ends are located at the bottom or top of the chip.

Preferably, the pins are made of Cu-Ag alloy, and the root parts and the tail ends of the pins are made of AgCu50 alloy materials; the pin bending part is made of AgCu5 alloy material.

Preferably, the alloy thicknesses of the root portion of the pin, the tail end of the pin and the bending part of the pin are different, the thickness of the root portion of the pin is larger than the thickness of the tail end of the pin, and the thickness of the tail end of the pin is larger than the thickness of the bending part of the pin.

Preferably, the tail ends of the pins are horizontally arranged, the pins are bent in a clamping and pressing mode, and the tail ends of the pins are stress points of the clamping and pressing.

A QFP packaging process supporting double-sided pins comprises the following steps:

step S1: designing the chip position and pin layout, and simultaneously cutting out grains before the chip is not packaged from the wafer;

step S2: designing a pin connection direction corresponding to the chip position;

Step S3: bonding the crystal grains before the chip is not packaged on a substrate by silver paste and heating and fixing;

step S4: using a glue dropping machine to drop conductive glue at the pins of the chip, and simultaneously coating a layer of conductive glue at the welding points of the gold wires;

Step S5: transmitting an electric signal by using a gold wire, and connecting pins of the chip with pins on the substrate by using a micro wire bonding machine;

Step S6: placing the chip and the substrate into a packaging mold, curing the packaging epoxy resin to form a final packaging shell, and marking a round or half-notch identifier by using laser etching;

step S7: clamping and pressing the pin structure;

Step S8: when the double-sided packaging technology is adopted for multi-chip connection, after the single chip is processed, a plurality of chips are connected in sequence according to a preset sequence, and a silicon substrate is used for welding and fixing;

step S9: after all the functional chips are connected and detected without errors, placing the functional chips into a die, and adding epoxy resin again for packaging and fixing;

step S10: the quality and reliability of the weld is ensured by X-ray detection.

The above technical features can be adapted and applied to different chip package sizes and pin counts, as long as the objects of the present invention can be achieved.

Compared with the prior art, the square flat double-sided packaging structure, the pin processing mode and the corresponding packaging structure design flow provided by the invention have at least the following beneficial effects:

Aiming at the problem that pins of a chip are usually connected in one way (namely, each pin can only transmit signals or power supply) in the traditional packaging technology, the designed double-sided packaging technology realizes the two-way connection of the pins by arranging the pins at the bottom and the top of the chip respectively, expands components from two-dimensional directions to three-dimensional structures, and develops and designs corresponding pin processing technologies. Compared with the traditional technology, the double-sided packaging technology can simultaneously transmit signals and power, so that the pin density can be doubled under the condition of approaching the same cost, or the volume space can be saved by half under the condition of the same pin density, and the flexibility of a chip is improved. The great increase of the pin density can enable the chip to realize more data transmission in the same time period, thereby improving the data transmission rate. In addition, the invention can optimize heat dissipation performance and simplify complexity of design and layout and wiring. The packaging effect is applicable to customized circuits and printed circuit boards (Printed Circuit Board, PCBs) with special structures in application scenes.

Drawings

The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:

FIG. 1 shows a square flat double-sided package structure A-a single-row anisotropic pin designed by the invention;

FIG. 2 shows a square flat double-sided package structure B-an anisotropic double-row staggered pin designed by the invention;

FIG. 3 shows a square flat double-sided package structure C-an anisotropic double-row symmetrical pin designed by the invention;

FIG. 4 is a top view of an anisotropic single row pin configuration of the present invention;

FIG. 5 shows a top view of an anisotropic double-row symmetrical pin configuration of the present invention;

FIG. 6 shows a side view of a pin processing apparatus machine tool of the present invention;

FIG. 7 is a flow chart of the packaging and pin processing process of the present invention;

FIG. 8 is a schematic diagram of gold wire connection pins in the packaging process of the present invention;

FIG. 9 is a schematic diagram showing the pin impact molding in the pin processing flow of the present invention;

fig. 10 shows a spatial structure of a multi-layered stacked chip;

Fig. 11 shows a schematic diagram of pin connection of a multi-layer stacked chip.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

The invention designs a double-sided packaging structure aiming at the problem that the pins of a chip in the traditional packaging technology are usually connected in one way, namely each pin can only transmit signals or power supply. The double-sided packaging structure realizes the bidirectional connection of the pins and the double-sided assembly of the chip and the device by arranging the pins at the bottom and the top of the chip respectively, improves the flexibility of the chip, saves the number of the pins, and simplifies the complexity of design and wiring. Meanwhile, the double-sided packaging structure can also realize high-density packaging of chips and improvement of data transmission rate, and optimize heat dissipation performance. The method is suitable for the fields of mobile communication, internet of things, intelligent home, automobile electronics, high-performance computing, artificial intelligence and the like, and provides higher performance and function integration.

The core principle of the double-sided packaging structure is that three specific types are designed for redesigning the arrangement of pins, namely a different-direction single-row pin, a different-direction double-row staggered pin and a different-direction double-row symmetrical pin structure.

In one embodiment, as shown in fig. 1, the invention provides a packaging mode of an anisotropic single-row pin, the structure of which is shown in fig. 1 in a simple side view, the structure of which is shown in fig. 4 in a top view, the packaging mode comprises a packaging shell, upward pins, downward pins and circular identifiers, the pins on one side are arranged in a straight line, the pins on the opposite side of the packaging structure are opposite in direction, and the circular identifiers are used for pin identification guidance on the upper left corner of the packaging structure.

In one embodiment, a packaging mode of a single-row of pins in different directions is adopted, a square chip with the packaging size of 7mm x 7mm is packaged, the number of pins is 8 pins on one side, 32 pins are all arranged on the other side, and the single side is in linear arrangement. The requirements for the specification are as follows: the width of the pins is 0.4mm, the pitch of the pins is 0.8mm (the center distance of adjacent pins), the distance between the edge pins and the frame is 0.3mm, and the length of the exposed pins is 1mm after stamping forming. The identification method of the pins is that the circular identifier is oriented towards the upper left corner, and is incremented by number ① anticlockwise.

In one embodiment, as shown in fig. 2, the invention provides a packaging mode of anisotropic double-row staggered pins, the simple side view of the structure is shown in fig. 2, the pins on one side are arranged in a straight line, the directions of adjacent pins are opposite, and the upper left corner of a packaging unit uses a half-notch identifier to conduct pin identification guidance.

In one embodiment, a packaging mode of opposite double-row staggered pins is adopted, the packaging size is 7mm square chips with 7mm square pins, the number of the pins is 8 pins on one side, 32 pins are arranged on the other side in a straight line, adjacent pins are oriented differently (for example, ① pins are oriented upwards, ② pins are oriented downwards, ③ pins are oriented upwards), the pin width is 0.4mm, the pin spacing is 0.8mm (the center distance between adjacent pins), the distance between an edge pin and a frame is 0.3mm, and the exposed pin length is 1mm after clamping and press molding. The identification method of the pin is that of the left upper corner half notch, and the numbering mode is that the anticlockwise increment is carried out by the number ①.

In one embodiment, as shown in fig. 3, the invention provides a packaging mode of anisotropic double-row symmetrical pins, the structure of which is shown in fig. 3 as a simple side view, and the structure of which is shown in fig. 5 as a top view, wherein the packaging mode comprises a packaging shell, upward pins, downward pins and half-notch identifiers, the pins on one side are arranged in a straight line symmetrical manner, the pins on the other side are oriented in the same direction, the pins on the other side are oriented in opposite directions vertically, and the left upper corner of the front face of a packaging unit uses the half-notch identifiers to conduct pin identification guidance.

In one embodiment, a packaging mode of opposite double-row symmetrical pins is adopted, a square chip with the packaging size of 7mm is packaged, the number of pins is 16 pins on one side (8 pins face upwards and 8 pins face downwards), 64 pins are arranged on the other side in a straight line symmetrical mode, the directions of the adjacent pins are the same in the horizontal direction, the directions of the adjacent pins are opposite in the vertical direction, the widths of the pins are 0.4mm, the pin spacing is 0.8mm (the center distance of the adjacent pins), and the distance between the edge pins and the frame is 0.3mm. After stamping forming, the exposed pins were 1mm in length. The pin identification method is as follows, half notch identification Fu Chao is toward the top left front, and the counter-clockwise label is incremented by number ①.

In one embodiment, the root parts and the bending parts of the pins are made of Cu-Ag alloy, the root parts of the pins are made of AgCu50 alloy material, and the hardness is about 125 HV; the AgCu5 alloy material is adopted for the pin bending part, the hardness is about 95HV, and the pin bending part is easier to form in the pin processing process due to the difference of the hardness, and meanwhile, the root of the pin is still kept in the original state without being affected by the processing.

In one embodiment, the alloy thickness of the root part of the pin is different from that of the bending part of the pin, and the root part of the pin is made of an alloy material with the thickness of 1 mm; the pin bending part adopts alloy material with thickness of 0.6mm, and because of thickness difference, in the pin processing process, the pin bending part is more easily processed into "J" shape, and the pin root is difficult to be damaged by processing.

The invention provides a pin processing mode corresponding to the packaging structure and corresponding pin processing equipment, and fig. 6 shows a machine tool side view of the pin processing equipment.

In one embodiment, a square, 32 pin chip with a package size of 7mm is leaded using a lead tooling apparatus. During processing, the fixing device is used for fixing the packaged chip in the middle, the clamping tools are used for processing by the machine tool on four sides, and the machine tool simultaneously controls the clamping tools with the same number as that of the single-side pins of the chip to perform operation, namely 8 clamping tools are operated at a time (the number of the single-side pins is 8 pins).

The invention also relates to a design work flow of the packaging structure, and FIG. 7 shows an overall flow chart, comprising wafer cutting, packaging frame, conductive adhesive covering, gold wire welding, packaging solidification and impact pin forming; fig. 8 shows a schematic diagram of a gold wire connection pin during processing, and fig. 9 shows pin impact molding during pin processing.

In one embodiment, the chip is packaged and leaded by the steps of:

step S1, cutting a wafer: designing the chip position and pin layout, and simultaneously cutting out grains before the chip is not packaged from the wafer;

step S2, designing a pin direction: designing a pin connection direction corresponding to the chip position;

step S3, packaging a frame: bonding the crystal grains before the chip is not packaged on a substrate by silver paste and heating and fixing;

Step S4, covering with conductive adhesive: using a glue dropping machine to drop conductive glue at the pins of the chip, and simultaneously coating a layer of conductive glue at the welding points of the gold wires;

step S5, gold wire welding: transmitting an electric signal by using a gold wire, and connecting pins of the chip with pins on the substrate by using a micro wire bonding machine;

step S6, packaging and solidifying: placing the chip and the substrate into a packaging mold, curing the packaging epoxy resin to form a final packaging shell, and marking a round or half-notch identifier by using laser etching;

step S7, impact pin forming: stamping the pin structure;

step S8, welding and fixing: when the double-sided packaging technology is adopted for multi-chip connection, after the single chip is processed, a plurality of chips are connected in sequence according to a preset sequence, and a silicon substrate is used for welding and fixing;

Step S9, packaging and fixing: after all the functional chips are connected and detected without errors, placing the functional chips into a die, and adding epoxy resin again for packaging and fixing;

step S10, quality detection: the quality and reliability of the weld is ensured by X-ray detection.

In one embodiment, a chip is packaged, and the required packaging structure is a single-row of pins in different directions. The processing is carried out by adopting the processing technological process, and the gold thread is connected with the pins to provide signal and power transmission channels. When the pin processing equipment is adopted for pin processing, the pin clamping and pressing can be completed only once.

In one embodiment, a chip is packaged, and the required packaging structure is an anisotropic double-row staggered pin. The processing is carried out by adopting the processing technological process, and the gold thread is connected with the pins to provide signal and power transmission channels. When the pin processing equipment is adopted for pin processing, the pin clamping and pressing can be completed only once.

In one embodiment, a chip is packaged, and the required packaging structure is an anisotropic double-row symmetrical pin. The processing is carried out by adopting the processing technological process, and the gold thread is connected with the pins to provide signal and power transmission channels. When the pin processing equipment is adopted for pin processing, two times of clamping are needed to be respectively carried out, and the clamping sequence defaults to downward clamping and then upward clamping.

The packaging structure, the pin processing mode, the pin processing equipment and the packaging process flow designed by the invention have various application scenes. In some special packaging scenes, the packaging form can reduce packaging cost, packaging volume and layout wiring complexity.

In one embodiment, the chips form a spatial structure as shown in fig. 10, which has the advantage of achieving more functional integration and performance improvement in a limited space. As shown in fig. 11, in the multi-layer stack, adjacent chips are connected by pins of each direction (up or down) in the vertical direction. The pins penetrate through the silicon substrate of the chip and are connected with the upper chip and the lower chip, so that signal transmission and power supply between the chips are realized.

In order to realize more pin connection in a limited space, thereby improving the packaging density and the chip integration effect, the invention designs a square flat double-sided packaging structure and three packaging forms under the structure, including an anisotropic single-row pin, an anisotropic double-row staggered pin, an anisotropic double-row symmetrical pin structure and a corresponding pin processing technology. The invention designs the pins of the chip package into two-way connection, expands the components from two-dimensional directions to three-dimensional structures, and simultaneously develops and designs corresponding pin processing devices. Compared with the traditional packaging technology, the invention has the advantages of low cost, high pin density, small volume, high transmission rate and the like. The packaging effect can be suitable for customized circuits and special-shaped structure PCBs in application scenes.

Claims (6)

1. The flat packaging structure supporting double-sided pins is characterized by comprising an anisotropic single-row pin, an anisotropic double-row staggered pin or an anisotropic double-row symmetrical pin structure; the two sides of the different-direction single-row pin structure adopt single-row pins which are arranged in a straight line, the extending directions of the single-row pins at the two sides are opposite, and the upper left corner of the packaging structure uses a circular identifier to conduct pin identification guidance; the structure of the anisotropic double-row staggered pins adopts double-row pins, each row of pins are in linear arrangement, the extending directions of adjacent pins are opposite, and the upper left corner of the packaging structure uses a half-notch identifier to conduct pin identification guidance; the structure of the different-direction double-row symmetrical pins adopts double-row pins, the double-row pins are symmetrically arranged, the directions of the transverse adjacent pins are the same, the directions of the vertical adjacent pins are opposite, and the left upper corner of the front surface of the packaging structure uses a half-notch identifier to conduct pin identification guidance.

2. The dual sided leaded flat package structure of claim 1, wherein the terminal ends of the leads are located at the bottom or top of the chip.

3. The flat package structure supporting double-sided pins according to claim 1, wherein the pins are made of Cu-Ag alloy, and the root portions and the end portions of the pins are made of AgCu50 alloy material; the pin bending part is made of AgCu5 alloy material.

4. The flat package structure supporting dual sided leads of claim 1, wherein the alloy thickness of the lead root, the lead end and the lead bend is different, the thickness of the lead root is greater than the thickness of the lead end, and the thickness of the lead end is greater than the thickness of the lead bend.

5. The flat package structure supporting double-sided pins as claimed in claim 1, wherein the ends of the pins are horizontally arranged, the pins are bent by means of clamping and pressing, and the ends of the pins are stress points of clamping and pressing.

6. The process of supporting a flat package structure with dual sided leads as recited in claim 1, comprising the steps of:

step S1: designing the chip position and pin layout, and simultaneously cutting out grains before the chip is not packaged from the wafer;

step S2: designing a pin connection direction corresponding to the chip position;

Step S3: bonding the crystal grains before the chip is not packaged on a substrate by silver paste and heating and fixing;

step S4: using a glue dropping machine to drop conductive glue at the pins of the chip, and simultaneously coating a layer of conductive glue at the welding points of the gold wires;

Step S5: transmitting an electric signal by using a gold wire, and connecting pins of the chip with pins on the substrate by using a micro wire bonding machine;

Step S6: placing the chip and the substrate into a packaging mold, curing the packaging epoxy resin to form a final packaging shell, and marking a round or half-notch identifier by using laser etching;

step S7: clamping and pressing the pin structure;

step S8: when the double-sided packaging technology is adopted for multi-chip connection, after the single chip is processed, a plurality of chips are connected in sequence according to a preset sequence, and the silicon substrate is used for welding and fixing;

step S9: after all the functional chips are connected and detected without errors, placing the functional chips into a die, and adding epoxy resin again for packaging and fixing;

step S10: the quality and reliability of the weld is ensured by X-ray detection.