CN117954328A - Packaging structure and manufacturing method thereof - Google Patents
Packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN117954328A CN117954328A CN202211293331.XA CN202211293331A CN117954328A CN 117954328 A CN117954328 A CN 117954328A CN 202211293331 A CN202211293331 A CN 202211293331A CN 117954328 A CN117954328 A CN 117954328A
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- insulator
- substrate
- insulating layer
- conductive
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 112
- 239000012212 insulator Substances 0.000 claims abstract description 81
- 229910000679 solder Inorganic materials 0.000 claims abstract description 61
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 230000008018 melting Effects 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 18
- 238000005476 soldering Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 4
- -1 polyethylene terephthalate Polymers 0.000 description 4
- 239000004721 Polyphenylene oxide Substances 0.000 description 3
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 3
- 239000011112 polyethylene naphthalate Substances 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 229920006380 polyphenylene oxide Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 210000001503 joint Anatomy 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a manufacturing method of a packaging structure, which comprises the following steps: providing a circuit substrate, wherein the circuit substrate comprises a first insulator and a first conductor arranged in the first insulator; removing part of the first insulator, so that part of the first conductor protrudes out of the surface of the rest first insulator, and forming a containing space by surrounding part of the first conductor and the first insulator; arranging a first solder ball on the surface of the first conducting body, which is away from the first insulator, so as to obtain a first packaging substrate; providing a packaging piece, wherein the packaging piece comprises a second packaging substrate and an electronic element arranged on one side of the second packaging substrate; the first solder balls are in contact with the second packaging substrate, and at least part of the electronic elements are accommodated in the accommodating space; and heating and melting the first solder balls, wherein the first packaging substrate is electrically connected with the second packaging substrate. The application also provides a packaging structure.
Description
Technical Field
The application relates to the technical field of electronic element packaging, in particular to a packaging structure and a manufacturing method thereof.
Background
The conventional POP (package on package ) packaging process is to form a raised copper pillar on the surface of the first package substrate as a solder joint to bond with the second package substrate. At present, copper pillars are formed on the surface of the first package substrate by using a common electroplating method, and the heights of the electroplated copper pillars are uneven due to uneven current density during electroplating, so that poor loading is easily caused. And the binding force between the electroplated copper column and the connecting pad on the second packaging substrate is poor, so that the electroplated copper column is easy to fall off in the subsequent processing process, and the reliability is reduced.
Disclosure of Invention
In order to solve the problems in the background technology, the application provides a manufacturing method of a packaging structure.
In addition, it is also necessary to provide a package structure manufactured by the manufacturing method.
The application provides a manufacturing method of a packaging structure, which comprises the following steps:
providing a circuit substrate, wherein the circuit substrate comprises a first insulator and a first conductor arranged in the first insulator;
removing part of the first insulator, so that part of the first conductor protrudes out of the surface of the rest first insulator, and the protruding part of the first conductor and the first insulator enclose to form a containing space;
arranging a first solder ball on the surface of the first conducting body, which is away from the first insulator, so as to obtain a first packaging substrate;
Arranging a packaging piece on the first packaging substrate, wherein the packaging piece comprises a second packaging substrate and an electronic element arranged on one side of the second packaging substrate; the first solder balls are in contact with the second packaging substrate, and at least part of the electronic elements are accommodated in the accommodating space;
and heating and melting the first solder balls, and electrically connecting the first conducting body and the second packaging substrate by the cooled and solidified first solder balls to obtain the packaging structure.
Further, the step of "removing a portion of the first insulator" includes: a portion of the first insulator is removed using a plasma desmear process.
Further, the circuit substrate further comprises two inner circuit layers arranged in the first insulator at intervals and a first outer circuit layer arranged at one side of the first insulator, the first insulator comprises a first insulating layer, a second insulating layer and a third insulating layer along the thickness direction, the first insulating layer is arranged at one side of one inner circuit layer, the second insulating layer is arranged between the two inner circuit layers, and the third insulating layer is arranged between the first outer circuit layer and the other inner circuit layer;
The step of "removing a portion of the first insulator" includes:
and removing part of the first insulating layer.
Further, the first conductive body includes a first conductive post penetrating through the first insulating layer, a second conductive post disposed in the second insulating layer, and a third conductive post disposed in the third insulating layer, wherein the first conductive post is disposed on one side of one of the inner circuit layers along the thickness direction, the second conductive post is connected between the two inner circuit layers along the thickness direction, and the third conductive post is disposed between the first outer circuit layer and the other inner circuit layer along the thickness direction;
part of the first conducting columns protrude out of the surface of the rest part of the first insulating layer, and the first insulating layer and the protruding part of the first conducting columns enclose to form the accommodating space.
Further, the manufacturing method of the circuit substrate comprises the following steps:
Providing a carrier plate, wherein the carrier plate comprises a substrate layer, a stripping layer and a metal layer, and the stripping layer is arranged between the metal layer and the substrate layer;
Adding a layer on the surface of the carrier plate to obtain a circuit substrate intermediate;
Separating the release layer and the metal layer; and
And removing the metal layer to obtain the independent circuit substrate.
Further, the second packaging substrate comprises a second insulator and a second outer line layer which are stacked, the second outer line layer comprises a plurality of connection pads, second solder balls are arranged on the connection pads, and the second solder balls are in contact with the first solder balls;
The step of "heat-melting the first solder ball" further includes:
and performing reflow soldering on the first solder ball and the second solder ball to form a conductive connecting piece, wherein the conductive connecting piece is electrically connected with the first packaging substrate and the second packaging substrate.
Further, the second package substrate further includes a second conductive body disposed in the second insulator, the second conductive body is connected to the second outer circuit layer, and the second conductive body is disposed corresponding to the connection pad.
The application also provides a packaging structure, which comprises a first packaging substrate, a packaging piece and a conductive connecting piece, wherein the first packaging substrate comprises a first insulator and a first conductor arranged in the first insulator; part of the first conducting body protrudes out of the surface of the first insulator, and the protruding part of the first conducting body and the first insulator enclose to form a containing space; the packaging piece comprises a second packaging substrate and an electronic element arranged on one side of the second packaging substrate, the second packaging substrate comprises a second insulator and a second outer line layer which are overlapped, and the electronic element is connected to the second outer line layer and is partially accommodated in the accommodating space; the conductive connecting piece is arranged between the first packaging substrate and the second packaging substrate and is electrically connected with the first conducting body and the second outer line layer.
Further, the circuit substrate further comprises two inner circuit layers arranged in the first insulator at intervals and a first outer circuit layer arranged at one side of the first insulator, the first insulator comprises a first insulating layer, a second insulating layer and a third insulating layer along the thickness direction, the first insulating layer is arranged at one side of one inner circuit layer, the second insulating layer is arranged between the two inner circuit layers, and the third insulating layer is arranged between the first outer circuit layer and the other inner circuit layer;
The first conductive body comprises a first conductive column arranged in the first insulating layer, a second conductive column arranged in the second insulating layer and a third conductive column arranged in the third insulating layer, wherein the first conductive column is connected to one side of one of the inner circuit layers, the second conductive column is connected with two inner circuit layers, and the third conductive column is connected with the first outer circuit layer and the other inner circuit layer;
part of the first conducting columns protrude out of the surface of the first insulating layer, and the first insulating layer and the protruding part of the first conducting columns enclose to form the accommodating space.
Further, the second outer line layer comprises a plurality of connection pads, and the conductive connection piece is connected to the surface of the first conductive pillar, which faces away from the first insulating layer, and the connection pads; the second packaging substrate further comprises a second conducting body arranged in the second insulator, the second conducting body is connected to the second outer circuit layer, and the second conducting body is arranged corresponding to the connecting pad.
Compared with the prior art, the manufacturing method of the packaging structure provided by the application has the advantages that the accommodating space is formed by removing part of the first insulator, part of the first conductor protrudes out of the surface of the first insulator, and the protruding part of the first conductor is equivalent to a copper column in the traditional process, but the manufacturing method is not limited by electroplating (such as current density, aperture aspect ratio and the like), so that the protruding part of the structure is uniform in height, and the quantity and the spacing density of the first conductor are easier to regulate and control. And the first conducting body part is buried in the first insulator, so that the bonding force is strong, the first conducting body part is not easy to fall off, and the reliability is good.
In addition, the accommodating space has a certain depth and can accommodate the electronic element, so that the size of the first solder ball is not required to be increased to ensure the height between the first packaging substrate and the electronic element, and the first solder ball with a small size can be adopted, thereby being more beneficial to high-density connection. The part of the first conducting body protruding out of the application is equivalent to a copper column in the traditional process, and is in point-to-face connection when being in butt joint with the packaging piece, so that the accuracy is good, and the yield of the packaging structure is high.
In addition, the first packaging substrate is manufactured by dividing the carrier plate in a mode of removing the carrier plate and etching the metal layer, so that the thickness of the first insulator can be greatly reduced, space is saved, and the thinning of the packaging structure is facilitated.
Drawings
Fig. 1 is a schematic cross-sectional view of a carrier plate with a metal layer formed on the surface thereof according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional view of the carrier plate shown in fig. 1 after a circuit substrate is formed on the surface thereof.
Fig. 3 is a schematic cross-sectional view of the circuit substrate shown in fig. 2 after a protective film is provided on the surface thereof.
FIG. 4 is a schematic cross-sectional view showing a process of separating the metal layer and the peeling layer shown in FIG. 3
Fig. 5 is a schematic cross-sectional view of a first intermediate obtained after the separation process shown in fig. 4.
Fig. 6 is a schematic cross-sectional view of the protective film of fig. 5 after removal.
Fig. 7 is a schematic cross-sectional view of a second intermediate obtained after removing a portion of the first insulating layer shown in fig. 6.
Fig. 8 is a schematic cross-sectional view of the second intermediate shown in fig. 7 after the first solder mask layer is disposed on one side of the second intermediate.
Fig. 9 is a schematic cross-sectional view of the first package substrate obtained after the first solder balls are disposed on one side of the first conductive via shown in fig. 8.
Fig. 10 is a schematic cross-sectional view illustrating a process of butting the first package substrate to the package shown in fig. 9.
Fig. 11 is a schematic cross-sectional view of a package structure obtained after reflow soldering the first solder ball and the second solder ball shown in fig. 10.
Description of the main reference signs
Packaging structure 300
Carrier plate 10
Substrate layer 101
Release layer 102
Metal layer 11
Circuit board 20
First insulator 21
First insulating layer 211
Second insulating layer 212
Third insulating layer 213
First inner circuit layer 22
First outer wiring layer 23
First connection pad 232
First conductive body 24
First conductive pillar 241
Second conductive pillar 242
Third conductive column 243
Protective film 25
First intermediate 26
Accommodation space R
Second intermediate 27
First solder mask layer 30
First opening 31
First solder ball 32
First package substrate 100
Package 200
Second package substrate 40
Second insulator 41
Second outer circuit layer 42
Second connection pad 422
Third connection pad 424
Second inner circuit layer 43
Third outside wiring layer 44
Second conductive body 45
Second solder mask layer 46
Second opening 462
Third solder mask layer 47
Second solder ball 48
Electronic component 50
Conductive connection 60
The application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may be present.
Referring to fig. 1 to 11, an embodiment of the present application provides a method for manufacturing a package structure 300, including the steps of:
Step S1: referring to fig. 1, a carrier 10 is provided, the carrier 10 includes a substrate layer 101 and a release layer 102 disposed on a surface of the substrate layer 101, and a metal layer 11 is formed on a surface of the release layer 102 facing away from the substrate layer 101.
The carrier 10 plays a bearing role, and the material of the base material layer 101 is not limited on the premise that the base material layer 101 satisfies a certain hardness.
The release layer 102 may be located on one surface of the substrate layer 101 or may be located on two opposite surfaces of the substrate layer 101. In this embodiment, the release layer 102 is located on two opposite surfaces of the substrate layer 101. The release layer 102 and the metal layer 11 need to be separated from each other during the subsequent process, so the release layer 102 functions to temporarily connect the base material layer 101 and the metal layer 11.
The material of the peeling layer 102 may be a metal material or an insulating material. In the present embodiment, the material of the release layer 102 is metallic copper, so that the hardness of the carrier 10 can be further enhanced.
In this embodiment, the number of the metal layers 11 is two, and the two release layers 102 are respectively located on the surfaces facing away from the substrate layer 101. The material of the metal layer 11 may be conductive materials such as copper, silver, nickel, etc., and the metal layer 11 facilitates the formation of subsequent circuit layers. In some embodiments, the metal layer 11 may also be omitted.
Step S2: referring to fig. 2, a circuit substrate 20 is formed on the surface of the carrier 10 by layering.
The circuit substrate 20 includes a first insulator 21, at least one first inner circuit layer 22, a first outer circuit layer 23, and a first conductive body 24, wherein the first outer circuit layer 23 is disposed on a surface of the first insulator 21 facing away from the carrier 10, the first inner circuit layer 22 is disposed in the first insulator 21, and the plurality of first conductive bodies 24 are electrically connected with the first inner circuit layer 22 and the first outer circuit layer 23.
In this embodiment, the number of the first inner circuit layers 22 is two. The first insulator 21 has a thickness direction a. Along the thickness direction a, the first insulator 21 includes a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213, the first insulating layer 211 is disposed between the metal layer 11 and the adjacent first inner circuit layers 22, the second insulating layer 212 is disposed between two of the first inner circuit layers 22, and the third insulating layer 213 is disposed between the first outer circuit layer 23 and the adjacent other of the first inner circuit layers 22. The first conductive body 24 includes a first conductive post 241 disposed in the first insulating layer 211, a second conductive post 242 disposed in the second insulating layer 212, and a third conductive post 243 disposed in the third insulating layer 213, wherein the first conductive post 241 is electrically connected to the metal layer 11 and the adjacent first inner circuit layer 22, the second conductive post 242 is electrically connected to two first inner circuit layers 22, and the third conductive post 243 is electrically connected to the first outer circuit layer 23 and the adjacent other first inner circuit layer 22.
The material of the first insulator 21 may be one selected from epoxy resin (PP), bismaleimide-triazine (BT) resin, polyphenylene oxide (Polyphenylene Oxide, PPO), polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), polyethylene naphthalate (Polyethylene Naphthalate, PEN), and the like. Specifically, the film can be prepreg (prepreg), FR-4 or ABF film (Ajinomoto build-up film) and the like.
In some embodiments, the circuit substrate 20 may be formed on a surface of one of the metal layers 11, and in other embodiments, the circuit substrates 20 may be formed on surfaces of both of the metal layers 11 independently of each other.
Step S3: referring to fig. 6, the carrier 10 is removed to obtain the circuit substrate 20.
Specifically, step S3 further includes:
step S31: referring to fig. 3, a protective film 25 is disposed on a side of the circuit substrate 20 away from the carrier 10, and the protective film 25 covers the first outer circuit layer 23.
Step S32: referring to fig. 4 and 5, the release layer 102 and the metal layer 11 are separated to remove the carrier plate 10, and then the metal layer 11 is etched away to obtain the first intermediate 26.
The metal layer 11 is etched completely, and the surface of the first via 241 facing away from the first inner circuit layer 22 is substantially flush with the surface of the first insulating layer 211.
Step S33: referring to fig. 5 and 6, the protective film 25 is removed to obtain the independent circuit substrate 20.
In step S4, referring to fig. 7, a portion of the first insulating layer 211 is removed to obtain a second intermediate 27.
Specifically, a portion of the first insulating layer 211 is removed from the side of the circuit substrate 20 provided with the first conductive pillar 241 by plasma photoresist (also called plasma) process along the thickness direction a of the first insulating layer 21 according to a predetermined depth, a portion of the first conductive pillar 241 protrudes from the surface of the second intermediate 27, and a receiving space R is defined between the protruding portion of the first conductive pillar 241 and the first insulating layer 211.
The accommodating space R has a depth H, which is smaller than the thickness of the first insulating layer 211.
Step S5: referring to fig. 8, a first solder mask layer 30 is disposed on a side of the second intermediate body 27 facing away from the accommodating space R.
The first outer circuit layer 23 includes a plurality of first connection pads 232 disposed at intervals. The first solder mask layer 30 has a plurality of first openings 31, and the first connection pads 232 are exposed from the bottoms of the first openings 31.
In this embodiment, the first connection pad 232 may be used for electrically connecting to an external configuration unit, such as an electronic device, other circuit board, package substrate, or the like.
Step S6: referring to fig. 9, a first solder ball 32 is disposed on a surface of the first conductive pillar 241 facing away from the first insulator 21, so as to obtain a first package substrate 100.
Step S7: referring to fig. 10, a package 200 is provided, and the package 200 is abutted against the first package substrate 100.
The package 200 includes a second package substrate 40 and an electronic component 50 disposed on one side of the second package substrate 40, and connects the first package substrate 100 and the package 200, and a portion of the electronic component 50 is accommodated in the accommodating space R.
In this embodiment, the second package substrate 40 includes a second insulator 41, a second outer circuit layer 42, two second inner circuit layers 43, a third outer circuit layer 44, and a plurality of second vias 45, wherein the second outer circuit layer 42 and the third outer circuit layer 44 are respectively disposed on two opposite surfaces of the second insulator 41, the two second inner circuit layers 43 are disposed in the second insulator 41 at intervals, and the second vias 45 electrically conduct the second outer circuit layer 42, the two second inner circuit layers 43, and the third outer circuit layer 44. The second outer circuit layer 42 includes at least two second connection pads 422 and a plurality of third connection pads 424 disposed at intervals, and the second connection pads 422 are disposed corresponding to the first conductive pillars 241.
The second package substrate 40 is further provided with a second solder mask layer 46 and a third solder mask layer 47 on opposite sides thereof, the second solder mask layer has a plurality of second openings 462, and the second connection pads 422 and the third connection pads 424 are exposed from the bottoms of the second openings 462. The electronic component 50 is disposed on the third connection pad 424. The second connection pad 422 is provided with a second solder ball 48, and the second solder ball 48 is in contact with the first solder ball 32.
Step S8: referring to fig. 11, the second solder balls 48 and the first solder balls 32 are reflowed to form conductive connectors 60, so that the first package substrate 100 and the second package substrate 40 are electrically connected through the conductive connectors 60 to obtain a package structure 300.
Compared with the prior art, the manufacturing method of the packaging structure provided by the application has the following advantages:
(1) By removing a portion of the first insulator 21 to form the accommodating space R, and making a portion of the first conductive pillars 241 protrude from the surface of the first insulator 21, the protruding portion of the first conductive pillars 241 corresponds to a copper pillar in a conventional process, but the manufacturing method in the present application is not limited by an electroplating process (such as current density, aperture aspect ratio, etc.), so that the protruding portion has a uniform structure height, and the number and pitch density of the first conductive pillars 241 are easier to regulate. And the first conductive pillar 241 is partially embedded in the first insulator 21, so that the first conductive pillar is not easy to fall off, and has good reliability.
(2) Since the accommodating space R has a certain depth and can accommodate the electronic component 50, the size of the first solder ball 32 does not need to be increased to ensure the height between the first package substrate 100 and the electronic component 50, and the first solder ball 32 with a small size can be used to facilitate high-density connection.
(3) In the application, the protruding portion of the first conductive pillar 241 corresponds to a copper pillar in the conventional process, the accuracy is high when the first conductive pillar is in butt joint with the package 200, and the yield of the package structure 300 is high. The second solder balls 48 are directly soldered with the first solder balls 32 by reflow without requiring a complicated production process of copper plating columns, and the method is simple to operate and low in production cost.
(4) By dividing the first package substrate 100 by removing the carrier 10 and etching the metal layer 11, the thickness of the first insulator 21 can be greatly reduced, which saves space and is beneficial to the thinning of the package structure 300.
Referring to fig. 11, an embodiment of the present application further provides a package structure 300 manufactured by the above manufacturing method, where the package structure 300 includes a first package substrate 100 and a package 200 stacked together, and a conductive connection member 60 disposed between the first package substrate 100 and the package 200.
The first package substrate 100 includes a first insulator 21, at least one first inner circuit layer 22, a first outer circuit layer 23, a plurality of first vias 24, a first solder mask layer 30 and first solder balls 32. The first outer circuit layer 23 is disposed on one surface of the first insulator 21, the first inner circuit layer 22 is disposed in the first insulator 21, and the first via 24 is electrically connected to the first inner circuit layer 22 and the first outer circuit layer 23.
In this embodiment, the number of the first inner circuit layers 22 is two. The first insulator 21 has a thickness direction a, along which the first insulator 21 includes a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213, the first insulating layer 211 is disposed between the metal layer 11 and the adjacent first inner circuit layers 22, the second insulating layer 212 is disposed between two of the first inner circuit layers 22, and the third insulating layer 213 is disposed between the first outer circuit layer 23 and the adjacent other of the first inner circuit layers 22. The first conductive body 24 includes a first conductive post 241 disposed in the first insulating layer 211, a second conductive post 242 disposed in the second insulating layer 212, and a third conductive post 243 disposed in the third insulating layer 213, wherein the first conductive post 241 is electrically connected to the metal layer 11 and the adjacent first inner circuit layer 22, the second conductive post 242 is electrically connected to two first inner circuit layers 22, and the third conductive post 243 is electrically connected to the first outer circuit layer 23 and the adjacent other first inner circuit layer 22.
The first solder balls 32 are disposed on a surface of the first conductive pillars 241 facing away from the first insulator 21. The first conductive pillars 241 protrude from the surface of the first insulating layer 211, and a portion of the first conductive pillars 241 and the first insulating layer 211 enclose a receiving space R. The first outer circuit layer 23 includes a plurality of first connection pads 232. The first solder mask layer 30 is disposed on a side of the circuit substrate 20 facing away from the accommodating space R, the first solder mask layer 30 has a plurality of first openings 31, and the first connection pads 232 are exposed from the bottoms of the first openings 31.
The package 200 includes a second package substrate 40 and an electronic component 50 disposed on one side of the second package substrate 40, and connects the first package substrate 100 and the package 200, and a portion of the electronic component 50 is accommodated in the accommodating space R.
The second package substrate 40 includes a second insulator 41, a second outer circuit layer 42, two second inner circuit layers 43, a third outer circuit layer 44, and a second conductive body 45, wherein the second outer circuit layer 42 and the third outer circuit layer 44 are respectively disposed on two opposite surfaces of the second insulator 41, the two second inner circuit layers 43 are disposed in the second insulator 41 at intervals, and the second conductive body 45 electrically connects the second outer circuit layer 42, the two second inner circuit layers 43, and the third outer circuit layer 44. The second outer circuit layer 42 includes at least two second connection pads 422 and a plurality of third connection pads 424, and the second connection pads 422 are disposed corresponding to the first conductive pillars 241.
The second package substrate 40 is further provided with a second solder mask layer 46 and a third solder mask layer 47 on opposite sides thereof, the second solder mask layer has a plurality of second openings 462, and the second connection pads 422 and the third connection pads 424 are exposed from the bottoms of the second openings 462. The electronic component 50 is disposed on the third connection pad 424. The second connection pad 422 is provided with a second solder ball 48, the second solder ball 48 and the first solder ball 32 are soldered to form the conductive connection piece 60, and the first package substrate 100 and the second package substrate 40 are electrically connected through the conductive connection piece 60.
Further, other variations within the spirit of the present application will occur to those skilled in the art, and it is intended, of course, that such variations be included within the scope of the application as claimed herein.
Claims (10)
1. The manufacturing method of the packaging structure is characterized by comprising the following steps of:
providing a circuit substrate, wherein the circuit substrate comprises a first insulator and a first conductor arranged in the first insulator;
removing part of the first insulator, so that part of the first conductor protrudes out of the surface of the rest first insulator, and the protruding part of the first conductor and the first insulator enclose to form a containing space;
arranging a first solder ball on the surface of the first conducting body, which is away from the first insulator, so as to obtain a first packaging substrate;
Arranging a packaging piece on the first packaging substrate, wherein the packaging piece comprises a second packaging substrate and an electronic element arranged on one side of the second packaging substrate; the first solder balls are in contact with the second packaging substrate, and at least part of the electronic elements are accommodated in the accommodating space;
and heating and melting the first solder balls, and electrically connecting the first conducting body and the second packaging substrate by the cooled and solidified first solder balls to obtain the packaging structure.
2. The method of manufacturing a package structure of claim 1, wherein the step of removing a portion of the first insulator comprises:
A portion of the first insulator is removed using a plasma desmear process.
3. The method of manufacturing a package structure according to claim 1, wherein the circuit substrate further includes two inner circuit layers disposed in the first insulator at intervals, and a first outer circuit layer disposed on one side of the first insulator, the first insulator including a first insulating layer disposed on one side of one of the inner circuit layers, a second insulating layer disposed between the two inner circuit layers, and a third insulating layer disposed between the first outer circuit layer and the other inner circuit layer in a thickness direction;
The step of "removing a portion of the first insulator" includes: and removing part of the first insulating layer.
4. The method of manufacturing a package structure according to claim 3, wherein the first conductive body includes a first conductive pillar penetrating through the first insulating layer, a second conductive pillar disposed in the second insulating layer, and a third conductive pillar disposed in the third insulating layer, the first conductive pillar being disposed on one side of one of the inner circuit layers in the thickness direction, the second conductive pillar being connected between the two inner circuit layers in the thickness direction, the third conductive pillar being disposed between the first outer circuit layer and the other inner circuit layer in the thickness direction;
part of the first conducting columns protrude out of the surface of the rest part of the first insulating layer, and the first insulating layer and the protruding part of the first conducting columns enclose to form the accommodating space.
5. The method for manufacturing a package structure according to claim 1, wherein the method for manufacturing a circuit substrate comprises the steps of:
Providing a carrier plate, wherein the carrier plate comprises a substrate layer, a stripping layer and a metal layer, and the stripping layer is arranged between the metal layer and the substrate layer;
Adding a layer on the surface of the carrier plate to obtain a circuit substrate intermediate;
Separating the release layer and the metal layer; and
And removing the metal layer to obtain the independent circuit substrate.
6. The method of manufacturing a package structure according to claim 1, wherein the second package substrate includes a second insulator and a second outer circuit layer stacked together, the second outer circuit layer includes a plurality of connection pads, second solder balls are disposed on the connection pads, and the second solder balls are in contact with the first solder balls;
The step of "heat-melting the first solder ball" further includes:
and performing reflow soldering on the first solder ball and the second solder ball to form a conductive connecting piece, wherein the conductive connecting piece is electrically connected with the first packaging substrate and the second packaging substrate.
7. The method of claim 6, wherein the second package substrate further comprises a second conductive body disposed in the second insulator, the second conductive body is connected to the second outer circuit layer, and the second conductive body is disposed corresponding to the connection pad.
8. A package structure, comprising:
The first packaging substrate comprises a first insulator and a first conducting body arranged in the first insulator, part of the first conducting body protrudes out of the surface of the first insulator, and the protruding part of the first conducting body and the first insulator are enclosed to form a containing space;
The packaging piece comprises a second packaging substrate and an electronic element arranged on one side of the second packaging substrate, the second packaging substrate comprises a second insulator and a second outer line layer which are overlapped, and the electronic element is connected to the second outer line layer and is partially accommodated in the accommodating space;
The conductive connecting piece is arranged between the first packaging substrate and the second packaging substrate and is electrically connected with the first conducting body and the second outer line layer.
9. The package structure of claim 8, wherein the circuit substrate further comprises two inner circuit layers disposed in the first insulator at intervals and a first outer circuit layer disposed on one side of the first insulator, the first insulator including a first insulating layer disposed on one side of one of the inner circuit layers, a second insulating layer disposed between the two inner circuit layers, and a third insulating layer disposed between the first outer circuit layer and the other of the inner circuit layers in a thickness direction;
The first conductive body comprises a first conductive column arranged in the first insulating layer, a second conductive column arranged in the second insulating layer and a third conductive column arranged in the third insulating layer, wherein the first conductive column is connected to one side of one of the inner circuit layers, the second conductive column is connected with two inner circuit layers, and the third conductive column is connected with the first outer circuit layer and the other inner circuit layer; part of the first conducting columns protrude out of the surface of the first insulating layer, and the first insulating layer and the protruding part of the first conducting columns enclose to form the accommodating space.
10. The package structure of claim 9, wherein the second outer line layer includes a plurality of connection pads, the conductive connection being connected to a surface of the first via away from the first insulating layer and the connection pads; the second packaging substrate further comprises a second conducting body arranged in the second insulator, the second conducting body is connected to the second outer circuit layer, and the second conducting body is arranged corresponding to the connecting pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211293331.XA CN117954328A (en) | 2022-10-21 | 2022-10-21 | Packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211293331.XA CN117954328A (en) | 2022-10-21 | 2022-10-21 | Packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117954328A true CN117954328A (en) | 2024-04-30 |
Family
ID=90803662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211293331.XA Pending CN117954328A (en) | 2022-10-21 | 2022-10-21 | Packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117954328A (en) |
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2022
- 2022-10-21 CN CN202211293331.XA patent/CN117954328A/en active Pending
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