CN117950972A - Simulation verification method and device for chip, computer equipment and storage medium - Google Patents
Simulation verification method and device for chip, computer equipment and storage medium Download PDFInfo
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Abstract
The invention relates to a simulation verification method, a simulation verification device, simulation verification equipment and a simulation verification storage medium for a chip, wherein a UVM verification environment of the chip to be verified is generated; generating a UVM test case by using an automatic script, and adding the UVM test case into a UVM verification environment of a chip to be verified; configuring and submitting a simulation task to a UVM verification environment by using an automatic script to perform simulation test; the high automation of the chip simulation verification work is realized, the technical effect of the work efficiency of the chip simulation verification work is improved by monitoring the real-time state of the simulation server for performing the simulation test, and the technical problem that the simulation verification work cannot be delivered on time due to the fact that the test vectors in the SOC project are very large is solved.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a method and apparatus for simulating and verifying a chip, a computer device, and a storage medium.
Background
SoC validation work refers to a series of tests and checks performed during System on Chip (SoC) development to ensure that such highly integrated chips meet design requirements in terms of functionality and performance. While SoC is a technology that integrates multiple components in a traditional computer or electronic device onto a single chip, for example: the cpu, the graphics processor, the memory, the i/o controller, etc. are integrated on a single chip.
However, the verification work has strong timeliness, the project plan is usually formulated according to the difficulty of the project and the project node of the Foundation manufacturer, and after the project time point is determined, the verification personnel is required to complete all simulation verification works before the specified time point, especially in some medium and large-scale SOC projects, the required test vectors are very large, so that the workload of the simulation verification work is suddenly increased, and the simulation verification result cannot be delivered on time.
Disclosure of Invention
The invention mainly aims to provide a simulation verification method, device, computer equipment and storage medium for a chip, which realize the high automation of the chip simulation verification work, improve the work efficiency of the chip simulation verification work and solve the technical problem that the simulation verification work cannot be delivered on time due to a great number of test vectors in an SOC project by utilizing the characteristics of a UVM environment to support the highly-automatic verification process and adopting an automatic script to automatically generate test cases, automatically configure the simulation tasks and automatically submit the simulation tasks.
In order to achieve the above object, the present invention provides a simulation verification method for a chip, comprising the steps of: generating a UVM verification environment of a chip to be verified; generating a UVM test case by using an automation script, and adding the UVM test case into a UVM verification environment of the chip to be verified; and configuring and submitting a simulation task to the UVM verification environment by using the automation script to perform simulation test.
Further, generating a UVM test case by using an automation script, and adding the UVM test case to a UVM verification environment of the chip to be verified, including: generating a UVM test case by using an automatic script, and writing a software program according to the requirements of the chip to be verified, wherein the software program is used for simulating the operation conditions and the application scene of the chip to be verified; and adding the UVM test case and the software program into a UVM verification environment of the chip to be verified.
Further, before generating the UVM test case using the automation script, the method further comprises: and writing the automation script by adopting a preset script language, wherein the preset script language comprises two languages of Perl and Python.
Further, after generating the UVM test case using the automation script, the method further comprises: and adding the test vectors in the UVM test case into a JSON list for management.
Further, configuring and submitting simulation tasks to the UVM verification environment for simulation testing using the automation script, including: configuring a plurality of simulation tasks using the automation script; sequentially submitting the simulation tasks to a simulation server in the UVM verification environment for simulation test; judging whether the simulation tasks are completely submitted to the simulation server for simulation test; under the condition that the simulation tasks are not completely submitted, continuing to sequentially submit the simulation tasks to a simulation server in the UVM verification environment for simulation test; and prompting the target object to verify completion under the condition that the simulation tasks are submitted completely.
Further, after sequentially submitting the simulation tasks to a simulation server in the UVM verification environment for simulation testing, the method includes: acquiring real-time state information of the simulation server; judging whether the load of the simulation server exceeds a preset threshold according to the real-time state information of the simulation server; under the condition that the load of the simulation server exceeds a preset threshold, stopping submitting the simulation task to the simulation server in the UVM verification environment for simulation test, and returning to the step of acquiring real-time state information of the simulation server; and under the condition that the load of the simulation server does not exceed a preset threshold value, continuously executing the step of submitting the simulation task to the simulation server in the UVM verification environment for simulation test.
Further, after acquiring the real-time status information of the simulation server, the method further comprises: determining whether the simulation server is in an abnormal state according to the real-time state information of the simulation server; and under the condition that the simulation server is in an abnormal state, sending an alarm prompt to a target object.
The invention provides a simulation verification device of a chip, which comprises: the first generation unit is used for generating a UVM verification environment of the chip to be verified; the second generation unit is used for generating a UVM test case by using an automatic script and adding the UVM test case into a UVM verification environment of the chip to be verified; and the simulation test unit is used for configuring and submitting a simulation task to the UVM verification environment by using the automation script to perform simulation test.
The invention also provides a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of any of the methods described above when the computer program is executed.
The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method of any of the preceding claims.
The simulation verification method, the device, the computer equipment and the storage medium of the chip provided by the invention utilize the characteristics of the highly-automatic verification process supported by the UVM environment, automatically generate test cases, automatically configure simulation tasks and automatically submit the simulation tasks by adopting the automatic script, realize the high automation of the chip simulation verification work, improve the work efficiency of the chip simulation verification work, and solve the technical problem that the simulation verification work cannot be delivered on time due to a very large number of test vectors in the SOC project.
Drawings
FIG. 1 is a schematic diagram showing steps of a simulation verification method of a chip according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a portion of a simulation verification method of a chip according to an embodiment of the invention;
FIG. 3 is a block diagram of a simulation verification apparatus of a chip in an embodiment of the present invention;
fig. 4 is a block diagram schematically illustrating a structure of a computer device according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The method for chip simulation verification provided by the invention is implemented by taking computer equipment as an execution main body.
Referring to fig. 1, a schematic diagram of steps of a method for chip simulation verification according to the present invention includes the following steps:
s1, generating a UVM verification environment of a chip to be verified.
UVM verification environment is an environment dedicated to Integrated Circuit (IC) and system-on-a-chip (SoC) design verification, based on the UVM (Universal Verification Methodology) framework. UVM is a widely adopted hardware validation standard that provides a set of structured methods to create an efficient, reusable test environment. The main purpose of the UVM verification environment is to ensure that the chip design meets its intended functional and performance requirements.
Key components of the UVM verification environment include: 1. test standard (Testbench): all UVM components for testing chips, such as agents, monitors (monitors), drivers, and verifiers (checkers); 2. agent (Agents): each agent typically contains a sequencer (sequencer), driver, monitor, and verifier (checker), which are used to simulate and monitor interface interactions with the Device Under Test (DUT); 3. test Sequences (Sequences): defining a series of operations or transactions for generating input stimuli for the device under test; 4. verification mechanism (Scoreboards AND CHECKERS): for checking and verifying whether the output of the device under test meets expectations; 5. coverage collection (Coverage Collection): for evaluating which parts of the design the test case covers and determining if more tests are needed to completely cover the design; 6. environment Configuration (Configuration): allowing test engineers to configure and modify the behavior of the test environment to accommodate different test requirements.
S2, generating a UVM test case by using an automatic script, and adding the UVM test case into a UVM verification environment of the chip to be verified.
UVM test cases (Universal Verification Methodology TEST CASES) are a specific set of test scenarios used in the verification process of Integrated Circuit (IC) and system-on-a-chip (SoC) designs. These test cases are written in accordance with the UVM framework, aimed at verifying and ensuring that the chip design meets its intended functional and performance requirements.
The UVM test case comprises the following key components: 1. test scenario: specific test scenario descriptions, including certain specific aspects of the chip or function to be verified; 2. input data and stimulus: input data and stimulus sequences for driving a Device Under Test (DUT); 3. expected behavior: for a given input and stimulus, the expected behavior or output that the device should exhibit; 4. check point: a check point in the test case is used for confirming whether the actual behavior of the equipment accords with the expectation; 5. coverage and performance index: the test cases aim at achieving coverage and performance indexes.
It should be noted that: the purpose of adding the UVM test cases to the UVM verification environment of the chip to be verified is to execute the test cases in the verification environment, so that the function verification and the simulation test are carried out on the chip to be verified. By adding the test cases into the verification environment, various scenes and conditions can be simulated, whether the functions of the chip to be verified meet the design requirements or not can be verified, and the chip can work normally under various conditions. This helps to ensure the stability, reliability and correctness of the chip, and improves the quality and reliability of the chip design.
S3, configuring and submitting a simulation task to the UVM verification environment for simulation test by using the automation script.
The invention utilizes the characteristics of the highly-automatic verification process supported by the UVM environment, adopts the automatic script to automatically generate the test case, automatically configure the simulation task and automatically submit the simulation task, realizes the high automation of the chip simulation verification work, improves the working efficiency of the chip simulation verification work, and solves the technical problem that the simulation verification work cannot be delivered on time due to the fact that the test vectors in the SOC project are very large.
In addition, the UVM verification environment includes the following advantages: 1. scalability: the test environment can add or modify components as needed to accommodate new test requirements; 2. accurate error diagnosis: UVM provides error detection and diagnostic tools that help verify engineers accurately identify and repair problems; the above advantages can improve the working efficiency of the chip simulation verification work.
In one embodiment, generating a UVM verification environment for a chip to be verified includes: creating a verification framework of the UVM verification environment, configuring environment variables of the UVM verification environment, and updating a verification component of the UVM verification environment to obtain the UVM verification environment.
In particular, the authentication framework that creates a UVM authentication environment may include: installing and configuring a UVM library and a simulation tool; creating a UVM project structure comprising a test benchmark, an agent, a monitor, a verifier and the like; UVM agents and components are defined to simulate different parts of the SoC.
Specifically, configuring the environment variables of the UVM verification environment may include: editing setup.csh scripts, setting environment variables to point to paths of the UVM library and simulation tools, and further ensuring that all necessary libraries and dependent items are correctly referenced.
In particular, the authentication component that updates the UVM authentication environment may include: filelist is modified to ensure that the UVM verification environment contains all necessary design and verification files, setting backdoor access to facilitate more efficient access to data and verification data.
In one embodiment, generating a UVM test case using an automation script and adding the UVM test case to a UVM verification environment of the chip to be verified, including: generating a UVM test case by using an automatic script, and writing a software program according to the chip requirement, wherein the software program is used for simulating the operation condition and the application scene of the chip; and adding the UVM test case and the software program into a UVM verification environment of the chip to be verified.
According to the embodiment, the software program simulating the operation condition and the application scene of the chip to be verified is added to the UVM verification environment of the chip to be verified together with the UVM test case, so that the technical problem that an independent hardware test or an independent software test cannot be fully covered is solved, the more comprehensive test coverage rate is provided, the hardware problem which only occurs under the specific software condition is conveniently revealed, the accuracy and the reliability of test verification are enhanced, and the problem in design can be found and repaired earlier.
In one embodiment, before generating the UVM test case using the automation script, the method further comprises: and writing the automation script by adopting a preset script language, wherein the preset script language comprises two languages of Perl and Python.
Perl and Python are two powerful scripting languages, and both Perl and Python provide rich libraries and APIs to support external program calls and data processing, meaning that data can be called or passed directly from a software program into a script, and vice versa.
By utilizing the characteristics of Perl and Python, the technical effect that the test case generated by using the script files written by the Perl and Python languages can be coupled with the software program more conveniently is realized, and the working efficiency of chip simulation verification work is further improved.
In one embodiment, after generating the UVM test case using the automation script, the method further comprises: and adding the test vectors in the UVM test case into a JSON list for management.
JSON (JavaScript Object Notation) is a lightweight data exchange format that is easy to read and write, and easy to machine parse and generate. It is text-based and can be used to represent structured data. The use of JSON format to manage test cases has the following advantages: 1. the JSON format is clear and readable, so that the complex test vector is managed more intuitively and easily; 2. JSON can effectively represent hierarchical and structured data, which is useful for describing different aspects of a test vector (e.g., input parameters, expected results, etc.); 3. the JSON format allows for easy addition, modification and deletion of test vectors, which is important to cope with iterative changes in SoC design; 4. the JSON format can be easily integrated with scripting languages such as Perl, python and the like and other automation tools to support an automation test flow.
The JSON list management test vector specifically comprises the following contents: 1. defining the attribute of each test vector in the JSON file, wherein the attribute comprises a test name, input data, configuration parameters, expected results and the like; 2. updating or adding a new test vector by editing a JSON file according to the change of the SoC design or the new test requirement; 3. using an automation script to read test vector data in the JSON file, and executing a corresponding test case; 4. after the test is completed, the result can be recorded back to the JSON file, or a report in JSON format is used to summarize the test result; 5. the JSON file is incorporated into the version control system to track the history of changes to the test vector.
In other words, by using JSON format to manage test vectors, the efficiency of organizing, accessing, and maintaining test data in the SoC verification process can be improved, thereby speeding up the verification period and improving the accuracy of the test.
In one embodiment, referring to fig. 2, a flow chart of a method for chip simulation verification according to the present invention is provided, the method for configuring and submitting a simulation task to the UVM verification environment for simulation test using the automation script includes: configuring a plurality of simulation tasks using the automation script; sequentially submitting the simulation tasks to a simulation server in the UVM verification environment for simulation test; judging whether the simulation tasks are completely submitted to the simulation server for simulation test; under the condition that the simulation tasks are not completely submitted, continuing to sequentially submit the simulation tasks to a simulation server in the UVM verification environment for simulation test; and prompting the target object to verify completion under the condition that the simulation tasks are submitted completely.
According to the embodiment, the simulation tasks are submitted to the simulation server in the UVM verification environment in sequence for simulation test, the state of the simulation tasks is checked in real time, namely whether the simulation tasks are submitted to the simulation server for simulation test is judged in real time, and under the condition that the simulation tasks are not submitted in sequence, the simulation tasks are submitted to the simulation server in the UVM verification environment for simulation test continuously, so that the time interval for submitting the simulation tasks is reduced, and convergence of simulation verification is accelerated.
In one embodiment, referring to fig. 2, which is a schematic flow chart of a method for chip simulation verification according to the present invention, after the simulation tasks are sequentially submitted to a simulation server in the UVM verification environment for performing a simulation test, the method includes: acquiring real-time state information of the simulation server; judging whether the load of the simulation server exceeds a preset threshold according to the real-time state information of the simulation server; under the condition that the load of the simulation server exceeds a preset threshold, stopping submitting the simulation task to the simulation server in the UVM verification environment for simulation test, and returning to the step of acquiring real-time state information of the simulation server; and under the condition that the load of the simulation server does not exceed a preset threshold value, continuously executing the step of submitting the simulation task to the simulation server in the UVM verification environment for simulation test.
According to the embodiment, whether the simulation server is overloaded or not is monitored in real time by acquiring the real-time state information of the simulation server and according to the real-time state information of the simulation server, so that the simulation task is stopped to be submitted under the condition that the simulation server is overloaded, and the simulation task is continuously submitted under the condition that the simulation server is monitored not to be overloaded any more, overload of the server is avoided, resource allocation is optimized, flexibility of task scheduling is improved, and simulation verification efficiency is guaranteed.
In one embodiment, referring to fig. 2, a flow chart of a method for chip simulation verification according to the present invention is provided, and after obtaining real-time status information of a simulation server, the method further includes: determining whether the simulation server is in an abnormal state according to the real-time state information of the simulation server; and under the condition that the simulation server is in an abnormal state, sending an alarm prompt to a target object.
According to the embodiment, the state of the simulation server is monitored in real time, and an alarm prompt is sent to the target object when the abnormal state is detected, so that the abnormal state of the simulation server, such as overload, performance degradation or other faults, can be immediately identified, and the risk that the problem is ignored is reduced; meanwhile, when abnormality is detected, an alarm is sent immediately, so that related personnel or a system can be ensured to respond quickly, and necessary intervention measures are adopted; furthermore, the simulation server resources can be better managed, and the problems caused by resource abuse or improper management are avoided.
In a word, the method of the real-time monitoring and alarming mechanism provides strong support for managing and maintaining the simulation server, so that higher efficiency and reliability are brought to the SoC verification project.
Referring to fig. 3, a schematic structural diagram of a simulation verification device for a chip according to the present invention includes:
A first generating unit 1, configured to generate a UVM verification environment of a chip to be verified;
The second generating unit 2 is used for generating a UVM test case by using an automation script and adding the UVM test case into a UVM verification environment of the chip to be verified;
and the simulation test unit 3 is used for configuring and submitting a simulation task to the UVM verification environment by using the automation script to perform simulation test.
In this embodiment, for specific implementation of each unit in the above embodiment of the apparatus, please refer to the description in the above embodiment of the method, and no further description is given here.
Referring to fig. 4, in an embodiment of the present invention, there is further provided a computer device, which may be a server, and the internal structure of the computer device may be as shown in fig. 4. The computer device includes a processor, a memory, a display screen, an input device, a network interface, and a database connected by a system bus. Wherein the computer is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used for communicating with an external terminal through a network connection. Which computer program, when being executed by a processor, carries out the above-mentioned method.
It will be appreciated by those skilled in the art that the architecture shown in fig. 4 is merely a block diagram of a portion of the architecture in connection with the present inventive arrangements and is not intended to limit the computer devices to which the present inventive arrangements are applicable.
An embodiment of the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above method. It is understood that the computer readable storage medium in this embodiment may be a volatile readable storage medium or a nonvolatile readable storage medium.
In summary, for the embodiment of the invention, the characteristics of highly-automated verification process are supported by using the UVM environment, and the automatic script is adopted to automatically generate test cases, automatically configure simulation tasks and automatically submit the simulation tasks, so that the highly-automated chip simulation verification work is realized, the work efficiency of the chip simulation verification work is improved, and the technical problem that the simulation verification work cannot be delivered on time due to the fact that the test vectors in the SOC project are very many is solved.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium provided by the present invention and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article, or method that comprises the element.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (10)
1. The simulation verification method of the chip is characterized by comprising the following steps of:
Generating a UVM verification environment of a chip to be verified;
Generating a UVM test case by using an automation script, and adding the UVM test case into a UVM verification environment of the chip to be verified;
And configuring and submitting a simulation task to the UVM verification environment by using the automation script to perform simulation test.
2. The method of claim 1, wherein generating UVM test cases using an automation script and adding the UVM test cases to a UVM verification environment of the chip to be verified comprises:
Generating a UVM test case by using an automatic script, and writing a software program according to the requirements of the chip to be verified, wherein the software program is used for simulating the operation conditions and the application scene of the chip to be verified;
and adding the UVM test case and the software program into a UVM verification environment of the chip to be verified.
3. The simulation verification method of claim 2, wherein prior to generating the UVM test case using the automation script, the method further comprises:
and writing the automation script by adopting a preset script language, wherein the preset script language comprises two languages of Perl and Python.
4. The simulation verification method of claim 1, wherein after generating the UVM test case using the automation script, the method further comprises:
And adding the test vectors in the UVM test case into a JSON list for management.
5. The simulation verification method of claim 1, wherein configuring and submitting simulation tasks into the UVM verification environment for simulation testing using the automation script comprises:
configuring a plurality of simulation tasks using the automation script;
Sequentially submitting the simulation tasks to a simulation server in the UVM verification environment for simulation test;
judging whether the simulation tasks are completely submitted to the simulation server for simulation test;
Under the condition that the simulation tasks are not completely submitted, continuing to sequentially submit the simulation tasks to a simulation server in the UVM verification environment for simulation test;
and prompting the target object to verify completion under the condition that the simulation tasks are submitted completely.
6. The simulation verification method of claim 5, wherein after sequentially submitting the simulation tasks to simulation servers in the UVM verification environment for simulation testing, the method comprises:
Acquiring real-time state information of the simulation server;
Judging whether the load of the simulation server exceeds a preset threshold according to the real-time state information of the simulation server;
Under the condition that the load of the simulation server exceeds a preset threshold, stopping submitting the simulation task to the simulation server in the UVM verification environment for simulation test, and returning to the step of acquiring real-time state information of the simulation server;
And under the condition that the load of the simulation server does not exceed a preset threshold value, continuously executing the step of submitting the simulation task to the simulation server in the UVM verification environment for simulation test.
7. The simulation verification method of claim 6, wherein after acquiring the real-time status information of the simulation server, the method further comprises:
Determining whether the simulation server is in an abnormal state according to the real-time state information of the simulation server;
and under the condition that the simulation server is in an abnormal state, sending an alarm prompt to a target object.
8. A simulation verification apparatus for a chip, comprising:
The first generation unit is used for generating a UVM verification environment of the chip to be verified;
the second generation unit is used for generating a UVM test case by using an automatic script and adding the UVM test case into a UVM verification environment of the chip to be verified;
And the simulation test unit is used for configuring and submitting a simulation task to the UVM verification environment by using the automation script to perform simulation test.
9. A computer device comprising a memory and a processor, the memory having stored therein a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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